src/ds/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/io.h>
7
8#include <mgba/internal/ds/ds.h>
9#include <mgba/internal/ds/ipc.h>
10
11mLOG_DEFINE_CATEGORY(DS_IO, "DS I/O");
12
13static void _DSHaltCNT(struct DSCommon* dscore, uint8_t value) {
14 switch (value >> 6) {
15 case 0:
16 default:
17 break;
18 case 1:
19 mLOG(DS_IO, STUB, "Enter GBA mode not supported");
20 break;
21 case 2:
22 ARMHalt(dscore->cpu);
23 break;
24 case 3:
25 mLOG(DS_IO, STUB, "Enter sleep mode not supported");
26 break;
27 }
28}
29
30static uint32_t DSIOWrite(struct DSCommon* dscore, uint32_t address, uint16_t value) {
31 switch (address) {
32 // Video
33 case DS_REG_DISPSTAT:
34 DSVideoWriteDISPSTAT(dscore, value);
35 break;
36
37 // DMA Fill
38 case DS_REG_DMA0FILL_LO:
39 case DS_REG_DMA0FILL_HI:
40 case DS_REG_DMA1FILL_LO:
41 case DS_REG_DMA1FILL_HI:
42 case DS_REG_DMA2FILL_LO:
43 case DS_REG_DMA2FILL_HI:
44 case DS_REG_DMA3FILL_LO:
45 case DS_REG_DMA3FILL_HI:
46 break;
47
48 // Timers
49 case DS_REG_TM0CNT_LO:
50 GBATimerWriteTMCNT_LO(&dscore->timers[0], value);
51 return 0x20000;
52 case DS_REG_TM1CNT_LO:
53 GBATimerWriteTMCNT_LO(&dscore->timers[1], value);
54 return 0x20000;
55 case DS_REG_TM2CNT_LO:
56 GBATimerWriteTMCNT_LO(&dscore->timers[2], value);
57 return 0x20000;
58 case DS_REG_TM3CNT_LO:
59 GBATimerWriteTMCNT_LO(&dscore->timers[3], value);
60 return 0x20000;
61
62 case DS_REG_TM0CNT_HI:
63 value &= 0x00C7;
64 DSTimerWriteTMCNT_HI(&dscore->timers[0], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM0CNT_LO >> 1], value);
65 break;
66 case DS_REG_TM1CNT_HI:
67 value &= 0x00C7;
68 DSTimerWriteTMCNT_HI(&dscore->timers[1], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM1CNT_LO >> 1], value);
69 break;
70 case DS_REG_TM2CNT_HI:
71 value &= 0x00C7;
72 DSTimerWriteTMCNT_HI(&dscore->timers[2], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM2CNT_LO >> 1], value);
73 break;
74 case DS_REG_TM3CNT_HI:
75 value &= 0x00C7;
76 DSTimerWriteTMCNT_HI(&dscore->timers[3], &dscore->timing, dscore->cpu, &dscore->memory.io[DS_REG_TM3CNT_LO >> 1], value);
77 break;
78
79 case DS_REG_IPCSYNC:
80 value &= 0x6F00;
81 value |= dscore->memory.io[address >> 1] & 0x000F;
82 DSIPCWriteSYNC(dscore->ipc->cpu, dscore->ipc->memory.io, value);
83 break;
84 case DS_REG_IPCFIFOCNT:
85 value = DSIPCWriteFIFOCNT(dscore, value);
86 break;
87 case DS_REG_IME:
88 DSWriteIME(dscore->cpu, dscore->memory.io, value);
89 break;
90 case DS_REG_IF_LO:
91 case DS_REG_IF_HI:
92 value = dscore->memory.io[address >> 1] & ~value;
93 break;
94 default:
95 return 0;
96 }
97 return value | 0x10000;
98}
99
100static void DSIOUpdateTimer(struct DSCommon* dscore, uint32_t address) {
101 switch (address) {
102 case DS_REG_TM0CNT_LO:
103 GBATimerUpdateRegisterInternal(&dscore->timers[0], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
104 break;
105 case DS_REG_TM1CNT_LO:
106 GBATimerUpdateRegisterInternal(&dscore->timers[1], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
107 break;
108 case DS_REG_TM2CNT_LO:
109 GBATimerUpdateRegisterInternal(&dscore->timers[2], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
110 break;
111 case DS_REG_TM3CNT_LO:
112 GBATimerUpdateRegisterInternal(&dscore->timers[3], &dscore->timing, dscore->cpu, &dscore->memory.io[address >> 1], 0);
113 break;
114 }
115}
116
117void DS7IOInit(struct DS* ds) {
118 memset(ds->memory.io7, 0, sizeof(ds->memory.io7));
119}
120
121void DS7IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
122 switch (address) {
123 default:
124 {
125 uint32_t v2 = DSIOWrite(&ds->ds7, address, value);
126 if (v2 & 0x10000) {
127 value = v2;
128 break;
129 } else if (v2 & 0x20000) {
130 return;
131 }
132 }
133 mLOG(DS_IO, STUB, "Stub DS7 I/O register write: %06X:%04X", address, value);
134 if (address >= DS7_REG_MAX) {
135 mLOG(DS_IO, GAME_ERROR, "Write to unused DS7 I/O register: %06X:%04X", address, value);
136 return;
137 }
138 break;
139 }
140 ds->memory.io7[address >> 1] = value;
141}
142
143void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
144 if (address == DS7_REG_HALTCNT) {
145 _DSHaltCNT(&ds->ds7, value);
146 return;
147 }
148 if (address < DS7_REG_MAX) {
149 uint16_t value16 = value << (8 * (address & 1));
150 value16 |= (ds->ds7.memory.io[(address & 0xFFF) >> 1]) & ~(0xFF << (8 * (address & 1)));
151 DS7IOWrite(ds, address & 0xFFFFFFFE, value16);
152 } else {
153 mLOG(DS, STUB, "Writing to unknown DS7 register: %08X:%02X", address, value);
154 }
155}
156
157void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
158 switch (address) {
159 case DS_REG_DMA0SAD_LO:
160 value = DSDMAWriteSAD(&ds->ds7, 0, value);
161 break;
162 case DS_REG_DMA1SAD_LO:
163 value = DSDMAWriteSAD(&ds->ds7, 1, value);
164 break;
165 case DS_REG_DMA2SAD_LO:
166 value = DSDMAWriteSAD(&ds->ds7, 2, value);
167 break;
168 case DS_REG_DMA3SAD_LO:
169 value = DSDMAWriteSAD(&ds->ds7, 3, value);
170 break;
171
172 case DS_REG_DMA0DAD_LO:
173 value = DSDMAWriteDAD(&ds->ds7, 0, value);
174 break;
175 case DS_REG_DMA1DAD_LO:
176 value = DSDMAWriteDAD(&ds->ds7, 1, value);
177 break;
178 case DS_REG_DMA2DAD_LO:
179 value = DSDMAWriteDAD(&ds->ds7, 2, value);
180 break;
181 case DS_REG_DMA3DAD_LO:
182 value = DSDMAWriteDAD(&ds->ds7, 3, value);
183 break;
184
185 case DS_REG_DMA0CNT_LO:
186 DS7DMAWriteCNT(&ds->ds7, 0, value);
187 break;
188 case DS_REG_DMA1CNT_LO:
189 DS7DMAWriteCNT(&ds->ds7, 1, value);
190 break;
191 case DS_REG_DMA2CNT_LO:
192 DS7DMAWriteCNT(&ds->ds7, 2, value);
193 break;
194 case DS_REG_DMA3CNT_LO:
195 DS7DMAWriteCNT(&ds->ds7, 3, value);
196 break;
197
198 case DS_REG_IPCFIFOSEND_LO:
199 DSIPCWriteFIFO(&ds->ds7, value);
200 break;
201 case DS_REG_IE_LO:
202 DSWriteIE(ds->ds7.cpu, ds->ds7.memory.io, value);
203 break;
204 default:
205 DS7IOWrite(ds, address, value & 0xFFFF);
206 DS7IOWrite(ds, address | 2, value >> 16);
207 return;
208 }
209 ds->ds7.memory.io[address >> 1] = value;
210 ds->ds7.memory.io[(address >> 1) + 1] = value >> 16;
211}
212
213uint16_t DS7IORead(struct DS* ds, uint32_t address) {
214 switch (address) {
215 case DS_REG_TM0CNT_LO:
216 case DS_REG_TM1CNT_LO:
217 case DS_REG_TM2CNT_LO:
218 case DS_REG_TM3CNT_LO:
219 DSIOUpdateTimer(&ds->ds7, address);
220 break;
221 case DS_REG_DMA0FILL_LO:
222 case DS_REG_DMA0FILL_HI:
223 case DS_REG_DMA1FILL_LO:
224 case DS_REG_DMA1FILL_HI:
225 case DS_REG_DMA2FILL_LO:
226 case DS_REG_DMA2FILL_HI:
227 case DS_REG_DMA3FILL_LO:
228 case DS_REG_DMA3FILL_HI:
229 case DS_REG_TM0CNT_HI:
230 case DS_REG_TM1CNT_HI:
231 case DS_REG_TM2CNT_HI:
232 case DS_REG_TM3CNT_HI:
233 case DS_REG_IPCSYNC:
234 case DS_REG_IPCFIFOCNT:
235 case DS_REG_IME:
236 case DS_REG_IE_LO:
237 case DS_REG_IE_HI:
238 case DS_REG_IF_LO:
239 case DS_REG_IF_HI:
240 // Handled transparently by the registers
241 break;
242 default:
243 mLOG(DS_IO, STUB, "Stub DS7 I/O register read: %06X", address);
244 }
245 if (address < DS7_REG_MAX) {
246 return ds->memory.io7[address >> 1];
247 }
248 return 0;
249}
250
251uint32_t DS7IORead32(struct DS* ds, uint32_t address) {
252 switch (address) {
253 case DS_REG_IPCFIFORECV_LO:
254 return DSIPCReadFIFO(&ds->ds7);
255 default:
256 return DS7IORead(ds, address & 0x00FFFFFC) | (DS7IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
257 }
258}
259
260void DS9IOInit(struct DS* ds) {
261 memset(ds->memory.io9, 0, sizeof(ds->memory.io9));
262}
263
264void DS9IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
265 switch (address) {
266 default:
267 {
268 uint32_t v2 = DSIOWrite(&ds->ds9, address, value);
269 if (v2 & 0x10000) {
270 value = v2;
271 break;
272 } else if (v2 & 0x20000) {
273 return;
274 }
275 }
276 mLOG(DS_IO, STUB, "Stub DS9 I/O register write: %06X:%04X", address, value);
277 if (address >= DS7_REG_MAX) {
278 mLOG(DS_IO, GAME_ERROR, "Write to unused DS9 I/O register: %06X:%04X", address, value);
279 return;
280 }
281 break;
282 }
283 ds->memory.io9[address >> 1] = value;
284}
285
286void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
287 if (address < DS9_REG_MAX) {
288 uint16_t value16 = value << (8 * (address & 1));
289 value16 |= (ds->memory.io9[(address & 0x1FFF) >> 1]) & ~(0xFF << (8 * (address & 1)));
290 DS9IOWrite(ds, address & 0xFFFFFFFE, value16);
291 } else {
292 mLOG(DS, STUB, "Writing to unknown DS9 register: %08X:%02X", address, value);
293 }
294}
295
296void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
297 switch (address) {
298 case DS_REG_DMA0SAD_LO:
299 value = DSDMAWriteSAD(&ds->ds9, 0, value);
300 break;
301 case DS_REG_DMA1SAD_LO:
302 value = DSDMAWriteSAD(&ds->ds9, 1, value);
303 break;
304 case DS_REG_DMA2SAD_LO:
305 value = DSDMAWriteSAD(&ds->ds9, 2, value);
306 break;
307 case DS_REG_DMA3SAD_LO:
308 value = DSDMAWriteSAD(&ds->ds9, 3, value);
309 break;
310
311 case DS_REG_DMA0DAD_LO:
312 value = DSDMAWriteDAD(&ds->ds9, 0, value);
313 break;
314 case DS_REG_DMA1DAD_LO:
315 value = DSDMAWriteDAD(&ds->ds9, 1, value);
316 break;
317 case DS_REG_DMA2DAD_LO:
318 value = DSDMAWriteDAD(&ds->ds9, 2, value);
319 break;
320 case DS_REG_DMA3DAD_LO:
321 value = DSDMAWriteDAD(&ds->ds9, 3, value);
322 break;
323
324 case DS_REG_DMA0CNT_LO:
325 DS9DMAWriteCNT(&ds->ds9, 0, value);
326 break;
327 case DS_REG_DMA1CNT_LO:
328 DS9DMAWriteCNT(&ds->ds9, 1, value);
329 break;
330 case DS_REG_DMA2CNT_LO:
331 DS9DMAWriteCNT(&ds->ds9, 2, value);
332 break;
333 case DS_REG_DMA3CNT_LO:
334 DS9DMAWriteCNT(&ds->ds9, 3, value);
335 break;
336
337 case DS_REG_IPCFIFOSEND_LO:
338 DSIPCWriteFIFO(&ds->ds9, value);
339 break;
340 case DS_REG_IE_LO:
341 DSWriteIE(ds->ds9.cpu, ds->ds9.memory.io, value);
342 break;
343 default:
344 DS9IOWrite(ds, address, value & 0xFFFF);
345 DS9IOWrite(ds, address | 2, value >> 16);
346 return;
347 }
348 ds->ds9.memory.io[address >> 1] = value;
349 ds->ds9.memory.io[(address >> 1) + 1] = value >> 16;
350}
351
352uint16_t DS9IORead(struct DS* ds, uint32_t address) {
353 switch (address) {
354 case DS_REG_TM0CNT_LO:
355 case DS_REG_TM1CNT_LO:
356 case DS_REG_TM2CNT_LO:
357 case DS_REG_TM3CNT_LO:
358 DSIOUpdateTimer(&ds->ds9, address);
359 break;
360 case DS_REG_DMA0FILL_LO:
361 case DS_REG_DMA0FILL_HI:
362 case DS_REG_DMA1FILL_LO:
363 case DS_REG_DMA1FILL_HI:
364 case DS_REG_DMA2FILL_LO:
365 case DS_REG_DMA2FILL_HI:
366 case DS_REG_DMA3FILL_LO:
367 case DS_REG_DMA3FILL_HI:
368 case DS_REG_TM0CNT_HI:
369 case DS_REG_TM1CNT_HI:
370 case DS_REG_TM2CNT_HI:
371 case DS_REG_TM3CNT_HI:
372 case DS_REG_IPCSYNC:
373 case DS_REG_IPCFIFOCNT:
374 case DS_REG_IME:
375 case DS_REG_IE_LO:
376 case DS_REG_IE_HI:
377 case DS_REG_IF_LO:
378 case DS_REG_IF_HI:
379 // Handled transparently by the registers
380 break;
381 default:
382 mLOG(DS_IO, STUB, "Stub DS9 I/O register read: %06X", address);
383 }
384 if (address < DS9_REG_MAX) {
385 return ds->ds9.memory.io[address >> 1];
386 }
387 return 0;
388}
389
390uint32_t DS9IORead32(struct DS* ds, uint32_t address) {
391 switch (address) {
392 case DS_REG_IPCFIFORECV_LO:
393 return DSIPCReadFIFO(&ds->ds9);
394 default:
395 return DS9IORead(ds, address & 0x00FFFFFC) | (DS9IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
396 }
397}