src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/io.h>
7
8#include <mgba/internal/gb/gb.h>
9#include <mgba/internal/gb/sio.h>
10#include <mgba/internal/gb/serialize.h>
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
13
14MGBA_EXPORT const char* const GBIORegisterNames[] = {
15 [GB_REG_JOYP] = "JOYP",
16 [GB_REG_SB] = "SB",
17 [GB_REG_SC] = "SC",
18 [GB_REG_DIV] = "DIV",
19 [GB_REG_TIMA] = "TIMA",
20 [GB_REG_TMA] = "TMA",
21 [GB_REG_TAC] = "TAC",
22 [GB_REG_IF] = "IF",
23 [GB_REG_NR10] = "NR10",
24 [GB_REG_NR11] = "NR11",
25 [GB_REG_NR12] = "NR12",
26 [GB_REG_NR13] = "NR13",
27 [GB_REG_NR14] = "NR14",
28 [GB_REG_NR21] = "NR21",
29 [GB_REG_NR22] = "NR22",
30 [GB_REG_NR23] = "NR23",
31 [GB_REG_NR24] = "NR24",
32 [GB_REG_NR30] = "NR30",
33 [GB_REG_NR31] = "NR31",
34 [GB_REG_NR32] = "NR32",
35 [GB_REG_NR33] = "NR33",
36 [GB_REG_NR34] = "NR34",
37 [GB_REG_NR41] = "NR41",
38 [GB_REG_NR42] = "NR42",
39 [GB_REG_NR43] = "NR43",
40 [GB_REG_NR44] = "NR44",
41 [GB_REG_NR50] = "NR50",
42 [GB_REG_NR51] = "NR51",
43 [GB_REG_NR52] = "NR52",
44 [GB_REG_LCDC] = "LCDC",
45 [GB_REG_STAT] = "STAT",
46 [GB_REG_SCY] = "SCY",
47 [GB_REG_SCX] = "SCX",
48 [GB_REG_LY] = "LY",
49 [GB_REG_LYC] = "LYC",
50 [GB_REG_DMA] = "DMA",
51 [GB_REG_BGP] = "BGP",
52 [GB_REG_OBP0] = "OBP0",
53 [GB_REG_OBP1] = "OBP1",
54 [GB_REG_WY] = "WY",
55 [GB_REG_WX] = "WX",
56 [GB_REG_KEY0] = "KEY0",
57 [GB_REG_KEY1] = "KEY1",
58 [GB_REG_VBK] = "VBK",
59 [GB_REG_BANK] = "BANK",
60 [GB_REG_HDMA1] = "HDMA1",
61 [GB_REG_HDMA2] = "HDMA2",
62 [GB_REG_HDMA3] = "HDMA3",
63 [GB_REG_HDMA4] = "HDMA4",
64 [GB_REG_HDMA5] = "HDMA5",
65 [GB_REG_RP] = "RP",
66 [GB_REG_BCPS] = "BCPS",
67 [GB_REG_BCPD] = "BCPD",
68 [GB_REG_OCPS] = "OCPS",
69 [GB_REG_OCPD] = "OCPD",
70 [GB_REG_OPRI] = "OPRI",
71 [GB_REG_SVBK] = "SVBK",
72 [GB_REG_IE] = "IE",
73};
74
75static const uint8_t _registerMask[] = {
76 [GB_REG_SC] = 0x7E, // TODO: GBC differences
77 [GB_REG_IF] = 0xE0,
78 [GB_REG_TAC] = 0xF8,
79 [GB_REG_NR10] = 0x80,
80 [GB_REG_NR11] = 0x3F,
81 [GB_REG_NR12] = 0x00,
82 [GB_REG_NR13] = 0xFF,
83 [GB_REG_NR14] = 0xBF,
84 [GB_REG_NR21] = 0x3F,
85 [GB_REG_NR22] = 0x00,
86 [GB_REG_NR23] = 0xFF,
87 [GB_REG_NR24] = 0xBF,
88 [GB_REG_NR30] = 0x7F,
89 [GB_REG_NR31] = 0xFF,
90 [GB_REG_NR32] = 0x9F,
91 [GB_REG_NR33] = 0xFF,
92 [GB_REG_NR34] = 0xBF,
93 [GB_REG_NR41] = 0xFF,
94 [GB_REG_NR42] = 0x00,
95 [GB_REG_NR43] = 0x00,
96 [GB_REG_NR44] = 0xBF,
97 [GB_REG_NR50] = 0x00,
98 [GB_REG_NR51] = 0x00,
99 [GB_REG_NR52] = 0x70,
100 [GB_REG_STAT] = 0x80,
101 [GB_REG_KEY1] = 0x7E,
102 [GB_REG_VBK] = 0xFE,
103 [GB_REG_OCPS] = 0x40,
104 [GB_REG_BCPS] = 0x40,
105 [GB_REG_OPRI] = 0xFE,
106 [GB_REG_SVBK] = 0xF8,
107 [GB_REG_UNK75] = 0x8F,
108 [GB_REG_IE] = 0xE0,
109};
110
111static uint8_t _readKeys(struct GB* gb);
112static uint8_t _readKeysFiltered(struct GB* gb);
113
114static void _writeSGBBits(struct GB* gb, int bits) {
115 if (!bits) {
116 gb->sgbBit = -1;
117 memset(gb->sgbPacket, 0, sizeof(gb->sgbPacket));
118 }
119 if (bits == gb->currentSgbBits) {
120 return;
121 }
122 switch (bits) {
123 case 0:
124 case 1:
125 if (gb->currentSgbBits & 2) {
126 gb->sgbIncrement = !gb->sgbIncrement;
127 }
128 break;
129 case 3:
130 if (gb->sgbIncrement) {
131 gb->sgbIncrement = false;
132 gb->sgbCurrentController = (gb->sgbCurrentController + 1) & gb->sgbControllers;
133 }
134 break;
135 }
136 gb->currentSgbBits = bits;
137 if (gb->sgbBit == 128 && bits == 2) {
138 GBVideoWriteSGBPacket(&gb->video, gb->sgbPacket);
139 ++gb->sgbBit;
140 }
141 if (gb->sgbBit >= 128) {
142 return;
143 }
144 switch (bits) {
145 case 1:
146 if (gb->sgbBit < 0) {
147 return;
148 }
149 gb->sgbPacket[gb->sgbBit >> 3] |= 1 << (gb->sgbBit & 7);
150 break;
151 case 3:
152 ++gb->sgbBit;
153 default:
154 break;
155 }
156}
157
158void GBIOInit(struct GB* gb) {
159 memset(gb->memory.io, 0, sizeof(gb->memory.io));
160}
161
162void GBIOReset(struct GB* gb) {
163 memset(gb->memory.io, 0, sizeof(gb->memory.io));
164
165 GBIOWrite(gb, GB_REG_TIMA, 0);
166 GBIOWrite(gb, GB_REG_TMA, 0);
167 GBIOWrite(gb, GB_REG_TAC, 0);
168 GBIOWrite(gb, GB_REG_IF, 1);
169 GBIOWrite(gb, GB_REG_NR52, 0xF1);
170 GBIOWrite(gb, GB_REG_NR14, 0x3F);
171 GBIOWrite(gb, GB_REG_NR10, 0x80);
172 GBIOWrite(gb, GB_REG_NR11, 0xBF);
173 GBIOWrite(gb, GB_REG_NR12, 0xF3);
174 GBIOWrite(gb, GB_REG_NR13, 0xF3);
175 GBIOWrite(gb, GB_REG_NR24, 0x3F);
176 GBIOWrite(gb, GB_REG_NR21, 0x3F);
177 GBIOWrite(gb, GB_REG_NR22, 0x00);
178 GBIOWrite(gb, GB_REG_NR34, 0x3F);
179 GBIOWrite(gb, GB_REG_NR30, 0x7F);
180 GBIOWrite(gb, GB_REG_NR31, 0xFF);
181 GBIOWrite(gb, GB_REG_NR32, 0x9F);
182 GBIOWrite(gb, GB_REG_NR44, 0x3F);
183 GBIOWrite(gb, GB_REG_NR41, 0xFF);
184 GBIOWrite(gb, GB_REG_NR42, 0x00);
185 GBIOWrite(gb, GB_REG_NR43, 0x00);
186 GBIOWrite(gb, GB_REG_NR50, 0x77);
187 GBIOWrite(gb, GB_REG_NR51, 0xF3);
188 if (!gb->biosVf) {
189 GBIOWrite(gb, GB_REG_LCDC, 0x91);
190 gb->memory.io[GB_REG_BANK] = 1;
191 } else {
192 GBIOWrite(gb, GB_REG_LCDC, 0x00);
193 gb->memory.io[GB_REG_BANK] = 0xFF;
194 }
195 GBIOWrite(gb, GB_REG_SCY, 0x00);
196 GBIOWrite(gb, GB_REG_SCX, 0x00);
197 GBIOWrite(gb, GB_REG_LYC, 0x00);
198 gb->memory.io[GB_REG_DMA] = 0xFF;
199 GBIOWrite(gb, GB_REG_BGP, 0xFC);
200 if (gb->model < GB_MODEL_CGB) {
201 GBIOWrite(gb, GB_REG_OBP0, 0xFF);
202 GBIOWrite(gb, GB_REG_OBP1, 0xFF);
203 }
204 GBIOWrite(gb, GB_REG_WY, 0x00);
205 GBIOWrite(gb, GB_REG_WX, 0x00);
206 if (gb->model & GB_MODEL_CGB) {
207 GBIOWrite(gb, GB_REG_KEY0, 0);
208 GBIOWrite(gb, GB_REG_JOYP, 0xFF);
209 GBIOWrite(gb, GB_REG_VBK, 0);
210 GBIOWrite(gb, GB_REG_BCPS, 0x80);
211 GBIOWrite(gb, GB_REG_OCPS, 0);
212 GBIOWrite(gb, GB_REG_SVBK, 1);
213 GBIOWrite(gb, GB_REG_HDMA1, 0xFF);
214 GBIOWrite(gb, GB_REG_HDMA2, 0xFF);
215 GBIOWrite(gb, GB_REG_HDMA3, 0xFF);
216 GBIOWrite(gb, GB_REG_HDMA4, 0xFF);
217 gb->memory.io[GB_REG_HDMA5] = 0xFF;
218 } else {
219 memset(&gb->memory.io[GB_REG_KEY0], 0xFF, GB_REG_PCM34 - GB_REG_KEY0 + 1);
220 }
221
222 if (gb->model & GB_MODEL_SGB) {
223 GBIOWrite(gb, GB_REG_JOYP, 0xFF);
224 }
225 GBIOWrite(gb, GB_REG_IE, 0x00);
226}
227
228void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
229 switch (address) {
230 case GB_REG_SB:
231 GBSIOWriteSB(&gb->sio, value);
232 break;
233 case GB_REG_SC:
234 GBSIOWriteSC(&gb->sio, value);
235 break;
236 case GB_REG_DIV:
237 GBTimerDivReset(&gb->timer);
238 return;
239 case GB_REG_NR10:
240 if (gb->audio.enable) {
241 GBAudioWriteNR10(&gb->audio, value);
242 } else {
243 value = 0;
244 }
245 break;
246 case GB_REG_NR11:
247 if (gb->audio.enable) {
248 GBAudioWriteNR11(&gb->audio, value);
249 } else {
250 if (gb->audio.style == GB_AUDIO_DMG) {
251 GBAudioWriteNR11(&gb->audio, value & _registerMask[GB_REG_NR11]);
252 }
253 value = 0;
254 }
255 break;
256 case GB_REG_NR12:
257 if (gb->audio.enable) {
258 GBAudioWriteNR12(&gb->audio, value);
259 } else {
260 value = 0;
261 }
262 break;
263 case GB_REG_NR13:
264 if (gb->audio.enable) {
265 GBAudioWriteNR13(&gb->audio, value);
266 } else {
267 value = 0;
268 }
269 break;
270 case GB_REG_NR14:
271 if (gb->audio.enable) {
272 GBAudioWriteNR14(&gb->audio, value);
273 } else {
274 value = 0;
275 }
276 break;
277 case GB_REG_NR21:
278 if (gb->audio.enable) {
279 GBAudioWriteNR21(&gb->audio, value);
280 } else {
281 if (gb->audio.style == GB_AUDIO_DMG) {
282 GBAudioWriteNR21(&gb->audio, value & _registerMask[GB_REG_NR21]);
283 }
284 value = 0;
285 }
286 break;
287 case GB_REG_NR22:
288 if (gb->audio.enable) {
289 GBAudioWriteNR22(&gb->audio, value);
290 } else {
291 value = 0;
292 }
293 break;
294 case GB_REG_NR23:
295 if (gb->audio.enable) {
296 GBAudioWriteNR23(&gb->audio, value);
297 } else {
298 value = 0;
299 }
300 break;
301 case GB_REG_NR24:
302 if (gb->audio.enable) {
303 GBAudioWriteNR24(&gb->audio, value);
304 } else {
305 value = 0;
306 }
307 break;
308 case GB_REG_NR30:
309 if (gb->audio.enable) {
310 GBAudioWriteNR30(&gb->audio, value);
311 } else {
312 value = 0;
313 }
314 break;
315 case GB_REG_NR31:
316 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
317 GBAudioWriteNR31(&gb->audio, value);
318 } else {
319 value = 0;
320 }
321 break;
322 case GB_REG_NR32:
323 if (gb->audio.enable) {
324 GBAudioWriteNR32(&gb->audio, value);
325 } else {
326 value = 0;
327 }
328 break;
329 case GB_REG_NR33:
330 if (gb->audio.enable) {
331 GBAudioWriteNR33(&gb->audio, value);
332 } else {
333 value = 0;
334 }
335 break;
336 case GB_REG_NR34:
337 if (gb->audio.enable) {
338 GBAudioWriteNR34(&gb->audio, value);
339 } else {
340 value = 0;
341 }
342 break;
343 case GB_REG_NR41:
344 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
345 GBAudioWriteNR41(&gb->audio, value);
346 } else {
347 value = 0;
348 }
349 break;
350 case GB_REG_NR42:
351 if (gb->audio.enable) {
352 GBAudioWriteNR42(&gb->audio, value);
353 } else {
354 value = 0;
355 }
356 break;
357 case GB_REG_NR43:
358 if (gb->audio.enable) {
359 GBAudioWriteNR43(&gb->audio, value);
360 } else {
361 value = 0;
362 }
363 break;
364 case GB_REG_NR44:
365 if (gb->audio.enable) {
366 GBAudioWriteNR44(&gb->audio, value);
367 } else {
368 value = 0;
369 }
370 break;
371 case GB_REG_NR50:
372 if (gb->audio.enable) {
373 GBAudioWriteNR50(&gb->audio, value);
374 } else {
375 value = 0;
376 }
377 break;
378 case GB_REG_NR51:
379 if (gb->audio.enable) {
380 GBAudioWriteNR51(&gb->audio, value);
381 } else {
382 value = 0;
383 }
384 break;
385 case GB_REG_NR52:
386 GBAudioWriteNR52(&gb->audio, value);
387 value &= 0x80;
388 value |= gb->memory.io[GB_REG_NR52] & 0x0F;
389 break;
390 case GB_REG_WAVE_0:
391 case GB_REG_WAVE_1:
392 case GB_REG_WAVE_2:
393 case GB_REG_WAVE_3:
394 case GB_REG_WAVE_4:
395 case GB_REG_WAVE_5:
396 case GB_REG_WAVE_6:
397 case GB_REG_WAVE_7:
398 case GB_REG_WAVE_8:
399 case GB_REG_WAVE_9:
400 case GB_REG_WAVE_A:
401 case GB_REG_WAVE_B:
402 case GB_REG_WAVE_C:
403 case GB_REG_WAVE_D:
404 case GB_REG_WAVE_E:
405 case GB_REG_WAVE_F:
406 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
407 gb->audio.ch3.wavedata8[address - GB_REG_WAVE_0] = value;
408 } else if(gb->audio.ch3.readable) {
409 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
410 }
411 break;
412 case GB_REG_JOYP:
413 gb->memory.io[GB_REG_JOYP] = value | 0x0F;
414 _readKeys(gb);
415 if (gb->model & GB_MODEL_SGB) {
416 _writeSGBBits(gb, (value >> 4) & 3);
417 }
418 return;
419 case GB_REG_TIMA:
420 if (value && mTimingUntil(&gb->timing, &gb->timer.irq) > 2 - (int) gb->doubleSpeed) {
421 mTimingDeschedule(&gb->timing, &gb->timer.irq);
422 }
423 if (mTimingUntil(&gb->timing, &gb->timer.irq) == (int) gb->doubleSpeed - 2) {
424 return;
425 }
426 break;
427 case GB_REG_TMA:
428 if (mTimingUntil(&gb->timing, &gb->timer.irq) == (int) gb->doubleSpeed - 2) {
429 gb->memory.io[GB_REG_TIMA] = value;
430 }
431 break;
432 case GB_REG_TAC:
433 value = GBTimerUpdateTAC(&gb->timer, value);
434 break;
435 case GB_REG_IF:
436 gb->memory.io[GB_REG_IF] = value | 0xE0;
437 GBUpdateIRQs(gb);
438 return;
439 case GB_REG_LCDC:
440 // TODO: handle GBC differences
441 GBVideoProcessDots(&gb->video, 0);
442 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
443 GBVideoWriteLCDC(&gb->video, value);
444 break;
445 case GB_REG_LYC:
446 GBVideoWriteLYC(&gb->video, value);
447 break;
448 case GB_REG_DMA:
449 GBMemoryDMA(gb, value << 8);
450 break;
451 case GB_REG_SCY:
452 case GB_REG_SCX:
453 case GB_REG_WY:
454 case GB_REG_WX:
455 GBVideoProcessDots(&gb->video, 0);
456 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
457 break;
458 case GB_REG_BGP:
459 case GB_REG_OBP0:
460 case GB_REG_OBP1:
461 GBVideoProcessDots(&gb->video, 0);
462 GBVideoWritePalette(&gb->video, address, value);
463 break;
464 case GB_REG_STAT:
465 GBVideoWriteSTAT(&gb->video, value);
466 value = gb->video.stat;
467 break;
468 case GB_REG_BANK:
469 if (gb->memory.io[GB_REG_BANK] != 0xFF) {
470 break;
471 }
472 GBUnmapBIOS(gb);
473 if (gb->model >= GB_MODEL_CGB && gb->memory.io[GB_REG_KEY0] < 0x80) {
474 gb->model = GB_MODEL_DMG;
475 GBVideoDisableCGB(&gb->video);
476 }
477 break;
478 case GB_REG_IE:
479 gb->memory.ie = value;
480 GBUpdateIRQs(gb);
481 return;
482 default:
483 if (gb->model >= GB_MODEL_CGB) {
484 switch (address) {
485 case GB_REG_KEY0:
486 break;
487 case GB_REG_KEY1:
488 value &= 0x1;
489 value |= gb->memory.io[address] & 0x80;
490 break;
491 case GB_REG_VBK:
492 GBVideoSwitchBank(&gb->video, value);
493 break;
494 case GB_REG_HDMA1:
495 case GB_REG_HDMA2:
496 case GB_REG_HDMA3:
497 case GB_REG_HDMA4:
498 // Handled transparently by the registers
499 break;
500 case GB_REG_HDMA5:
501 value = GBMemoryWriteHDMA5(gb, value);
502 break;
503 case GB_REG_BCPS:
504 gb->video.bcpIndex = value & 0x3F;
505 gb->video.bcpIncrement = value & 0x80;
506 gb->memory.io[GB_REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
507 break;
508 case GB_REG_BCPD:
509 if (gb->video.mode != 3) {
510 GBVideoProcessDots(&gb->video, 0);
511 }
512 GBVideoWritePalette(&gb->video, address, value);
513 return;
514 case GB_REG_OCPS:
515 gb->video.ocpIndex = value & 0x3F;
516 gb->video.ocpIncrement = value & 0x80;
517 gb->memory.io[GB_REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
518 break;
519 case GB_REG_OCPD:
520 if (gb->video.mode != 3) {
521 GBVideoProcessDots(&gb->video, 0);
522 }
523 GBVideoWritePalette(&gb->video, address, value);
524 return;
525 case GB_REG_SVBK:
526 GBMemorySwitchWramBank(&gb->memory, value);
527 value = gb->memory.wramCurrentBank;
528 break;
529 default:
530 goto failed;
531 }
532 goto success;
533 }
534 failed:
535 mLOG(GB_IO, GAME_ERROR, "Writing to unknown register FF%02X:%02X", address, value);
536 return;
537 }
538 success:
539 gb->memory.io[address] = value;
540}
541
542static uint8_t _readKeys(struct GB* gb) {
543 uint8_t keys = *gb->keySource;
544 if (gb->sgbCurrentController != 0) {
545 keys = 0;
546 }
547 uint8_t joyp = gb->memory.io[GB_REG_JOYP];
548 switch (joyp & 0x30) {
549 case 0x30:
550 keys = gb->sgbCurrentController;
551 break;
552 case 0x20:
553 keys >>= 4;
554 break;
555 case 0x10:
556 break;
557 case 0x00:
558 keys |= keys >> 4;
559 break;
560 }
561 gb->memory.io[GB_REG_JOYP] = (0xCF | joyp) ^ (keys & 0xF);
562 if (joyp & ~gb->memory.io[GB_REG_JOYP] & 0xF) {
563 gb->memory.io[GB_REG_IF] |= (1 << GB_IRQ_KEYPAD);
564 GBUpdateIRQs(gb);
565 }
566 return gb->memory.io[GB_REG_JOYP];
567}
568
569static uint8_t _readKeysFiltered(struct GB* gb) {
570 uint8_t keys = _readKeys(gb);
571 if (!gb->allowOpposingDirections && (keys & 0x30) == 0x20) {
572 unsigned rl = keys & 0x03;
573 unsigned ud = keys & 0x0C;
574 if (!rl) {
575 keys |= 0x03;
576 }
577 if (!ud) {
578 keys |= 0x0C;
579 }
580 }
581 return keys;
582}
583
584uint8_t GBIORead(struct GB* gb, unsigned address) {
585 switch (address) {
586 case GB_REG_JOYP:
587 {
588 size_t c;
589 for (c = 0; c < mCoreCallbacksListSize(&gb->coreCallbacks); ++c) {
590 struct mCoreCallbacks* callbacks = mCoreCallbacksListGetPointer(&gb->coreCallbacks, c);
591 if (callbacks->keysRead) {
592 callbacks->keysRead(callbacks->context);
593 }
594 }
595 }
596 return _readKeysFiltered(gb);
597 case GB_REG_IE:
598 return gb->memory.ie;
599 case GB_REG_WAVE_0:
600 case GB_REG_WAVE_1:
601 case GB_REG_WAVE_2:
602 case GB_REG_WAVE_3:
603 case GB_REG_WAVE_4:
604 case GB_REG_WAVE_5:
605 case GB_REG_WAVE_6:
606 case GB_REG_WAVE_7:
607 case GB_REG_WAVE_8:
608 case GB_REG_WAVE_9:
609 case GB_REG_WAVE_A:
610 case GB_REG_WAVE_B:
611 case GB_REG_WAVE_C:
612 case GB_REG_WAVE_D:
613 case GB_REG_WAVE_E:
614 case GB_REG_WAVE_F:
615 if (gb->audio.playingCh3) {
616 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
617 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
618 } else {
619 return 0xFF;
620 }
621 } else {
622 return gb->audio.ch3.wavedata8[address - GB_REG_WAVE_0];
623 }
624 break;
625 case GB_REG_PCM12:
626 if (gb->model < GB_MODEL_CGB) {
627 mLOG(GB_IO, GAME_ERROR, "Reading from CGB register FF%02X in DMG mode", address);
628 } else if (gb->audio.enable) {
629 return (gb->audio.ch1.sample) | (gb->audio.ch2.sample << 4);
630 }
631 break;
632 case GB_REG_PCM34:
633 if (gb->model < GB_MODEL_CGB) {
634 mLOG(GB_IO, GAME_ERROR, "Reading from CGB register FF%02X in DMG mode", address);
635 } else if (gb->audio.enable) {
636 return (gb->audio.ch3.sample) | (gb->audio.ch4.sample << 4);
637 }
638 break;
639 case GB_REG_SB:
640 case GB_REG_SC:
641 case GB_REG_IF:
642 case GB_REG_NR10:
643 case GB_REG_NR11:
644 case GB_REG_NR12:
645 case GB_REG_NR14:
646 case GB_REG_NR21:
647 case GB_REG_NR22:
648 case GB_REG_NR24:
649 case GB_REG_NR30:
650 case GB_REG_NR32:
651 case GB_REG_NR34:
652 case GB_REG_NR41:
653 case GB_REG_NR42:
654 case GB_REG_NR43:
655 case GB_REG_NR44:
656 case GB_REG_NR50:
657 case GB_REG_NR51:
658 case GB_REG_NR52:
659 case GB_REG_DIV:
660 case GB_REG_TIMA:
661 case GB_REG_TMA:
662 case GB_REG_TAC:
663 case GB_REG_STAT:
664 case GB_REG_LCDC:
665 case GB_REG_SCY:
666 case GB_REG_SCX:
667 case GB_REG_LY:
668 case GB_REG_LYC:
669 case GB_REG_DMA:
670 case GB_REG_BGP:
671 case GB_REG_OBP0:
672 case GB_REG_OBP1:
673 case GB_REG_WY:
674 case GB_REG_WX:
675 // Handled transparently by the registers
676 break;
677 case GB_REG_KEY1:
678 case GB_REG_VBK:
679 case GB_REG_HDMA1:
680 case GB_REG_HDMA2:
681 case GB_REG_HDMA3:
682 case GB_REG_HDMA4:
683 case GB_REG_HDMA5:
684 case GB_REG_BCPS:
685 case GB_REG_BCPD:
686 case GB_REG_OCPS:
687 case GB_REG_OCPD:
688 case GB_REG_SVBK:
689 case GB_REG_UNK72:
690 case GB_REG_UNK73:
691 case GB_REG_UNK75:
692 // Handled transparently by the registers
693 if (gb->model < GB_MODEL_CGB) {
694 // In DMG mode, these all get initialized to 0xFF during reset
695 // But in DMG-on-CGB mode, they get initialized by the CGB reset so they can be non-zero
696 mLOG(GB_IO, GAME_ERROR, "Reading from CGB register FF%02X in DMG mode", address);
697 }
698 break;
699 default:
700 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
701 return 0xFF;
702 }
703 return gb->memory.io[address] | _registerMask[address];
704}
705
706void GBTestKeypadIRQ(struct GB* gb) {
707 _readKeys(gb);
708}
709
710struct GBSerializedState;
711void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
712 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
713 state->ie = gb->memory.ie;
714}
715
716void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
717 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
718 gb->memory.ie = state->ie;
719
720 gb->audio.enable = GBAudioEnableGetEnable(*gb->audio.nr52);
721 if (gb->audio.enable) {
722 GBIOWrite(gb, GB_REG_NR10, gb->memory.io[GB_REG_NR10]);
723 GBIOWrite(gb, GB_REG_NR11, gb->memory.io[GB_REG_NR11]);
724 GBIOWrite(gb, GB_REG_NR12, gb->memory.io[GB_REG_NR12]);
725 GBIOWrite(gb, GB_REG_NR13, gb->memory.io[GB_REG_NR13]);
726 gb->audio.ch1.control.frequency &= 0xFF;
727 gb->audio.ch1.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[GB_REG_NR14] << 8);
728 gb->audio.ch1.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[GB_REG_NR14] << 8);
729 GBIOWrite(gb, GB_REG_NR21, gb->memory.io[GB_REG_NR21]);
730 GBIOWrite(gb, GB_REG_NR22, gb->memory.io[GB_REG_NR22]);
731 GBIOWrite(gb, GB_REG_NR23, gb->memory.io[GB_REG_NR23]);
732 gb->audio.ch2.control.frequency &= 0xFF;
733 gb->audio.ch2.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[GB_REG_NR24] << 8);
734 gb->audio.ch2.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[GB_REG_NR24] << 8);
735 GBIOWrite(gb, GB_REG_NR30, gb->memory.io[GB_REG_NR30]);
736 GBIOWrite(gb, GB_REG_NR31, gb->memory.io[GB_REG_NR31]);
737 GBIOWrite(gb, GB_REG_NR32, gb->memory.io[GB_REG_NR32]);
738 GBIOWrite(gb, GB_REG_NR33, gb->memory.io[GB_REG_NR33]);
739 gb->audio.ch3.rate &= 0xFF;
740 gb->audio.ch3.rate |= GBAudioRegisterControlGetRate(gb->memory.io[GB_REG_NR34] << 8);
741 gb->audio.ch3.stop = GBAudioRegisterControlGetStop(gb->memory.io[GB_REG_NR34] << 8);
742 GBIOWrite(gb, GB_REG_NR41, gb->memory.io[GB_REG_NR41]);
743 GBIOWrite(gb, GB_REG_NR42, gb->memory.io[GB_REG_NR42]);
744 GBIOWrite(gb, GB_REG_NR43, gb->memory.io[GB_REG_NR43]);
745 gb->audio.ch4.stop = GBAudioRegisterNoiseControlGetStop(gb->memory.io[GB_REG_NR44]);
746 GBIOWrite(gb, GB_REG_NR50, gb->memory.io[GB_REG_NR50]);
747 GBIOWrite(gb, GB_REG_NR51, gb->memory.io[GB_REG_NR51]);
748 }
749
750 gb->video.renderer->writeVideoRegister(gb->video.renderer, GB_REG_LCDC, state->io[GB_REG_LCDC]);
751 gb->video.renderer->writeVideoRegister(gb->video.renderer, GB_REG_SCY, state->io[GB_REG_SCY]);
752 gb->video.renderer->writeVideoRegister(gb->video.renderer, GB_REG_SCX, state->io[GB_REG_SCX]);
753 gb->video.renderer->writeVideoRegister(gb->video.renderer, GB_REG_WY, state->io[GB_REG_WY]);
754 gb->video.renderer->writeVideoRegister(gb->video.renderer, GB_REG_WX, state->io[GB_REG_WX]);
755 if (gb->model & GB_MODEL_SGB) {
756 gb->video.renderer->writeVideoRegister(gb->video.renderer, GB_REG_BGP, state->io[GB_REG_BGP]);
757 gb->video.renderer->writeVideoRegister(gb->video.renderer, GB_REG_OBP0, state->io[GB_REG_OBP0]);
758 gb->video.renderer->writeVideoRegister(gb->video.renderer, GB_REG_OBP1, state->io[GB_REG_OBP1]);
759 }
760 gb->video.stat = state->io[GB_REG_STAT];
761}