src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26const uint8_t DS_CHIP_ID[4] = { 0xC2, 0x0F, 0x00, 0x00 };
27
28static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
29static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
30static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
31
32enum {
33 DS7_SP_BASE = 0x380FD80,
34 DS7_SP_BASE_IRQ = 0x380FF80,
35 DS7_SP_BASE_SVC = 0x380FFC0,
36
37 DS9_SP_BASE = 0x3002F7C,
38 DS9_SP_BASE_IRQ = 0x3003F80,
39 DS9_SP_BASE_SVC = 0x3003FC0,
40};
41
42static void DSInit(void* cpu, struct mCPUComponent* component);
43
44static void DS7Reset(struct ARMCore* cpu);
45static void DS7TestIRQ(struct ARMCore* cpu);
46static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
47static void DS7ProcessEvents(struct ARMCore* cpu);
48
49static void DS9Reset(struct ARMCore* cpu);
50static void DS9TestIRQ(struct ARMCore* cpu);
51static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
52static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
53static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
54static void DS9ProcessEvents(struct ARMCore* cpu);
55
56static void DSProcessEvents(struct DSCommon* dscore);
57static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
58static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
59static void DSBreakpoint(struct ARMCore* cpu, int immediate);
60
61static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
62 UNUSED(cyclesLate);
63 struct DS* ds = context;
64 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
65 if (ds->activeCpu == ds->ds9.cpu) {
66 ds->activeCpu = ds->ds7.cpu;
67 ds->cycleDrift += cycles;
68 cycles = ds->cycleDrift >> 1;
69 timing = &ds->ds7.timing;
70 } else {
71 ds->activeCpu = ds->ds9.cpu;
72 ds->cycleDrift -= cycles << 1;
73 cycles = ds->cycleDrift + SLICE_CYCLES;
74 timing = &ds->ds9.timing;
75 }
76 mTimingSchedule(timing, &ds->slice, cycles);
77 ds->sliceStart = mTimingCurrentTime(timing);
78 ds->earlyExit = true;
79}
80
81static void _divide(struct mTiming* timing, void* context, uint32_t cyclesLate) {
82 UNUSED(timing);
83 UNUSED(cyclesLate);
84 struct DS* ds = context;
85 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x8000;
86 int64_t numerator;
87 int64_t denominator;
88 LOAD_64LE(numerator, DS9_REG_DIV_NUMER_0, ds->memory.io9);
89 LOAD_64LE(denominator, DS9_REG_DIV_DENOM_0, ds->memory.io9);
90 bool max = false;
91 switch (ds->memory.io9[DS9_REG_DIVCNT >> 1] & 0x3) {
92 case 0:
93 numerator = (int64_t)(int32_t) numerator;
94 case 1:
95 case 3:
96 denominator = (int64_t)(int32_t) denominator;
97 break;
98 }
99 if (numerator == INT64_MIN) {
100 max = true;
101 }
102 if (!denominator) {
103 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
104 STORE_64LE(numerator, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
105 numerator >>= 63LL;
106 numerator = -numerator;
107 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
108 return;
109 }
110 if (denominator == -1LL && max) {
111 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
112 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
113 return;
114 }
115 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x4000;
116 int64_t result = numerator / denominator;
117 int64_t remainder = numerator % denominator; // TODO: defined behavior for negative denominator?
118 STORE_64LE(result, DS9_REG_DIV_RESULT_0, ds->memory.io9);
119 STORE_64LE(remainder, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
120}
121
122 static void _sqrt(struct mTiming* timing, void* context, uint32_t cyclesLate) {
123 UNUSED(timing);
124 UNUSED(cyclesLate);
125 struct DS* ds = context;
126 ds->memory.io9[DS9_REG_SQRTCNT >> 1] &= ~0x8000;
127 uint64_t param;
128 LOAD_64LE(param, DS9_REG_SQRT_PARAM_0, ds->memory.io9);
129 if (!(ds->memory.io9[DS9_REG_SQRTCNT >> 1] & 1)) {
130 param &= 0xFFFFFFFFULL;
131 }
132
133 uint64_t result = 0;
134 uint64_t bit = 0x4000000000000000ULL; // The second-to-top bit is set: 1 << 30 for 32 bits
135
136 // "bit" starts at the highest power of four <= the argument.
137 while (bit > param) {
138 bit >>= 2;
139 }
140
141 while (bit != 0) {
142 if (param >= param + bit) {
143 param -= param + bit;
144 param = (result >> 1) + bit;
145 } else {
146 param >>= 1;
147 }
148 bit >>= 2;
149 }
150 STORE_32LE(result, DS9_REG_SQRT_RESULT_LO, ds->memory.io9);
151}
152
153void DSCreate(struct DS* ds) {
154 ds->d.id = DS_COMPONENT_MAGIC;
155 ds->d.init = DSInit;
156 ds->d.deinit = NULL;
157 ds->ds7.p = ds;
158 ds->ds9.p = ds;
159 ds->ds7.cpu = NULL;
160 ds->ds9.cpu = NULL;
161 ds->ds7.ipc = &ds->ds9;
162 ds->ds9.ipc = &ds->ds7;
163}
164
165static void DSInit(void* cpu, struct mCPUComponent* component) {
166 struct DS* ds = (struct DS*) component;
167 struct ARMCore* core = cpu;
168 if (!ds->ds7.cpu) {
169 // The ARM7 must get initialized first
170 ds->ds7.cpu = core;
171 ds->debugger = 0;
172 ds->sync = 0;
173 return;
174 }
175 ds->ds9.cpu = cpu;
176 ds->activeCpu = NULL;
177
178 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
179
180 ds->slice.name = "DS CPU Time Slicing";
181 ds->slice.callback = _slice;
182 ds->slice.context = ds;
183 ds->slice.priority = UINT_MAX;
184
185 CircleBufferInit(&ds->ds7.fifo, 64);
186 CircleBufferInit(&ds->ds9.fifo, 64);
187
188 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
189 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
190 DSMemoryInit(ds);
191 DSDMAInit(ds);
192
193 DSVideoInit(&ds->video);
194 ds->video.p = ds;
195
196 ds->ds7.springIRQ = 0;
197 ds->ds9.springIRQ = 0;
198 DSTimerInit(ds);
199 ds->keySource = NULL;
200 ds->rtcSource = NULL;
201 ds->rumble = NULL;
202
203 ds->romVf = NULL;
204
205 ds->keyCallback = NULL;
206
207 ds->divEvent.name = "DS Hardware Divide";
208 ds->divEvent.callback = _divide;
209 ds->divEvent.context = ds;
210 ds->divEvent.priority = 0x50;
211
212 ds->sqrtEvent.name = "DS Hardware Sqrt";
213 ds->sqrtEvent.callback = _sqrt;
214 ds->sqrtEvent.context = ds;
215 ds->sqrtEvent.priority = 0x51;
216
217 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
218 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
219}
220
221void DSUnloadROM(struct DS* ds) {
222 if (ds->romVf) {
223 ds->romVf->close(ds->romVf);
224 ds->romVf = NULL;
225 }
226}
227
228void DSDestroy(struct DS* ds) {
229 CircleBufferDeinit(&ds->ds7.fifo);
230 CircleBufferDeinit(&ds->ds9.fifo);
231 DSUnloadROM(ds);
232 DSMemoryDeinit(ds);
233 mTimingDeinit(&ds->ds7.timing);
234 mTimingDeinit(&ds->ds9.timing);
235}
236
237void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
238 irqh->reset = DS7Reset;
239 irqh->processEvents = DS7ProcessEvents;
240 irqh->swi16 = DS7Swi16;
241 irqh->swi32 = DS7Swi32;
242 irqh->hitIllegal = DSIllegal;
243 irqh->readCPSR = DS7TestIRQ;
244 irqh->writeCP15 = NULL;
245 irqh->readCP15 = NULL;
246 irqh->hitStub = DSHitStub;
247 irqh->bkpt16 = DSBreakpoint;
248 irqh->bkpt32 = DSBreakpoint;
249}
250
251void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
252 irqh->reset = DS9Reset;
253 irqh->processEvents = DS9ProcessEvents;
254 irqh->swi16 = DS9Swi16;
255 irqh->swi32 = DS9Swi32;
256 irqh->hitIllegal = DSIllegal;
257 irqh->readCPSR = DS9TestIRQ;
258 irqh->writeCP15 = DS9WriteCP15;
259 irqh->readCP15 = DS9ReadCP15;
260 irqh->hitStub = DSHitStub;
261 irqh->bkpt16 = DSBreakpoint;
262 irqh->bkpt32 = DSBreakpoint;
263}
264
265void DS7Reset(struct ARMCore* cpu) {
266 ARMSetPrivilegeMode(cpu, MODE_IRQ);
267 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
268 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
269 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
270 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
271 cpu->gprs[ARM_SP] = DS7_SP_BASE;
272
273 struct DS* ds = (struct DS*) cpu->master;
274 mTimingClear(&ds->ds7.timing);
275 CircleBufferInit(&ds->ds7.fifo, 64);
276 DSMemoryReset(ds);
277 DSDMAReset(&ds->ds7);
278 DS7IOInit(ds);
279
280 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
281 if (header) {
282 memcpy(&ds->memory.ram[0x3FF800 >> 2], DS_CHIP_ID, 4);
283 memcpy(&ds->memory.ram[0x3FF804 >> 2], DS_CHIP_ID, 4);
284 memcpy(&ds->memory.ram[0x3FFC00 >> 2], DS_CHIP_ID, 4);
285 memcpy(&ds->memory.ram[0x3FFC04 >> 2], DS_CHIP_ID, 4);
286 memcpy(&ds->memory.ram[0x3FFE00 >> 2], header, 0x170);
287 DS7IOWrite32(ds, DS_REG_ROMCNT_LO, header->busTiming | 0x2700000);
288 // TODO: Error check
289 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
290 uint32_t base = header->arm7Base - DS_BASE_RAM;
291 uint32_t* basePointer = &ds->memory.ram[base >> 2];
292 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
293 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
294 }
295 cpu->gprs[12] = header->arm7Entry;
296 cpu->gprs[ARM_LR] = header->arm7Entry;
297 cpu->gprs[ARM_PC] = header->arm7Entry;
298 int currentCycles = 0;
299 ARM_WRITE_PC;
300
301 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
302 }
303}
304
305void DS9Reset(struct ARMCore* cpu) {
306 ARMSetPrivilegeMode(cpu, MODE_IRQ);
307 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
308 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
309 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
310 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
311 cpu->gprs[ARM_SP] = DS9_SP_BASE;
312
313 struct DS* ds = (struct DS*) cpu->master;
314 mTimingClear(&ds->ds9.timing);
315 CircleBufferInit(&ds->ds9.fifo, 64);
316 DSVideoReset(&ds->video);
317 DSDMAReset(&ds->ds9);
318 DS9IOInit(ds);
319
320 ds->activeCpu = cpu;
321 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
322 ds->cycleDrift = 0;
323 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
324
325 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
326 if (header) {
327 // TODO: Error check
328 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
329 uint32_t base = header->arm9Base - DS_BASE_RAM;
330 uint32_t* basePointer = &ds->memory.ram[base >> 2];
331 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
332 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
333 }
334 cpu->gprs[12] = header->arm9Entry;
335 cpu->gprs[ARM_LR] = header->arm9Entry;
336 cpu->gprs[ARM_PC] = header->arm9Entry;
337 int currentCycles = 0;
338 ARM_WRITE_PC;
339
340 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
341 }
342}
343
344static void DS7ProcessEvents(struct ARMCore* cpu) {
345 struct DS* ds = (struct DS*) cpu->master;
346 DSProcessEvents(&ds->ds7);
347}
348
349static void DS9ProcessEvents(struct ARMCore* cpu) {
350 struct DS* ds = (struct DS*) cpu->master;
351 DSProcessEvents(&ds->ds9);
352}
353
354static void DSProcessEvents(struct DSCommon* dscore) {
355 struct ARMCore* cpu = dscore->cpu;
356 struct DS* ds = dscore->p;
357 if (dscore->springIRQ && !cpu->cpsr.i) {
358 ARMRaiseIRQ(cpu);
359 dscore->springIRQ = 0;
360 }
361
362 int32_t nextEvent = cpu->nextEvent;
363 while (cpu->cycles >= nextEvent) {
364 int32_t cycles = cpu->cycles;
365
366 cpu->cycles = 0;
367 cpu->nextEvent = 0;
368
369#ifndef NDEBUG
370 if (cycles < 0) {
371 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
372 }
373#endif
374 nextEvent = cycles;
375 do {
376 nextEvent = mTimingTick(&dscore->timing, nextEvent);
377 } while (ds->cpuBlocked);
378
379 if (ds->earlyExit) {
380 ds->earlyExit = false;
381 break;
382 }
383
384 cpu->nextEvent = nextEvent;
385 if (cpu->halted) {
386 cpu->cycles = nextEvent;
387 }
388#ifndef NDEBUG
389 else if (nextEvent < 0) {
390 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
391 }
392#endif
393 }
394}
395
396void DSRunLoop(struct DS* ds) {
397 if (ds->activeCpu == ds->ds9.cpu) {
398 ARMv5RunLoop(ds->ds9.cpu);
399 } else {
400 ARMv4RunLoop(ds->ds7.cpu);
401 }
402}
403
404void DS7Step(struct DS* ds) {
405 int32_t pc = ds->ds7.cpu->gprs[ARM_PC];
406 do {
407 while (ds->activeCpu == ds->ds9.cpu) {
408 ARMv5RunLoop(ds->ds9.cpu);
409 }
410 ARMv4Run(ds->ds7.cpu);
411 } while (ds->ds7.cpu->halted || ds->ds7.cpu->gprs[ARM_PC] == pc);
412}
413
414void DS9Step(struct DS* ds) {
415 int32_t pc = ds->ds9.cpu->gprs[ARM_PC];
416 do {
417 while (ds->activeCpu == ds->ds7.cpu) {
418 ARMv4RunLoop(ds->ds7.cpu);
419 }
420 ARMv5Run(ds->ds9.cpu);
421 } while (ds->ds9.cpu->halted || ds->ds9.cpu->gprs[ARM_PC] == pc);
422}
423
424void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
425 ds->debugger = (struct ARMDebugger*) debugger->platform;
426 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
427 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
428 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
429 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
430}
431
432void DSDetachDebugger(struct DS* ds) {
433 ds->debugger = NULL;
434 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
435 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
436 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
437 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
438}
439
440bool DSLoadROM(struct DS* ds, struct VFile* vf) {
441 DSUnloadROM(ds);
442 ds->romVf = vf;
443 // TODO: error check
444 return true;
445}
446
447bool DSIsROM(struct VFile* vf) {
448 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
449 return false;
450 }
451 uint8_t signature[sizeof(DS_ROM_MAGIC)];
452 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
453 return false;
454 }
455 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
456}
457
458bool DSIsBIOS7(struct VFile* vf) {
459 size_t size = vf->size(vf);
460 void* data = NULL;
461 uint32_t crc;
462 if (size == DS7_SIZE_BIOS) {
463 data = vf->map(vf, size, MAP_READ);
464 }
465 if (!data) {
466 return false;
467 }
468 crc = doCrc32(data, size);
469 vf->unmap(vf, data, size);
470 return crc == DS7_BIOS_CHECKSUM;
471}
472
473bool DSIsBIOS9(struct VFile* vf) {
474 size_t size = vf->size(vf);
475 void* data = NULL;
476 uint32_t crc;
477 if (size == DS9_SIZE_BIOS) {
478 data = vf->map(vf, 0x1000, MAP_READ);
479 } else if (size == 0x1000) {
480 data = vf->map(vf, 0x1000, MAP_READ);
481 }
482 if (!data) {
483 return false;
484 }
485 crc = doCrc32(data, 0x1000);
486 vf->unmap(vf, data, 0x1000);
487 return crc == DS9_BIOS_CHECKSUM;
488}
489
490bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
491 size_t size = vf->size(vf);
492 void* data = NULL;
493 uint32_t crc;
494 if (size == DS7_SIZE_BIOS) {
495 data = vf->map(vf, size, MAP_READ);
496 } else if (size == 0x1000) {
497 data = calloc(DS9_SIZE_BIOS, 1);
498 vf->read(vf, data, size);
499 } else if (size == DS9_SIZE_BIOS) {
500 data = vf->map(vf, size, MAP_READ);
501 }
502 if (!data) {
503 return false;
504 }
505 crc = doCrc32(data, size);
506 if (crc == DS7_BIOS_CHECKSUM) {
507 ds->bios7Vf = vf;
508 ds->memory.bios7 = data;
509 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
510 } else if (crc == DS9_BIOS_CHECKSUM) {
511 ds->bios9Vf = vf;
512 ds->memory.bios9 = data;
513 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
514 } else {
515 mLOG(DS, WARN, "BIOS checksum incorrect");
516 vf->unmap(vf, data, size);
517 return false;
518 }
519 return true;
520}
521
522void DSGetGameCode(struct DS* ds, char* out) {
523 memset(out, 0, 8);
524 if (!ds->romVf) {
525 return;
526 }
527
528 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
529 // TODO: TWL-?
530 memcpy(out, "NTR-", 4);
531 memcpy(&out[4], &cart->id, 4);
532 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
533}
534
535void DSGetGameTitle(struct DS* ds, char* out) {
536 memset(out, 0, 12);
537 if (!ds->romVf) {
538 return;
539 }
540
541 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
542 memcpy(out, &cart->title, 12);
543 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
544}
545
546void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
547 struct DS* ds = (struct DS*) cpu->master;
548 if (ds->debugger) {
549 struct mDebuggerEntryInfo info = {
550 .address = _ARMPCAddress(cpu),
551 .opcode = opcode
552 };
553 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
554 }
555 // TODO: More sensible category?
556 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
557}
558
559void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
560 struct DS* ds = (struct DS*) cpu->master;
561 if ((opcode & 0xFFFF) == (redzoneInstruction & 0xFFFF)) {
562 int currentCycles = 0;
563 if (cpu->executionMode == MODE_THUMB) {
564 cpu->gprs[ARM_PC] -= WORD_SIZE_THUMB * 2;
565 THUMB_WRITE_PC;
566 } else {
567 cpu->gprs[ARM_PC] -= WORD_SIZE_ARM * 2;
568 ARM_WRITE_PC;
569 }
570 } else if (ds->debugger) {
571 struct mDebuggerEntryInfo info = {
572 .address = _ARMPCAddress(cpu),
573 .opcode = opcode
574 };
575 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
576 } else {
577 ARMRaiseUndefined(cpu);
578 }
579}
580
581void DSBreakpoint(struct ARMCore* cpu, int immediate) {
582 struct DS* ds = (struct DS*) cpu->master;
583 if (immediate >= CPU_COMPONENT_MAX) {
584 return;
585 }
586 switch (immediate) {
587 case CPU_COMPONENT_DEBUGGER:
588 if (ds->debugger) {
589 struct mDebuggerEntryInfo info = {
590 .address = _ARMPCAddress(cpu)
591 };
592 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
593 }
594 break;
595 default:
596 break;
597 }
598}
599
600void DS7TestIRQ(struct ARMCore* cpu) {
601 struct DS* ds = (struct DS*) cpu->master;
602 if (!ds->memory.io7[DS_REG_IME >> 1]) {
603 return;
604 }
605 uint32_t test = (ds->memory.io7[DS_REG_IE_LO >> 1] & ds->memory.io7[DS_REG_IF_LO >> 1]);
606 test |= (ds->memory.io7[DS_REG_IE_HI >> 1] & ds->memory.io7[DS_REG_IF_HI >> 1]) << 16;
607 if (test) {
608 ds->ds7.springIRQ = test;
609 cpu->nextEvent = cpu->cycles;
610 }
611}
612
613void DS9TestIRQ(struct ARMCore* cpu) {
614 struct DS* ds = (struct DS*) cpu->master;
615 if (!ds->memory.io9[DS_REG_IME >> 1]) {
616 return;
617 }
618 uint32_t test = (ds->memory.io9[DS_REG_IE_LO >> 1] & ds->memory.io9[DS_REG_IF_LO >> 1]);
619 test |= (ds->memory.io9[DS_REG_IE_HI >> 1] & ds->memory.io9[DS_REG_IF_HI >> 1]) << 16;
620 if (test) {
621 ds->ds9.springIRQ = test;
622 cpu->nextEvent = cpu->cycles;
623 }
624}
625
626static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
627 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
628}
629
630static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
631 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
632 switch (opcode2) {
633 case 0:
634 cpu->cp15.r2.d = value;
635 break;
636 case 1:
637 cpu->cp15.r2.i = value;
638 break;
639 default:
640 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
641 break;
642 }
643}
644
645static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
646 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
647 switch (opcode2) {
648 case 0:
649 cpu->cp15.r3.d = value;
650 break;
651 default:
652 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
653 break;
654 }
655}
656
657static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
658 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
659}
660
661static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
662 cpu->cp15.r6.region[crm] = value;
663 uint32_t base = ARMProtectionGetBase(value) << 12;
664 uint32_t size = 2 << ARMProtectionGetSize(value);
665 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
666}
667
668static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
669 switch (crm) {
670 case 0:
671 if (opcode2 == 4) {
672 ARMHalt(cpu);
673 return;
674 }
675 break;
676 }
677 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
678}
679
680static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
681 uint32_t base = ARMTCMControlGetBase(value) << 12;
682 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
683 struct DS* ds = (struct DS*) cpu->master;
684 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
685 switch (opcode2) {
686 case 0:
687 cpu->cp15.r9.d = value;
688 ds->memory.dtcmBase = base;
689 ds->memory.dtcmSize = size;
690 break;
691 case 1:
692 cpu->cp15.r9.i = value;
693 ds->memory.itcmSize = size;
694 break;
695 default:
696 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
697 break;
698 }
699}
700
701void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
702 switch (crn) {
703 default:
704 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
705 break;
706 case 0:
707 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
708 ARMRaiseUndefined(cpu);
709 break;
710 case 1:
711 _writeSysControl(cpu, crm, opcode2, value);
712 break;
713 case 2:
714 _writeCacheControl(cpu, crm, opcode2, value);
715 break;
716 case 3:
717 _writeWriteBufferControl(cpu, crm, opcode2, value);
718 break;
719 case 5:
720 _writeAccessControl(cpu, crm, opcode2, value);
721 break;
722 case 6:
723 _writeRegionConfiguration(cpu, crm, opcode2, value);
724 break;
725 case 7:
726 _writeCache(cpu, crm, opcode2, value);
727 break;
728 case 9:
729 _writeTCMControl(cpu, crm, opcode2, value);
730 break;
731 }
732}
733
734static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
735 switch (opcode2) {
736 case 0:
737 return cpu->cp15.r9.d;
738 case 1:
739 return cpu->cp15.r9.i;
740 default:
741 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
742 return 0;
743 }
744}
745
746uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
747 switch (crn) {
748 default:
749 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
750 return 0;
751 case 9:
752 return _readTCMControl(cpu, crm, opcode2);
753 }
754}
755
756void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
757 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
758 ARMRaiseIRQ(cpu);
759 }
760}
761void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
762 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
763 ARMRaiseIRQ(cpu);
764 }
765}
766
767void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
768 if (irq < 16) {
769 io[DS_REG_IF_LO >> 1] |= 1 << irq;
770 } else {
771 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
772 }
773
774 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
775 cpu->halted = 0;
776 if (io[DS_REG_IME >> 1]) {
777 ARMRaiseIRQ(cpu);
778 }
779 }
780}
781
782void DSFrameStarted(struct DS* ds) {
783 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
784 if (callbacks && callbacks->videoFrameStarted) {
785 callbacks->videoFrameStarted(callbacks->context);
786 }
787}
788
789void DSFrameEnded(struct DS* ds) {
790 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
791 if (callbacks && callbacks->videoFrameEnded) {
792 callbacks->videoFrameEnded(callbacks->context);
793 }
794}