1/* Copyright (c) 2013-2015 Jeffrey Pfau
   2 *
   3 * This Source Code Form is subject to the terms of the Mozilla Public
   4 * License, v. 2.0. If a copy of the MPL was not distributed with this
   5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
   6#include "memory.h"
   7
   8#include "macros.h"
   9
  10#include "decoder.h"
  11#include "gba/hardware.h"
  12#include "gba/io.h"
  13#include "gba/serialize.h"
  14#include "gba/hle-bios.h"
  15#include "util/memory.h"
  16
  17#define IDLE_LOOP_THRESHOLD 10000
  18
  19static uint32_t _popcount32(unsigned bits);
  20static uint32_t _deadbeef[2] = { 0xDEADBEEF, 0xFEEDFACE };
  21
  22static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
  23static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
  24
  25static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
  26static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
  27static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
  28static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
  29static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
  30static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
  31static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
  32
  33void GBAMemoryInit(struct GBA* gba) {
  34	struct ARMCore* cpu = gba->cpu;
  35	cpu->memory.load32 = GBALoad32;
  36	cpu->memory.load16 = GBALoad16;
  37	cpu->memory.load8 = GBALoad8;
  38	cpu->memory.loadMultiple = GBALoadMultiple;
  39	cpu->memory.store32 = GBAStore32;
  40	cpu->memory.store16 = GBAStore16;
  41	cpu->memory.store8 = GBAStore8;
  42	cpu->memory.storeMultiple = GBAStoreMultiple;
  43
  44	gba->memory.bios = (uint32_t*) hleBios;
  45	gba->memory.fullBios = 0;
  46	gba->memory.wram = 0;
  47	gba->memory.iwram = 0;
  48	gba->memory.rom = 0;
  49	gba->memory.hw.p = gba;
  50
  51	int i;
  52	for (i = 0; i < 16; ++i) {
  53		gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
  54		gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
  55		gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
  56		gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
  57		gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
  58		gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
  59		gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
  60		gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
  61	}
  62	for (; i < 256; ++i) {
  63		gba->memory.waitstatesNonseq16[i] = 0;
  64		gba->memory.waitstatesSeq16[i] = 0;
  65		gba->memory.waitstatesNonseq32[i] = 0;
  66		gba->memory.waitstatesSeq32[i] = 0;
  67	}
  68
  69	gba->memory.activeRegion = -1;
  70	cpu->memory.activeRegion = 0;
  71	cpu->memory.activeMask = 0;
  72	cpu->memory.setActiveRegion = GBASetActiveRegion;
  73	cpu->memory.activeSeqCycles32 = 0;
  74	cpu->memory.activeSeqCycles16 = 0;
  75	cpu->memory.activeNonseqCycles32 = 0;
  76	cpu->memory.activeNonseqCycles16 = 0;
  77	cpu->memory.activeUncachedCycles32 = 0;
  78	cpu->memory.activeUncachedCycles16 = 0;
  79	gba->memory.biosPrefetch = 0;
  80}
  81
  82void GBAMemoryDeinit(struct GBA* gba) {
  83	mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
  84	mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
  85	if (gba->memory.rom) {
  86		mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
  87	}
  88	GBASavedataDeinit(&gba->memory.savedata);
  89}
  90
  91void GBAMemoryReset(struct GBA* gba) {
  92	if (gba->memory.wram) {
  93		mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
  94	}
  95	gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
  96
  97	if (gba->memory.iwram) {
  98		mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
  99	}
 100	gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
 101
 102	memset(gba->memory.io, 0, sizeof(gba->memory.io));
 103	memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
 104	int i;
 105	for (i = 0; i < 4; ++i) {
 106		gba->memory.dma[i].count = 0x4000;
 107		gba->memory.dma[i].nextEvent = INT_MAX;
 108	}
 109	gba->memory.dma[3].count = 0x10000;
 110	gba->memory.activeDMA = -1;
 111	gba->memory.nextDMA = INT_MAX;
 112	gba->memory.eventDiff = 0;
 113
 114	if (!gba->memory.wram || !gba->memory.iwram) {
 115		GBAMemoryDeinit(gba);
 116		GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
 117	}
 118}
 119
 120static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
 121	struct ARMInstructionInfo info;
 122	uint32_t nextAddress = address;
 123	memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
 124	if (cpu->executionMode == MODE_THUMB) {
 125		while (true) {
 126			uint16_t opcode;
 127			LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
 128			ARMDecodeThumb(opcode, &info);
 129			switch (info.branchType) {
 130			case ARM_BRANCH_NONE:
 131				if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
 132					if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
 133						gba->idleDetectionStep = -1;
 134						return;
 135					}
 136					uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
 137					uint32_t offset = 0;
 138					if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
 139						offset = info.memory.offset.immediate;
 140					} else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
 141						int reg = info.memory.offset.reg;
 142						if (gba->cachedRegisters[reg]) {
 143							gba->idleDetectionStep = -1;
 144							return;
 145						}
 146						offset = gba->cachedRegisters[reg];
 147					}
 148					if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
 149						loadAddress -= offset;
 150					} else {
 151						loadAddress += offset;
 152					}
 153					if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
 154						gba->idleDetectionStep = -1;
 155						return;
 156					}
 157					if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
 158						gba->taintedRegisters[info.op1.reg] = true;
 159					} else {
 160						switch (info.memory.width) {
 161						case 1:
 162							gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
 163							break;
 164						case 2:
 165							gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
 166							break;
 167						case 4:
 168							gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
 169							break;
 170						}
 171					}
 172				} else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
 173					gba->taintedRegisters[info.op1.reg] = true;
 174				}
 175				nextAddress += WORD_SIZE_THUMB;
 176				break;
 177			case ARM_BRANCH:
 178				if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
 179					gba->idleLoop = address;
 180					gba->idleOptimization = IDLE_LOOP_REMOVE;
 181				}
 182				gba->idleDetectionStep = -1;
 183				return;
 184			default:
 185				gba->idleDetectionStep = -1;
 186				return;
 187			}
 188		}
 189	} else {
 190		gba->idleDetectionStep = -1;
 191	}
 192}
 193
 194static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
 195	struct GBA* gba = (struct GBA*) cpu->master;
 196	struct GBAMemory* memory = &gba->memory;
 197
 198	int newRegion = address >> BASE_OFFSET;
 199	if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
 200		if (address == gba->lastJump && address == gba->idleLoop) {
 201			GBAHalt(gba);
 202		} else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
 203			if (address == gba->lastJump) {
 204				switch (gba->idleDetectionStep) {
 205				case 0:
 206					memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
 207					++gba->idleDetectionStep;
 208					break;
 209				case 1:
 210					if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
 211						gba->idleDetectionStep = -1;
 212						++gba->idleDetectionFailures;
 213						if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
 214							gba->idleOptimization = IDLE_LOOP_IGNORE;
 215						}
 216						break;
 217					}
 218					_analyzeForIdleLoop(gba, cpu, address);
 219					break;
 220				}
 221			} else {
 222				gba->idleDetectionStep = 0;
 223			}
 224		}
 225	}
 226
 227	gba->lastJump = address;
 228	if (newRegion == memory->activeRegion) {
 229		return;
 230	}
 231
 232	if (memory->activeRegion == REGION_BIOS) {
 233		memory->biosPrefetch = cpu->prefetch[1];
 234	}
 235	memory->activeRegion = newRegion;
 236	switch (address & ~OFFSET_MASK) {
 237	case BASE_BIOS:
 238		cpu->memory.activeRegion = memory->bios;
 239		cpu->memory.activeMask = SIZE_BIOS - 1;
 240		break;
 241	case BASE_WORKING_RAM:
 242		cpu->memory.activeRegion = memory->wram;
 243		cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
 244		break;
 245	case BASE_WORKING_IRAM:
 246		cpu->memory.activeRegion = memory->iwram;
 247		cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
 248		break;
 249	case BASE_VRAM:
 250		cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
 251		cpu->memory.activeMask = 0x0000FFFF;
 252		break;
 253	case BASE_CART0:
 254	case BASE_CART0_EX:
 255	case BASE_CART1:
 256	case BASE_CART1_EX:
 257	case BASE_CART2:
 258	case BASE_CART2_EX:
 259		cpu->memory.activeRegion = memory->rom;
 260		cpu->memory.activeMask = SIZE_CART0 - 1;
 261		break;
 262	default:
 263		cpu->memory.activeRegion = _deadbeef;
 264		cpu->memory.activeMask = 0;
 265		GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
 266		break;
 267	}
 268	cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
 269	cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
 270	cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
 271	cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
 272	cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
 273	cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
 274}
 275
 276#define LOAD_BAD \
 277	GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
 278	if (gba->performingDMA) { \
 279		value = gba->bus; \
 280	} else { \
 281		value = cpu->prefetch[1]; \
 282		if (cpu->executionMode == MODE_THUMB) { \
 283			value |= value << 16; \
 284		} \
 285	}
 286
 287#define LOAD_BIOS \
 288	if (address < SIZE_BIOS) { \
 289		if (memory->activeRegion == REGION_BIOS) { \
 290			LOAD_32(value, address, memory->bios); \
 291		} else { \
 292			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
 293			value = memory->biosPrefetch; \
 294		} \
 295	} else { \
 296		LOAD_BAD; \
 297	}
 298
 299#define LOAD_WORKING_RAM \
 300	LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
 301	wait += waitstatesRegion[REGION_WORKING_RAM];
 302
 303#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 304#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
 305
 306#define LOAD_PALETTE_RAM \
 307	LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
 308	++wait;
 309
 310#define LOAD_VRAM \
 311	if ((address & 0x0001FFFF) < SIZE_VRAM) { \
 312		LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
 313	} else { \
 314		LOAD_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
 315	} \
 316	++wait;
 317
 318#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 319
 320#define LOAD_CART \
 321	wait += waitstatesRegion[address >> BASE_OFFSET]; \
 322	if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
 323		LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom); \
 324	} else { \
 325		GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
 326		value = (address >> 1) & 0xFFFF; \
 327		value |= value << 16; \
 328	}
 329
 330#define LOAD_SRAM \
 331	wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
 332	value = GBALoad8(cpu, address, 0); \
 333	value |= value << 8; \
 334	value |= value << 16;
 335
 336uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 337	struct GBA* gba = (struct GBA*) cpu->master;
 338	struct GBAMemory* memory = &gba->memory;
 339	uint32_t value = 0;
 340	int wait = 0;
 341	char* waitstatesRegion = memory->waitstatesNonseq32;
 342
 343	switch (address >> BASE_OFFSET) {
 344	case REGION_BIOS:
 345		LOAD_BIOS;
 346		break;
 347	case REGION_WORKING_RAM:
 348		LOAD_WORKING_RAM;
 349		break;
 350	case REGION_WORKING_IRAM:
 351		LOAD_WORKING_IRAM;
 352		break;
 353	case REGION_IO:
 354		LOAD_IO;
 355		break;
 356	case REGION_PALETTE_RAM:
 357		LOAD_PALETTE_RAM;
 358		break;
 359	case REGION_VRAM:
 360		LOAD_VRAM;
 361		break;
 362	case REGION_OAM:
 363		LOAD_OAM;
 364		break;
 365	case REGION_CART0:
 366	case REGION_CART0_EX:
 367	case REGION_CART1:
 368	case REGION_CART1_EX:
 369	case REGION_CART2:
 370	case REGION_CART2_EX:
 371		LOAD_CART;
 372		break;
 373	case REGION_CART_SRAM:
 374	case REGION_CART_SRAM_MIRROR:
 375		LOAD_SRAM;
 376		break;
 377	default:
 378		LOAD_BAD;
 379		break;
 380	}
 381
 382	if (cycleCounter) {
 383		*cycleCounter += 1 + wait;
 384	}
 385	// Unaligned 32-bit loads are "rotated" so they make some semblance of sense
 386	int rotate = (address & 3) << 3;
 387	return ROR(value, rotate);
 388}
 389
 390uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 391	struct GBA* gba = (struct GBA*) cpu->master;
 392	struct GBAMemory* memory = &gba->memory;
 393	uint32_t value = 0;
 394	int wait = 0;
 395
 396	switch (address >> BASE_OFFSET) {
 397	case REGION_BIOS:
 398		if (address < SIZE_BIOS) {
 399			if (memory->activeRegion == REGION_BIOS) {
 400				LOAD_16(value, address, memory->bios);
 401			} else {
 402				GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
 403				LOAD_16(value, address & 2, &memory->biosPrefetch);
 404			}
 405		} else {
 406			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
 407			if (gba->performingDMA) {
 408				LOAD_16(value, address & 2, &gba->bus);
 409			} else {
 410				uint32_t prefetch = cpu->prefetch[1];
 411				if (cpu->executionMode == MODE_THUMB) {
 412					prefetch |= prefetch << 16;
 413				}
 414				LOAD_16(value, address & 2, &prefetch);
 415			}
 416		}
 417		break;
 418	case REGION_WORKING_RAM:
 419		LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 420		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 421		break;
 422	case REGION_WORKING_IRAM:
 423		LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 424		break;
 425	case REGION_IO:
 426		value = GBAIORead(gba, address & (SIZE_IO - 1));
 427		break;
 428	case REGION_PALETTE_RAM:
 429		LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 430		break;
 431	case REGION_VRAM:
 432		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 433			LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 434		} else {
 435			LOAD_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 436		}
 437		break;
 438	case REGION_OAM:
 439		LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 440		break;
 441	case REGION_CART0:
 442	case REGION_CART0_EX:
 443	case REGION_CART1:
 444	case REGION_CART1_EX:
 445	case REGION_CART2:
 446		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 447		if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 448			LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
 449		} else {
 450			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
 451			value = (address >> 1) & 0xFFFF; \
 452		}
 453		break;
 454	case REGION_CART2_EX:
 455		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 456		if (memory->savedata.type == SAVEDATA_EEPROM) {
 457			value = GBASavedataReadEEPROM(&memory->savedata);
 458		} else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 459			LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
 460		} else {
 461			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
 462			value = (address >> 1) & 0xFFFF; \
 463		}
 464		break;
 465	case REGION_CART_SRAM:
 466	case REGION_CART_SRAM_MIRROR:
 467		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 468		value = GBALoad8(cpu, address, 0);
 469		value |= value << 8;
 470		break;
 471	default:
 472		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
 473		if (gba->performingDMA) {
 474			LOAD_16(value, address & 2, &gba->bus);
 475		} else {
 476			uint32_t prefetch = cpu->prefetch[1];
 477			if (cpu->executionMode == MODE_THUMB) {
 478				prefetch |= prefetch << 16;
 479			}
 480			LOAD_16(value, address & 2, &prefetch);
 481		}
 482		break;
 483	}
 484
 485	if (cycleCounter) {
 486		*cycleCounter += 1 + wait;
 487	}
 488	// Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
 489	int rotate = (address & 1) << 3;
 490	return ROR(value, rotate);
 491}
 492
 493uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 494	struct GBA* gba = (struct GBA*) cpu->master;
 495	struct GBAMemory* memory = &gba->memory;
 496	uint8_t value = 0;
 497	int wait = 0;
 498
 499	switch (address >> BASE_OFFSET) {
 500	case REGION_BIOS:
 501		if (address < SIZE_BIOS) {
 502			if (memory->activeRegion == REGION_BIOS) {
 503				value = ((int8_t*) memory->bios)[address];
 504			} else {
 505				GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
 506				value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
 507			}
 508		} else {
 509			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
 510			if (gba->performingDMA) {
 511				value = ((uint8_t*) &gba->bus)[address & 3];
 512			} else {
 513				uint32_t prefetch = cpu->prefetch[1];
 514				if (cpu->executionMode == MODE_THUMB) {
 515					prefetch |= prefetch << 16;
 516				}
 517				value = ((uint8_t*) &prefetch)[address & 3];
 518			}
 519		}
 520		break;
 521	case REGION_WORKING_RAM:
 522		value = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
 523		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 524		break;
 525	case REGION_WORKING_IRAM:
 526		value = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
 527		break;
 528	case REGION_IO:
 529		value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
 530		break;
 531	case REGION_PALETTE_RAM:
 532		value = ((int8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
 533		break;
 534	case REGION_VRAM:
 535		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 536			value = ((int8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
 537		} else {
 538			value = ((int8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
 539		}
 540		break;
 541	case REGION_OAM:
 542		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
 543		break;
 544	case REGION_CART0:
 545	case REGION_CART0_EX:
 546	case REGION_CART1:
 547	case REGION_CART1_EX:
 548	case REGION_CART2:
 549	case REGION_CART2_EX:
 550		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 551		if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 552			value = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
 553		} else {
 554			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
 555			value = (address >> 1) & 0xFF; \
 556		}
 557		break;
 558	case REGION_CART_SRAM:
 559	case REGION_CART_SRAM_MIRROR:
 560		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 561		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 562			GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
 563			GBASavedataInitSRAM(&memory->savedata);
 564		}
 565		if (memory->savedata.type == SAVEDATA_SRAM) {
 566			value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
 567		} else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
 568			value = GBASavedataReadFlash(&memory->savedata, address);
 569		} else if (memory->hw.devices & HW_TILT) {
 570			value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
 571		} else {
 572			GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
 573			value = 0xFF;
 574		}
 575		break;
 576	default:
 577		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
 578		if (gba->performingDMA) {
 579			value = ((uint8_t*) &gba->bus)[address & 3];
 580		} else {
 581			uint32_t prefetch = cpu->prefetch[1];
 582			if (cpu->executionMode == MODE_THUMB) {
 583				prefetch |= prefetch << 16;
 584			}
 585			value = ((uint8_t*) &prefetch)[address & 3];
 586		}
 587		break;
 588	}
 589
 590	if (cycleCounter) {
 591		*cycleCounter += 1 + wait;
 592	}
 593	return value;
 594}
 595
 596#define STORE_WORKING_RAM \
 597	STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
 598	wait += waitstatesRegion[REGION_WORKING_RAM];
 599
 600#define STORE_WORKING_IRAM \
 601	STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 602
 603#define STORE_IO \
 604	GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
 605
 606#define STORE_PALETTE_RAM \
 607	STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
 608	gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16); \
 609	++wait; \
 610	gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 611
 612#define STORE_VRAM \
 613	if ((address & 0x0001FFFF) < SIZE_VRAM) { \
 614		STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
 615	} else { \
 616		STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
 617	} \
 618	++wait;
 619
 620#define STORE_OAM \
 621	STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw); \
 622	gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
 623	gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
 624
 625#define STORE_CART \
 626	wait += waitstatesRegion[address >> BASE_OFFSET]; \
 627	GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
 628
 629#define STORE_SRAM \
 630	GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
 631
 632#define STORE_BAD \
 633	GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
 634
 635void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
 636	struct GBA* gba = (struct GBA*) cpu->master;
 637	struct GBAMemory* memory = &gba->memory;
 638	int wait = 0;
 639	char* waitstatesRegion = memory->waitstatesNonseq32;
 640
 641	switch (address >> BASE_OFFSET) {
 642	case REGION_WORKING_RAM:
 643		STORE_WORKING_RAM;
 644		break;
 645	case REGION_WORKING_IRAM:
 646		STORE_WORKING_IRAM
 647		break;
 648	case REGION_IO:
 649		STORE_IO;
 650		break;
 651	case REGION_PALETTE_RAM:
 652		STORE_PALETTE_RAM;
 653		break;
 654	case REGION_VRAM:
 655		STORE_VRAM;
 656		break;
 657	case REGION_OAM:
 658		STORE_OAM;
 659		break;
 660	case REGION_CART0:
 661	case REGION_CART0_EX:
 662	case REGION_CART1:
 663	case REGION_CART1_EX:
 664	case REGION_CART2:
 665	case REGION_CART2_EX:
 666		STORE_CART;
 667		break;
 668	case REGION_CART_SRAM:
 669	case REGION_CART_SRAM_MIRROR:
 670		STORE_SRAM;
 671		break;
 672	default:
 673		STORE_BAD;
 674		break;
 675	}
 676
 677	if (cycleCounter) {
 678		*cycleCounter += 1 + wait;
 679	}
 680}
 681
 682void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
 683	struct GBA* gba = (struct GBA*) cpu->master;
 684	struct GBAMemory* memory = &gba->memory;
 685	int wait = 0;
 686
 687	switch (address >> BASE_OFFSET) {
 688	case REGION_WORKING_RAM:
 689		STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 690		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 691		break;
 692	case REGION_WORKING_IRAM:
 693		STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 694		break;
 695	case REGION_IO:
 696		GBAIOWrite(gba, address & (SIZE_IO - 1), value);
 697		break;
 698	case REGION_PALETTE_RAM:
 699		STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 700		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 701		break;
 702	case REGION_VRAM:
 703		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 704			STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 705		} else {
 706			STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 707		}
 708		break;
 709	case REGION_OAM:
 710		STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 711		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 712		break;
 713	case REGION_CART0:
 714		if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFF)) {
 715			uint32_t reg = address & 0xFFFFFF;
 716			GBAHardwareGPIOWrite(&memory->hw, reg, value);
 717		} else {
 718			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
 719		}
 720		break;
 721	case REGION_CART2_EX:
 722		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 723			GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
 724			GBASavedataInitEEPROM(&memory->savedata);
 725		}
 726		GBASavedataWriteEEPROM(&memory->savedata, value, 1);
 727		break;
 728	case REGION_CART_SRAM:
 729	case REGION_CART_SRAM_MIRROR:
 730		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
 731		break;
 732	default:
 733		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
 734		break;
 735	}
 736
 737	if (cycleCounter) {
 738		*cycleCounter += 1 + wait;
 739	}
 740}
 741
 742void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
 743	struct GBA* gba = (struct GBA*) cpu->master;
 744	struct GBAMemory* memory = &gba->memory;
 745	int wait = 0;
 746
 747	switch (address >> BASE_OFFSET) {
 748	case REGION_WORKING_RAM:
 749		((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
 750		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 751		break;
 752	case REGION_WORKING_IRAM:
 753		((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
 754		break;
 755	case REGION_IO:
 756		GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
 757		break;
 758	case REGION_PALETTE_RAM:
 759		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
 760		break;
 761	case REGION_VRAM:
 762		if (address >= 0x06018000) {
 763			// TODO: check BG mode
 764			GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
 765			break;
 766		}
 767		((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
 768		((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
 769		break;
 770	case REGION_OAM:
 771		GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
 772		break;
 773	case REGION_CART0:
 774		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
 775		break;
 776	case REGION_CART_SRAM:
 777	case REGION_CART_SRAM_MIRROR:
 778		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 779			if (address == SAVEDATA_FLASH_BASE) {
 780				GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
 781				GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
 782			} else {
 783				GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
 784				GBASavedataInitSRAM(&memory->savedata);
 785			}
 786		}
 787		if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
 788			GBASavedataWriteFlash(&memory->savedata, address, value);
 789		} else if (memory->savedata.type == SAVEDATA_SRAM) {
 790			memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
 791		} else if (memory->hw.devices & HW_TILT) {
 792			GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
 793		} else {
 794			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 795		}
 796		wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
 797		break;
 798	default:
 799		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
 800		break;
 801	}
 802
 803	if (cycleCounter) {
 804		*cycleCounter += 1 + wait;
 805	}
 806}
 807
 808void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
 809	struct GBA* gba = (struct GBA*) cpu->master;
 810	struct GBAMemory* memory = &gba->memory;
 811	int32_t oldValue = -1;
 812
 813	switch (address >> BASE_OFFSET) {
 814	case REGION_WORKING_RAM:
 815		LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
 816		STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 817		break;
 818	case REGION_WORKING_IRAM:
 819		LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 820		STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 821		break;
 822	case REGION_IO:
 823		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
 824		break;
 825	case REGION_PALETTE_RAM:
 826		LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 827		STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 828		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 829		gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
 830		break;
 831	case REGION_VRAM:
 832		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 833			LOAD_32(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
 834			STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
 835		} else {
 836			LOAD_32(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
 837			STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
 838		}
 839		break;
 840	case REGION_OAM:
 841		LOAD_32(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
 842		STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 843		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 844		gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 1)) + 2) >> 1);
 845		break;
 846	case REGION_CART0:
 847	case REGION_CART0_EX:
 848	case REGION_CART1:
 849	case REGION_CART1_EX:
 850	case REGION_CART2:
 851	case REGION_CART2_EX:
 852		if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
 853			LOAD_32(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
 854			STORE_32(value, address & (SIZE_CART0 - 1), gba->memory.rom);
 855		} else {
 856			GBALog(gba, GBA_LOG_WARN, "Bad memory Patch32: 0x%08X", address);
 857		}
 858		break;
 859	case REGION_CART_SRAM:
 860	case REGION_CART_SRAM_MIRROR:
 861		if (memory->savedata.type == SAVEDATA_SRAM) {
 862			LOAD_32(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 863			STORE_32(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 864		} else {
 865			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 866		}
 867		break;
 868	default:
 869		GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
 870		break;
 871	}
 872	if (old) {
 873		*old = oldValue;
 874	}
 875}
 876
 877void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
 878	struct GBA* gba = (struct GBA*) cpu->master;
 879	struct GBAMemory* memory = &gba->memory;
 880	int16_t oldValue = -1;
 881
 882	switch (address >> BASE_OFFSET) {
 883	case REGION_WORKING_RAM:
 884		LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
 885		STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 886		break;
 887	case REGION_WORKING_IRAM:
 888		LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 889		STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 890		break;
 891	case REGION_IO:
 892		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
 893		break;
 894	case REGION_PALETTE_RAM:
 895		LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 896		STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 897		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 898		break;
 899	case REGION_VRAM:
 900		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 901			LOAD_16(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
 902			STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 903		} else {
 904			LOAD_16(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
 905			STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 906		}
 907		break;
 908	case REGION_OAM:
 909		LOAD_16(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
 910		STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 911		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 912		break;
 913	case REGION_CART0:
 914	case REGION_CART0_EX:
 915	case REGION_CART1:
 916	case REGION_CART1_EX:
 917	case REGION_CART2:
 918	case REGION_CART2_EX:
 919		if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
 920			LOAD_16(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
 921			STORE_16(value, address & (SIZE_CART0 - 1), gba->memory.rom);
 922		} else {
 923			GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
 924		}
 925		break;
 926	case REGION_CART_SRAM:
 927	case REGION_CART_SRAM_MIRROR:
 928		if (memory->savedata.type == SAVEDATA_SRAM) {
 929			LOAD_16(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 930			STORE_16(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 931		} else {
 932			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 933		}
 934		break;
 935	default:
 936		GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
 937		break;
 938	}
 939	if (old) {
 940		*old = oldValue;
 941	}
 942}
 943
 944#define LDM_LOOP(LDM) \
 945	for (i = 0; i < 16; i += 4) { \
 946		if (UNLIKELY(mask & (1 << i))) { \
 947			LDM; \
 948			waitstatesRegion = memory->waitstatesSeq32; \
 949			cpu->gprs[i] = value; \
 950			++wait; \
 951			address += 4; \
 952		} \
 953		if (UNLIKELY(mask & (2 << i))) { \
 954			LDM; \
 955			waitstatesRegion = memory->waitstatesSeq32; \
 956			cpu->gprs[i + 1] = value; \
 957			++wait; \
 958			address += 4; \
 959		} \
 960		if (UNLIKELY(mask & (4 << i))) { \
 961			LDM; \
 962			waitstatesRegion = memory->waitstatesSeq32; \
 963			cpu->gprs[i + 2] = value; \
 964			++wait; \
 965			address += 4; \
 966		} \
 967		if (UNLIKELY(mask & (8 << i))) { \
 968			LDM; \
 969			waitstatesRegion = memory->waitstatesSeq32; \
 970			cpu->gprs[i + 3] = value; \
 971			++wait; \
 972			address += 4; \
 973		} \
 974	}
 975
 976uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
 977	struct GBA* gba = (struct GBA*) cpu->master;
 978	struct GBAMemory* memory = &gba->memory;
 979	uint32_t value;
 980	int wait = 0;
 981	char* waitstatesRegion = memory->waitstatesNonseq32;
 982
 983	int i;
 984	int offset = 4;
 985	int popcount = 0;
 986	if (direction & LSM_D) {
 987		offset = -4;
 988		popcount = _popcount32(mask);
 989		address -= (popcount << 2) - 4;
 990	}
 991
 992	if (direction & LSM_B) {
 993		address += offset;
 994	}
 995
 996	uint32_t addressMisalign = address & 0x3;
 997	address &= 0xFFFFFFFC;
 998
 999	switch (address >> BASE_OFFSET) {
1000	case REGION_BIOS:
1001		LDM_LOOP(LOAD_BIOS);
1002		break;
1003	case REGION_WORKING_RAM:
1004		LDM_LOOP(LOAD_WORKING_RAM);
1005		break;
1006	case REGION_WORKING_IRAM:
1007		LDM_LOOP(LOAD_WORKING_IRAM);
1008		break;
1009	case REGION_IO:
1010		LDM_LOOP(LOAD_IO);
1011		break;
1012	case REGION_PALETTE_RAM:
1013		LDM_LOOP(LOAD_PALETTE_RAM);
1014		break;
1015	case REGION_VRAM:
1016		LDM_LOOP(LOAD_VRAM);
1017		break;
1018	case REGION_OAM:
1019		LDM_LOOP(LOAD_OAM);
1020		break;
1021	case REGION_CART0:
1022	case REGION_CART0_EX:
1023	case REGION_CART1:
1024	case REGION_CART1_EX:
1025	case REGION_CART2:
1026	case REGION_CART2_EX:
1027		LDM_LOOP(LOAD_CART);
1028		break;
1029	case REGION_CART_SRAM:
1030	case REGION_CART_SRAM_MIRROR:
1031		LDM_LOOP(LOAD_SRAM);
1032		break;
1033	default:
1034		LDM_LOOP(LOAD_BAD);
1035		break;
1036	}
1037
1038	if (cycleCounter) {
1039		*cycleCounter += wait;
1040	}
1041
1042	if (direction & LSM_B) {
1043		address -= offset;
1044	}
1045
1046	if (direction & LSM_D) {
1047		address -= (popcount << 2) + 4;
1048	}
1049
1050	return address | addressMisalign;
1051}
1052
1053#define STM_LOOP(STM) \
1054	for (i = 0; i < 16; i += 4) { \
1055		if (UNLIKELY(mask & (1 << i))) { \
1056			value = cpu->gprs[i]; \
1057			STM; \
1058			waitstatesRegion = memory->waitstatesSeq32; \
1059			++wait; \
1060			address += 4; \
1061		} \
1062		if (UNLIKELY(mask & (2 << i))) { \
1063			value = cpu->gprs[i + 1]; \
1064			STM; \
1065			waitstatesRegion = memory->waitstatesSeq32; \
1066			++wait; \
1067			address += 4; \
1068		} \
1069		if (UNLIKELY(mask & (4 << i))) { \
1070			value = cpu->gprs[i + 2]; \
1071			STM; \
1072			waitstatesRegion = memory->waitstatesSeq32; \
1073			++wait; \
1074			address += 4; \
1075		} \
1076		if (UNLIKELY(mask & (8 << i))) { \
1077			value = cpu->gprs[i + 3]; \
1078			STM; \
1079			waitstatesRegion = memory->waitstatesSeq32; \
1080			++wait; \
1081			address += 4; \
1082		} \
1083	}
1084
1085uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1086	struct GBA* gba = (struct GBA*) cpu->master;
1087	struct GBAMemory* memory = &gba->memory;
1088	uint32_t value;
1089	int wait = 0;
1090	char* waitstatesRegion = memory->waitstatesNonseq32;
1091
1092	int i;
1093	int offset = 4;
1094	int popcount = 0;
1095	if (direction & LSM_D) {
1096		offset = -4;
1097		popcount = _popcount32(mask);
1098		address -= (popcount << 2) - 4;
1099	}
1100
1101	if (direction & LSM_B) {
1102		address += offset;
1103	}
1104
1105	uint32_t addressMisalign = address & 0x3;
1106	address &= 0xFFFFFFFC;
1107
1108	switch (address >> BASE_OFFSET) {
1109	case REGION_WORKING_RAM:
1110		STM_LOOP(STORE_WORKING_RAM);
1111		break;
1112	case REGION_WORKING_IRAM:
1113		STM_LOOP(STORE_WORKING_IRAM);
1114		break;
1115	case REGION_IO:
1116		STM_LOOP(STORE_IO);
1117		break;
1118	case REGION_PALETTE_RAM:
1119		STM_LOOP(STORE_PALETTE_RAM);
1120		break;
1121	case REGION_VRAM:
1122		STM_LOOP(STORE_VRAM);
1123		break;
1124	case REGION_OAM:
1125		STM_LOOP(STORE_OAM);
1126		break;
1127	case REGION_CART0:
1128	case REGION_CART0_EX:
1129	case REGION_CART1:
1130	case REGION_CART1_EX:
1131	case REGION_CART2:
1132	case REGION_CART2_EX:
1133		STM_LOOP(STORE_CART);
1134		break;
1135	case REGION_CART_SRAM:
1136	case REGION_CART_SRAM_MIRROR:
1137		STM_LOOP(STORE_SRAM);
1138		break;
1139	default:
1140		STM_LOOP(STORE_BAD);
1141		break;
1142	}
1143
1144	if (cycleCounter) {
1145		*cycleCounter += wait;
1146	}
1147
1148	if (direction & LSM_B) {
1149		address -= offset;
1150	}
1151
1152	if (direction & LSM_D) {
1153		address -= (popcount << 2) + 4;
1154	}
1155
1156	return address | addressMisalign;
1157}
1158
1159void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1160	struct GBAMemory* memory = &gba->memory;
1161	struct ARMCore* cpu = gba->cpu;
1162	int sram = parameters & 0x0003;
1163	int ws0 = (parameters & 0x000C) >> 2;
1164	int ws0seq = (parameters & 0x0010) >> 4;
1165	int ws1 = (parameters & 0x0060) >> 5;
1166	int ws1seq = (parameters & 0x0080) >> 7;
1167	int ws2 = (parameters & 0x0300) >> 8;
1168	int ws2seq = (parameters & 0x0400) >> 10;
1169	int prefetch = parameters & 0x4000;
1170
1171	memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] =  GBA_ROM_WAITSTATES[sram];
1172	memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1173	memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1174	memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1175
1176	memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1177	memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1178	memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1179
1180	memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1181	memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1182	memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1183
1184	memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1185	memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1186	memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1187
1188	memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1189	memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1190	memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1191
1192	if (!prefetch) {
1193		memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
1194		memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
1195		memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
1196
1197		memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
1198		memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
1199		memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
1200
1201		memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
1202		memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
1203		memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
1204
1205		memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
1206		memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
1207		memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
1208	} else {
1209		memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
1210		memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
1211		memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
1212
1213		memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
1214		memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
1215		memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
1216
1217		memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
1218		memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
1219		memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
1220
1221		memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
1222		memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
1223		memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
1224	}
1225
1226	cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
1227	cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
1228
1229	cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
1230	cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
1231
1232	cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1233	cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1234}
1235
1236void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1237	struct GBAMemory* memory = &gba->memory;
1238	memory->dma[dma].source = address & 0x0FFFFFFE;
1239}
1240
1241void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1242	struct GBAMemory* memory = &gba->memory;
1243	memory->dma[dma].dest = address & 0x0FFFFFFE;
1244}
1245
1246void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1247	struct GBAMemory* memory = &gba->memory;
1248	memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1249}
1250
1251uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1252	struct GBAMemory* memory = &gba->memory;
1253	struct GBADMA* currentDma = &memory->dma[dma];
1254	int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1255	currentDma->reg = control;
1256
1257	if (GBADMARegisterIsDRQ(currentDma->reg)) {
1258		GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1259	}
1260
1261	if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1262		currentDma->nextSource = currentDma->source;
1263		currentDma->nextDest = currentDma->dest;
1264		currentDma->nextCount = currentDma->count;
1265		GBAMemoryScheduleDMA(gba, dma, currentDma);
1266	}
1267	// If the DMA has already occurred, this value might have changed since the function started
1268	return currentDma->reg;
1269};
1270
1271void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1272	struct ARMCore* cpu = gba->cpu;
1273	switch (GBADMARegisterGetTiming(info->reg)) {
1274	case DMA_TIMING_NOW:
1275		info->nextEvent = cpu->cycles;
1276		GBAMemoryUpdateDMAs(gba, 0);
1277		break;
1278	case DMA_TIMING_HBLANK:
1279		// Handled implicitly
1280		info->nextEvent = INT_MAX;
1281		break;
1282	case DMA_TIMING_VBLANK:
1283		// Handled implicitly
1284		info->nextEvent = INT_MAX;
1285		break;
1286	case DMA_TIMING_CUSTOM:
1287		info->nextEvent = INT_MAX;
1288		switch (number) {
1289		case 0:
1290			GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1291			break;
1292		case 1:
1293		case 2:
1294			GBAAudioScheduleFifoDma(&gba->audio, number, info);
1295			break;
1296		case 3:
1297			// GBAVideoScheduleVCaptureDma(dma, info);
1298			break;
1299		}
1300	}
1301}
1302
1303void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1304	struct GBAMemory* memory = &gba->memory;
1305	struct GBADMA* dma;
1306	int i;
1307	for (i = 0; i < 4; ++i) {
1308		dma = &memory->dma[i];
1309		if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1310			dma->nextEvent = cycles;
1311		}
1312	}
1313	GBAMemoryUpdateDMAs(gba, 0);
1314}
1315
1316void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1317	struct GBAMemory* memory = &gba->memory;
1318	struct GBADMA* dma;
1319	int i;
1320	for (i = 0; i < 4; ++i) {
1321		dma = &memory->dma[i];
1322		if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1323			dma->nextEvent = cycles;
1324		}
1325	}
1326	GBAMemoryUpdateDMAs(gba, 0);
1327}
1328
1329int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1330	struct GBAMemory* memory = &gba->memory;
1331	if (memory->nextDMA == INT_MAX) {
1332		return INT_MAX;
1333	}
1334	memory->nextDMA -= cycles;
1335	memory->eventDiff += cycles;
1336	if (memory->nextDMA <= 0) {
1337		struct GBADMA* dma = &memory->dma[memory->activeDMA];
1338		GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1339		GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1340		memory->eventDiff = 0;
1341	}
1342	return memory->nextDMA;
1343}
1344
1345void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1346	int i;
1347	struct GBAMemory* memory = &gba->memory;
1348	struct ARMCore* cpu = gba->cpu;
1349	memory->activeDMA = -1;
1350	memory->nextDMA = INT_MAX;
1351	for (i = 3; i >= 0; --i) {
1352		struct GBADMA* dma = &memory->dma[i];
1353		if (dma->nextEvent != INT_MAX) {
1354			dma->nextEvent -= cycles;
1355			if (GBADMARegisterIsEnable(dma->reg)) {
1356				memory->activeDMA = i;
1357				memory->nextDMA = dma->nextEvent;
1358			}
1359		}
1360	}
1361	if (memory->nextDMA < cpu->nextEvent) {
1362		cpu->nextEvent = memory->nextDMA;
1363	}
1364}
1365
1366void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1367	struct GBAMemory* memory = &gba->memory;
1368	struct ARMCore* cpu = gba->cpu;
1369	uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1370	int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1371	int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1372	int32_t wordsRemaining = info->nextCount;
1373	uint32_t source = info->nextSource;
1374	uint32_t dest = info->nextDest;
1375	uint32_t sourceRegion = source >> BASE_OFFSET;
1376	uint32_t destRegion = dest >> BASE_OFFSET;
1377	int32_t cycles = 2;
1378
1379	if (source == info->source) {
1380		// TODO: support 4 cycles for ROM access
1381		cycles += 2;
1382		if (width == 4) {
1383			cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1384			source &= 0xFFFFFFFC;
1385			dest &= 0xFFFFFFFC;
1386		} else {
1387			cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1388		}
1389	} else {
1390		if (width == 4) {
1391			cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1392		} else {
1393			cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1394		}
1395	}
1396
1397	gba->performingDMA = true;
1398	int32_t word;
1399	if (width == 4) {
1400		word = cpu->memory.load32(cpu, source, 0);
1401		gba->bus = word;
1402		cpu->memory.store32(cpu, dest, word, 0);
1403		source += sourceOffset;
1404		dest += destOffset;
1405		--wordsRemaining;
1406	} else {
1407		if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1408			word = GBASavedataReadEEPROM(&memory->savedata);
1409			gba->bus = word | (word << 16);
1410			cpu->memory.store16(cpu, dest, word, 0);
1411			source += sourceOffset;
1412			dest += destOffset;
1413			--wordsRemaining;
1414		} else if (destRegion == REGION_CART2_EX) {
1415			if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1416				GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1417				GBASavedataInitEEPROM(&memory->savedata);
1418			}
1419			word = cpu->memory.load16(cpu, source, 0);
1420			gba->bus = word | (word << 16);
1421			GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1422			source += sourceOffset;
1423			dest += destOffset;
1424			--wordsRemaining;
1425		} else {
1426			word = cpu->memory.load16(cpu, source, 0);
1427			gba->bus = word | (word << 16);
1428			cpu->memory.store16(cpu, dest, word, 0);
1429			source += sourceOffset;
1430			dest += destOffset;
1431			--wordsRemaining;
1432		}
1433	}
1434	gba->performingDMA = false;
1435
1436	if (!wordsRemaining) {
1437		if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1438			info->reg = GBADMARegisterClearEnable(info->reg);
1439			info->nextEvent = INT_MAX;
1440
1441			// Clear the enable bit in memory
1442			memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1443		} else {
1444			info->nextCount = info->count;
1445			if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1446				info->nextDest = info->dest;
1447			}
1448			GBAMemoryScheduleDMA(gba, number, info);
1449		}
1450		if (GBADMARegisterIsDoIRQ(info->reg)) {
1451			GBARaiseIRQ(gba, IRQ_DMA0 + number);
1452		}
1453	} else {
1454		info->nextDest = dest;
1455		info->nextCount = wordsRemaining;
1456	}
1457	info->nextSource = source;
1458
1459	if (info->nextEvent != INT_MAX) {
1460		info->nextEvent += cycles;
1461	}
1462	cpu->cycles += cycles;
1463}
1464
1465void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1466	memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1467	memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1468}
1469
1470void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1471	memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1472	memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1473}
1474
1475uint32_t _popcount32(unsigned bits) {
1476	bits = bits - ((bits >> 1) & 0x55555555);
1477	bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1478	return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1479}