src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
33
34static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
35static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
36static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
37
38static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
39
40static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
41static void _GBPocketCamCapture(struct GBMemory*);
42
43void GBMBCSwitchBank(struct GB* gb, int bank) {
44 size_t bankStart = bank * GB_SIZE_CART_BANK0;
45 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
46 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
47 bankStart &= (gb->memory.romSize - 1);
48 bank = bankStart / GB_SIZE_CART_BANK0;
49 }
50 gb->memory.romBank = &gb->memory.rom[bankStart];
51 gb->memory.currentBank = bank;
52 if (gb->cpu->pc < GB_BASE_VRAM) {
53 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
54 }
55}
56
57void GBMBCSwitchBank0(struct GB* gb, int bank) {
58 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
59 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
60 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
61 bankStart &= (gb->memory.romSize - 1);
62 }
63 gb->memory.romBase = &gb->memory.rom[bankStart];
64 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
65 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
66 }
67}
68
69void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
70 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
71 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
72 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
73 bankStart &= (gb->memory.romSize - 1);
74 bank = bankStart / GB_SIZE_CART_HALFBANK;
75 if (!bank) {
76 ++bank;
77 }
78 }
79 if (!half) {
80 gb->memory.romBank = &gb->memory.rom[bankStart];
81 gb->memory.currentBank = bank;
82 } else {
83 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
84 gb->memory.mbcState.mbc6.currentBank1 = bank;
85 }
86 if (gb->cpu->pc < GB_BASE_VRAM) {
87 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
88 }
89}
90
91static bool _isMulticart(const uint8_t* mem) {
92 bool success = true;
93 struct VFile* vf;
94
95 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
96 success = success && GBIsROM(vf);
97 vf->close(vf);
98
99 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
100 success = success && GBIsROM(vf);
101 vf->close(vf);
102
103 return success;
104}
105
106void GBMBCSwitchSramBank(struct GB* gb, int bank) {
107 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
108 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
109 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
110 bankStart &= (gb->sramSize - 1);
111 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
112 }
113 gb->memory.sramBank = &gb->memory.sram[bankStart];
114 gb->memory.sramCurrentBank = bank;
115}
116
117void GBMBCInit(struct GB* gb) {
118 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
119 if (gb->memory.rom) {
120 switch (cart->ramSize) {
121 case 0:
122 gb->sramSize = 0;
123 break;
124 case 1:
125 gb->sramSize = 0x800;
126 break;
127 default:
128 case 2:
129 gb->sramSize = 0x2000;
130 break;
131 case 3:
132 gb->sramSize = 0x8000;
133 break;
134 case 4:
135 gb->sramSize = 0x20000;
136 break;
137 case 5:
138 gb->sramSize = 0x10000;
139 break;
140 }
141
142 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
143 switch (cart->type) {
144 case 0:
145 case 8:
146 case 9:
147 gb->memory.mbcType = GB_MBC_NONE;
148 break;
149 case 1:
150 case 2:
151 case 3:
152 gb->memory.mbcType = GB_MBC1;
153 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
154 gb->memory.mbcState.mbc1.multicartStride = 4;
155 } else {
156 gb->memory.mbcState.mbc1.multicartStride = 5;
157 }
158 break;
159 case 5:
160 case 6:
161 gb->memory.mbcType = GB_MBC2;
162 break;
163 case 0x0F:
164 case 0x10:
165 gb->memory.mbcType = GB_MBC3_RTC;
166 break;
167 case 0x11:
168 case 0x12:
169 case 0x13:
170 gb->memory.mbcType = GB_MBC3;
171 break;
172 default:
173 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
174 // Fall through
175 case 0x19:
176 case 0x1A:
177 case 0x1B:
178 gb->memory.mbcType = GB_MBC5;
179 break;
180 case 0x1C:
181 case 0x1D:
182 case 0x1E:
183 gb->memory.mbcType = GB_MBC5_RUMBLE;
184 break;
185 case 0x20:
186 gb->memory.mbcType = GB_MBC6;
187 break;
188 case 0x22:
189 gb->memory.mbcType = GB_MBC7;
190 break;
191 case 0xFC:
192 gb->memory.mbcType = GB_POCKETCAM;
193 break;
194 case 0xFD:
195 gb->memory.mbcType = GB_TAMA5;
196 break;
197 case 0xFE:
198 gb->memory.mbcType = GB_HuC3;
199 break;
200 case 0xFF:
201 gb->memory.mbcType = GB_HuC1;
202 break;
203 }
204 }
205 } else {
206 gb->memory.mbcType = GB_MBC_NONE;
207 }
208 gb->memory.mbcRead = NULL;
209 switch (gb->memory.mbcType) {
210 case GB_MBC_NONE:
211 gb->memory.mbcWrite = _GBMBCNone;
212 break;
213 case GB_MBC1:
214 gb->memory.mbcWrite = _GBMBC1;
215 break;
216 case GB_MBC2:
217 gb->memory.mbcWrite = _GBMBC2;
218 gb->memory.mbcRead = _GBMBC2Read;
219 gb->sramSize = 0x100;
220 break;
221 case GB_MBC3:
222 gb->memory.mbcWrite = _GBMBC3;
223 break;
224 default:
225 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
226 // Fall through
227 case GB_MBC5:
228 gb->memory.mbcWrite = _GBMBC5;
229 break;
230 case GB_MBC6:
231 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
232 gb->memory.mbcWrite = _GBMBC6;
233 break;
234 case GB_MBC7:
235 gb->memory.mbcWrite = _GBMBC7;
236 gb->memory.mbcRead = _GBMBC7Read;
237 gb->sramSize = 0x100;
238 break;
239 case GB_MMM01:
240 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
241 gb->memory.mbcWrite = _GBMBC1;
242 break;
243 case GB_HuC1:
244 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
245 gb->memory.mbcWrite = _GBMBC1;
246 break;
247 case GB_HuC3:
248 gb->memory.mbcWrite = _GBHuC3;
249 break;
250 case GB_TAMA5:
251 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
252 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
253 gb->memory.mbcWrite = _GBTAMA5;
254 gb->memory.mbcRead = _GBTAMA5Read;
255 gb->sramSize = 0x20;
256 break;
257 case GB_MBC3_RTC:
258 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
259 gb->memory.mbcWrite = _GBMBC3;
260 break;
261 case GB_MBC5_RUMBLE:
262 gb->memory.mbcWrite = _GBMBC5;
263 break;
264 case GB_POCKETCAM:
265 gb->memory.mbcWrite = _GBPocketCam;
266 gb->memory.mbcRead = _GBPocketCamRead;
267 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
268 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
269 }
270 break;
271 }
272
273 gb->memory.currentBank = 1;
274 gb->memory.sramCurrentBank = 0;
275 gb->memory.sramAccess = false;
276 gb->memory.rtcAccess = false;
277 gb->memory.activeRtcReg = 0;
278 gb->memory.rtcLatched = false;
279 gb->memory.rtcLastLatch = 0;
280 if (gb->memory.rtc) {
281 if (gb->memory.rtc->sample) {
282 gb->memory.rtc->sample(gb->memory.rtc);
283 }
284 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
285 } else {
286 gb->memory.rtcLastLatch = time(0);
287 }
288 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
289
290 GBResizeSram(gb, gb->sramSize);
291
292 if (gb->memory.mbcType == GB_MBC3_RTC) {
293 GBMBCRTCRead(gb);
294 }
295}
296
297static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
298 time_t t;
299 if (rtc) {
300 if (rtc->sample) {
301 rtc->sample(rtc);
302 }
303 t = rtc->unixTime(rtc);
304 } else {
305 t = time(0);
306 }
307 time_t currentLatch = t;
308 t -= *rtcLastLatch;
309 *rtcLastLatch = currentLatch;
310
311 int64_t diff;
312 diff = rtcRegs[0] + t % 60;
313 if (diff < 0) {
314 diff += 60;
315 t -= 60;
316 }
317 rtcRegs[0] = diff % 60;
318 t /= 60;
319 t += diff / 60;
320
321 diff = rtcRegs[1] + t % 60;
322 if (diff < 0) {
323 diff += 60;
324 t -= 60;
325 }
326 rtcRegs[1] = diff % 60;
327 t /= 60;
328 t += diff / 60;
329
330 diff = rtcRegs[2] + t % 24;
331 if (diff < 0) {
332 diff += 24;
333 t -= 24;
334 }
335 rtcRegs[2] = diff % 24;
336 t /= 24;
337 t += diff / 24;
338
339 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
340 rtcRegs[3] = diff;
341 rtcRegs[4] &= 0xFE;
342 rtcRegs[4] |= (diff >> 8) & 1;
343 if (diff & 0x200) {
344 rtcRegs[4] |= 0x80;
345 }
346}
347
348void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
349 struct GBMemory* memory = &gb->memory;
350 int bank = value & 0x1F;
351 int stride = 1 << memory->mbcState.mbc1.multicartStride;
352 switch (address >> 13) {
353 case 0x0:
354 switch (value) {
355 case 0:
356 memory->sramAccess = false;
357 break;
358 case 0xA:
359 memory->sramAccess = true;
360 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
361 break;
362 default:
363 // TODO
364 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
365 break;
366 }
367 break;
368 case 0x1:
369 if (!bank) {
370 ++bank;
371 }
372 bank &= stride - 1;
373 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
374 break;
375 case 0x2:
376 bank &= 3;
377 if (memory->mbcState.mbc1.mode) {
378 GBMBCSwitchBank0(gb, bank);
379 GBMBCSwitchSramBank(gb, bank);
380 }
381 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
382 break;
383 case 0x3:
384 memory->mbcState.mbc1.mode = value & 1;
385 if (memory->mbcState.mbc1.mode) {
386 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
387 } else {
388 GBMBCSwitchBank0(gb, 0);
389 GBMBCSwitchSramBank(gb, 0);
390 }
391 break;
392 default:
393 // TODO
394 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
395 break;
396 }
397}
398
399void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
400 struct GBMemory* memory = &gb->memory;
401 int shift = (address & 1) * 4;
402 int bank = value & 0xF;
403 switch (address >> 13) {
404 case 0x0:
405 switch (value) {
406 case 0:
407 memory->sramAccess = false;
408 break;
409 case 0xA:
410 memory->sramAccess = true;
411 break;
412 default:
413 // TODO
414 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
415 break;
416 }
417 break;
418 case 0x1:
419 if (!bank) {
420 ++bank;
421 }
422 GBMBCSwitchBank(gb, bank);
423 break;
424 case 0x5:
425 if (!memory->sramAccess) {
426 return;
427 }
428 address &= 0x1FF;
429 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
430 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
431 default:
432 // TODO
433 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
434 break;
435 }
436}
437
438static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
439 address &= 0x1FF;
440 int shift = (address & 1) * 4;
441 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
442}
443
444void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
445 struct GBMemory* memory = &gb->memory;
446 int bank = value & 0x7F;
447 switch (address >> 13) {
448 case 0x0:
449 switch (value) {
450 case 0:
451 memory->sramAccess = false;
452 break;
453 case 0xA:
454 memory->sramAccess = true;
455 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
456 break;
457 default:
458 // TODO
459 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
460 break;
461 }
462 break;
463 case 0x1:
464 if (!bank) {
465 ++bank;
466 }
467 GBMBCSwitchBank(gb, bank);
468 break;
469 case 0x2:
470 if (value < 4) {
471 GBMBCSwitchSramBank(gb, value);
472 memory->rtcAccess = false;
473 } else if (value >= 8 && value <= 0xC) {
474 memory->activeRtcReg = value - 8;
475 memory->rtcAccess = true;
476 }
477 break;
478 case 0x3:
479 if (memory->rtcLatched && value == 0) {
480 memory->rtcLatched = false;
481 } else if (!memory->rtcLatched && value == 1) {
482 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
483 memory->rtcLatched = true;
484 }
485 break;
486 }
487}
488
489void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
490 struct GBMemory* memory = &gb->memory;
491 int bank;
492 switch (address >> 12) {
493 case 0x0:
494 case 0x1:
495 switch (value) {
496 case 0:
497 memory->sramAccess = false;
498 break;
499 case 0xA:
500 memory->sramAccess = true;
501 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
502 break;
503 default:
504 // TODO
505 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
506 break;
507 }
508 break;
509 case 0x2:
510 bank = (memory->currentBank & 0x100) | value;
511 GBMBCSwitchBank(gb, bank);
512 break;
513 case 0x3:
514 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
515 GBMBCSwitchBank(gb, bank);
516 break;
517 case 0x4:
518 case 0x5:
519 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
520 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
521 value &= ~8;
522 }
523 GBMBCSwitchSramBank(gb, value & 0xF);
524 break;
525 default:
526 // TODO
527 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
528 break;
529 }
530}
531
532void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
533 struct GBMemory* memory = &gb->memory;
534 int bank = value & 0x7F;
535 switch (address >> 10) {
536 case 0:
537 switch (value) {
538 case 0:
539 memory->sramAccess = false;
540 break;
541 case 0xA:
542 memory->sramAccess = true;
543 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
544 break;
545 default:
546 // TODO
547 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
548 break;
549 }
550 break;
551 case 0x9:
552 GBMBCSwitchHalfBank(gb, 0, bank);
553 break;
554 case 0xD:
555 GBMBCSwitchHalfBank(gb, 1, bank);
556 break;
557 default:
558 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
559 break;
560 }
561}
562
563void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
564 int bank = value & 0x7F;
565 switch (address >> 13) {
566 case 0x0:
567 switch (value) {
568 default:
569 case 0:
570 gb->memory.mbcState.mbc7.access = 0;
571 break;
572 case 0xA:
573 gb->memory.mbcState.mbc7.access |= 1;
574 break;
575 }
576 break;
577 case 0x1:
578 GBMBCSwitchBank(gb, bank);
579 break;
580 case 0x2:
581 if (value == 0x40) {
582 gb->memory.mbcState.mbc7.access |= 2;
583 } else {
584 gb->memory.mbcState.mbc7.access &= ~2;
585 }
586 break;
587 case 0x5:
588 _GBMBC7Write(&gb->memory, address, value);
589 default:
590 // TODO
591 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
592 break;
593 }
594}
595
596uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
597 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
598 if (mbc7->access != 3) {
599 return 0xFF;
600 }
601 switch (address & 0xF0) {
602 case 0x20:
603 if (memory->rotation && memory->rotation->readTiltX) {
604 int32_t x = -memory->rotation->readTiltX(memory->rotation);
605 x >>= 21;
606 x += 0x81D0;
607 return x;
608 }
609 return 0xFF;
610 case 0x30:
611 if (memory->rotation && memory->rotation->readTiltX) {
612 int32_t x = -memory->rotation->readTiltX(memory->rotation);
613 x >>= 21;
614 x += 0x81D0;
615 return x >> 8;
616 }
617 return 7;
618 case 0x40:
619 if (memory->rotation && memory->rotation->readTiltY) {
620 int32_t y = -memory->rotation->readTiltY(memory->rotation);
621 y >>= 21;
622 y += 0x81D0;
623 return y;
624 }
625 return 0xFF;
626 case 0x50:
627 if (memory->rotation && memory->rotation->readTiltY) {
628 int32_t y = -memory->rotation->readTiltY(memory->rotation);
629 y >>= 21;
630 y += 0x81D0;
631 return y >> 8;
632 }
633 return 7;
634 case 0x60:
635 return 0;
636 case 0x80:
637 return mbc7->eeprom;
638 default:
639 return 0xFF;
640 }
641}
642
643static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
644 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
645 if (mbc7->access != 3) {
646 return;
647 }
648 switch (address & 0xF0) {
649 case 0x00:
650 mbc7->latch = (value & 0x55) == 0x55;
651 return;
652 case 0x10:
653 mbc7->latch |= (value & 0xAA);
654 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
655 memory->rotation->sample(memory->rotation);
656 }
657 mbc7->latch = 0;
658 return;
659 default:
660 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
661 return;
662 case 0x80:
663 break;
664 }
665 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
666 value = GBMBC7FieldFillDO(value); // Hi-Z
667 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
668 mbc7->state = GBMBC7_STATE_IDLE;
669 }
670 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
671 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
672 mbc7->sr <<= 1;
673 mbc7->sr |= GBMBC7FieldGetDI(value);
674 ++mbc7->srBits;
675 }
676 switch (mbc7->state) {
677 case GBMBC7_STATE_IDLE:
678 if (GBMBC7FieldIsDI(value)) {
679 mbc7->state = GBMBC7_STATE_READ_COMMAND;
680 mbc7->srBits = 0;
681 mbc7->sr = 0;
682 }
683 break;
684 case GBMBC7_STATE_READ_COMMAND:
685 if (mbc7->srBits == 10) {
686 mbc7->state = 0x10 | (mbc7->sr >> 6);
687 if (mbc7->state & 0xC) {
688 mbc7->state &= ~0x3;
689 }
690 mbc7->srBits = 0;
691 mbc7->address = mbc7->sr & 0x7F;
692 }
693 break;
694 case GBMBC7_STATE_DO:
695 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
696 mbc7->sr <<= 1;
697 --mbc7->srBits;
698 if (!mbc7->srBits) {
699 mbc7->state = GBMBC7_STATE_IDLE;
700 }
701 break;
702 default:
703 break;
704 }
705 switch (mbc7->state) {
706 case GBMBC7_STATE_EEPROM_EWEN:
707 mbc7->writable = true;
708 mbc7->state = GBMBC7_STATE_IDLE;
709 break;
710 case GBMBC7_STATE_EEPROM_EWDS:
711 mbc7->writable = false;
712 mbc7->state = GBMBC7_STATE_IDLE;
713 break;
714 case GBMBC7_STATE_EEPROM_WRITE:
715 if (mbc7->srBits == 16) {
716 if (mbc7->writable) {
717 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
718 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
719 }
720 mbc7->state = GBMBC7_STATE_IDLE;
721 }
722 break;
723 case GBMBC7_STATE_EEPROM_ERASE:
724 if (mbc7->writable) {
725 memory->sram[mbc7->address * 2] = 0xFF;
726 memory->sram[mbc7->address * 2 + 1] = 0xFF;
727 }
728 mbc7->state = GBMBC7_STATE_IDLE;
729 break;
730 case GBMBC7_STATE_EEPROM_READ:
731 mbc7->srBits = 16;
732 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
733 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
734 mbc7->state = GBMBC7_STATE_DO;
735 value = GBMBC7FieldClearDO(value);
736 break;
737 case GBMBC7_STATE_EEPROM_WRAL:
738 if (mbc7->srBits == 16) {
739 if (mbc7->writable) {
740 int i;
741 for (i = 0; i < 128; ++i) {
742 memory->sram[i * 2] = mbc7->sr >> 8;
743 memory->sram[i * 2 + 1] = mbc7->sr;
744 }
745 }
746 mbc7->state = GBMBC7_STATE_IDLE;
747 }
748 break;
749 case GBMBC7_STATE_EEPROM_ERAL:
750 if (mbc7->writable) {
751 int i;
752 for (i = 0; i < 128; ++i) {
753 memory->sram[i * 2] = 0xFF;
754 memory->sram[i * 2 + 1] = 0xFF;
755 }
756 }
757 mbc7->state = GBMBC7_STATE_IDLE;
758 break;
759 default:
760 break;
761 }
762 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
763 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
764 }
765 mbc7->eeprom = value;
766}
767
768void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
769 struct GBMemory* memory = &gb->memory;
770 int bank = value & 0x3F;
771 if (address & 0x1FFF) {
772 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
773 }
774
775 switch (address >> 13) {
776 case 0x0:
777 switch (value) {
778 case 0xA:
779 memory->sramAccess = true;
780 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
781 break;
782 default:
783 memory->sramAccess = false;
784 break;
785 }
786 break;
787 case 0x1:
788 GBMBCSwitchBank(gb, bank);
789 break;
790 case 0x2:
791 GBMBCSwitchSramBank(gb, bank);
792 break;
793 default:
794 // TODO
795 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
796 break;
797 }
798}
799
800void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
801 struct GBMemory* memory = &gb->memory;
802 int bank = value & 0x3F;
803 switch (address >> 13) {
804 case 0x0:
805 switch (value) {
806 case 0:
807 memory->sramAccess = false;
808 break;
809 case 0xA:
810 memory->sramAccess = true;
811 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
812 break;
813 default:
814 // TODO
815 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
816 break;
817 }
818 break;
819 case 0x1:
820 GBMBCSwitchBank(gb, bank);
821 break;
822 case 0x2:
823 if (value < 0x10) {
824 GBMBCSwitchSramBank(gb, value);
825 memory->mbcState.pocketCam.registersActive = false;
826 } else {
827 memory->mbcState.pocketCam.registersActive = true;
828 }
829 break;
830 case 0x5:
831 address &= 0x7F;
832 if (address == 0 && value & 1) {
833 value &= 6; // TODO: Timing
834 _GBPocketCamCapture(memory);
835 }
836 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
837 memory->mbcState.pocketCam.registers[address] = value;
838 }
839 break;
840 default:
841 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
842 break;
843 }
844}
845
846uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
847 if (memory->mbcState.pocketCam.registersActive) {
848 if ((address & 0x7F) == 0) {
849 return memory->mbcState.pocketCam.registers[0];
850 }
851 return 0;
852 }
853 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
854}
855
856void _GBPocketCamCapture(struct GBMemory* memory) {
857 if (!memory->cam) {
858 return;
859 }
860 const void* image = NULL;
861 size_t stride;
862 enum mColorFormat format;
863 memory->cam->requestImage(memory->cam, &image, &stride, &format);
864 if (!image) {
865 return;
866 }
867 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
868 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
869 size_t x, y;
870 for (y = 0; y < GBCAM_HEIGHT; ++y) {
871 for (x = 0; x < GBCAM_WIDTH; ++x) {
872 uint32_t gray;
873 uint32_t color;
874 switch (format) {
875 case mCOLOR_XBGR8:
876 case mCOLOR_XRGB8:
877 case mCOLOR_ARGB8:
878 case mCOLOR_ABGR8:
879 color = ((const uint32_t*) image)[y * stride + x];
880 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
881 break;
882 case mCOLOR_BGRX8:
883 case mCOLOR_RGBX8:
884 case mCOLOR_RGBA8:
885 case mCOLOR_BGRA8:
886 color = ((const uint32_t*) image)[y * stride + x];
887 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
888 break;
889 case mCOLOR_BGR5:
890 case mCOLOR_RGB5:
891 case mCOLOR_ARGB5:
892 case mCOLOR_ABGR5:
893 color = ((const uint16_t*) image)[y * stride + x];
894 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
895 break;
896 case mCOLOR_BGR565:
897 case mCOLOR_RGB565:
898 color = ((const uint16_t*) image)[y * stride + x];
899 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
900 break;
901 case mCOLOR_BGRA5:
902 case mCOLOR_RGBA5:
903 color = ((const uint16_t*) image)[y * stride + x];
904 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
905 break;
906 default:
907 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
908 return;
909 }
910 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
911 gray = (gray + 1) * exposure / 0x300;
912 // TODO: Additional processing
913 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
914 if (gray < pocketCam->registers[matrixEntry + 6]) {
915 gray = 0x101;
916 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
917 gray = 0x100;
918 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
919 gray = 0x001;
920 } else {
921 gray = 0;
922 }
923 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
924 uint16_t existing;
925 LOAD_16LE(existing, coord + 0x100, memory->sram);
926 existing |= gray << (7 - (x & 7));
927 STORE_16LE(existing, coord + 0x100, memory->sram);
928 }
929 }
930}
931
932void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
933 struct GBMemory* memory = &gb->memory;
934 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
935 switch (address >> 13) {
936 case 0x5:
937 if (address & 1) {
938 tama5->reg = value;
939 } else {
940 value &= 0xF;
941 if (tama5->reg < GBTAMA5_MAX) {
942 tama5->registers[tama5->reg] = value;
943 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
944 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
945 switch (tama5->reg) {
946 case GBTAMA5_BANK_LO:
947 case GBTAMA5_BANK_HI:
948 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
949 break;
950 case GBTAMA5_WRITE_LO:
951 case GBTAMA5_WRITE_HI:
952 case GBTAMA5_CS:
953 break;
954 case GBTAMA5_ADDR_LO:
955 switch (tama5->registers[GBTAMA5_CS] >> 1) {
956 case 0x0: // RAM write
957 memory->sram[address] = out;
958 break;
959 case 0x1: // RAM read
960 break;
961 default:
962 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
963 }
964 break;
965 default:
966 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
967 break;
968 }
969 } else {
970 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
971 }
972 }
973 break;
974 default:
975 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
976 }
977}
978
979uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
980 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
981 if ((address & 0x1FFF) > 1) {
982 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
983 }
984 if (address & 1) {
985 return 0xFF;
986 } else {
987 uint8_t value = 0xF0;
988 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
989 switch (tama5->reg) {
990 case GBTAMA5_ACTIVE:
991 return 0xF1;
992 case GBTAMA5_READ_LO:
993 case GBTAMA5_READ_HI:
994 switch (tama5->registers[GBTAMA5_CS] >> 1) {
995 case 1:
996 value = memory->sram[address];
997 break;
998 default:
999 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1000 break;
1001 }
1002 if (tama5->reg == GBTAMA5_READ_HI) {
1003 value >>= 4;
1004 }
1005 value |= 0xF0;
1006 return value;
1007 default:
1008 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1009 return 0xF1;
1010 }
1011 }
1012}
1013
1014void GBMBCRTCRead(struct GB* gb) {
1015 struct GBMBCRTCSaveBuffer rtcBuffer;
1016 struct VFile* vf = gb->sramVf;
1017 if (!vf) {
1018 return;
1019 }
1020 vf->seek(vf, gb->sramSize, SEEK_SET);
1021 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1022 return;
1023 }
1024
1025 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1026 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1027 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1028 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1029 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1030 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1031}
1032
1033void GBMBCRTCWrite(struct GB* gb) {
1034 struct VFile* vf = gb->sramVf;
1035 if (!vf) {
1036 return;
1037 }
1038
1039 uint8_t rtcRegs[5];
1040 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1041 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1042 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1043
1044 struct GBMBCRTCSaveBuffer rtcBuffer;
1045 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1046 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1047 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1048 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1049 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1050 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1051 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1052 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1053 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1054 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1055 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1056
1057 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1058 // Writing past the end of the file can invalidate the file mapping
1059 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1060 gb->memory.sram = NULL;
1061 }
1062 vf->seek(vf, gb->sramSize, SEEK_SET);
1063 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1064 if (!gb->memory.sram) {
1065 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1066 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1067 }
1068}