src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int shift = cpu->gprs[rs];
23 if (rs == ARM_PC) {
24 shift += 4;
25 }
26 shift &= 0xFF;
27 int32_t shiftVal = cpu->gprs[rm];
28 if (rm == ARM_PC) {
29 shiftVal += 4;
30 }
31 if (!shift) {
32 cpu->shifterOperand = shiftVal;
33 cpu->shifterCarryOut = cpu->cpsr.c;
34 } else if (shift < 32) {
35 cpu->shifterOperand = shiftVal << shift;
36 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
37 } else if (shift == 32) {
38 cpu->shifterOperand = 0;
39 cpu->shifterCarryOut = shiftVal & 1;
40 } else {
41 cpu->shifterOperand = 0;
42 cpu->shifterCarryOut = 0;
43 }
44 } else {
45 int immediate = (opcode & 0x00000F80) >> 7;
46 if (!immediate) {
47 cpu->shifterOperand = cpu->gprs[rm];
48 cpu->shifterCarryOut = cpu->cpsr.c;
49 } else {
50 cpu->shifterOperand = cpu->gprs[rm] << immediate;
51 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
52 }
53 }
54}
55
56static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
57 int rm = opcode & 0x0000000F;
58 if (opcode & 0x00000010) {
59 int rs = (opcode >> 8) & 0x0000000F;
60 ++cpu->cycles;
61 int shift = cpu->gprs[rs];
62 if (rs == ARM_PC) {
63 shift += 4;
64 }
65 shift &= 0xFF;
66 uint32_t shiftVal = cpu->gprs[rm];
67 if (rm == ARM_PC) {
68 shiftVal += 4;
69 }
70 if (!shift) {
71 cpu->shifterOperand = shiftVal;
72 cpu->shifterCarryOut = cpu->cpsr.c;
73 } else if (shift < 32) {
74 cpu->shifterOperand = shiftVal >> shift;
75 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
76 } else if (shift == 32) {
77 cpu->shifterOperand = 0;
78 cpu->shifterCarryOut = shiftVal >> 31;
79 } else {
80 cpu->shifterOperand = 0;
81 cpu->shifterCarryOut = 0;
82 }
83 } else {
84 int immediate = (opcode & 0x00000F80) >> 7;
85 if (immediate) {
86 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
87 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
91 }
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 if (opcode & 0x00000010) {
98 int rs = (opcode >> 8) & 0x0000000F;
99 ++cpu->cycles;
100 int shift = cpu->gprs[rs];
101 if (rs == ARM_PC) {
102 shift += 4;
103 }
104 shift &= 0xFF;
105 int shiftVal = cpu->gprs[rm];
106 if (rm == ARM_PC) {
107 shiftVal += 4;
108 }
109 if (!shift) {
110 cpu->shifterOperand = shiftVal;
111 cpu->shifterCarryOut = cpu->cpsr.c;
112 } else if (shift < 32) {
113 cpu->shifterOperand = shiftVal >> shift;
114 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
115 } else if (cpu->gprs[rm] >> 31) {
116 cpu->shifterOperand = 0xFFFFFFFF;
117 cpu->shifterCarryOut = 1;
118 } else {
119 cpu->shifterOperand = 0;
120 cpu->shifterCarryOut = 0;
121 }
122 } else {
123 int immediate = (opcode & 0x00000F80) >> 7;
124 if (immediate) {
125 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
126 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
127 } else {
128 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
129 cpu->shifterOperand = cpu->shifterCarryOut;
130 }
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 if (opcode & 0x00000010) {
137 int rs = (opcode >> 8) & 0x0000000F;
138 ++cpu->cycles;
139 int shift = cpu->gprs[rs];
140 if (rs == ARM_PC) {
141 shift += 4;
142 }
143 shift &= 0xFF;
144 int shiftVal = cpu->gprs[rm];
145 if (rm == ARM_PC) {
146 shiftVal += 4;
147 }
148 int rotate = shift & 0x1F;
149 if (!shift) {
150 cpu->shifterOperand = shiftVal;
151 cpu->shifterCarryOut = cpu->cpsr.c;
152 } else if (rotate) {
153 cpu->shifterOperand = ROR(shiftVal, rotate);
154 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
155 } else {
156 cpu->shifterOperand = shiftVal;
157 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
158 }
159 } else {
160 int immediate = (opcode & 0x00000F80) >> 7;
161 if (immediate) {
162 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
163 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
164 } else {
165 // RRX
166 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
167 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
168 }
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
188 cpu->cpsr.flags = 0;
189 cpu->cpsr.n = ARM_SIGN(d);
190 cpu->cpsr.z = !d;
191 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
192 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
193}
194
195ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
196 cpu->cpsr.flags = 0;
197 cpu->cpsr.n = ARM_SIGN(d);
198 cpu->cpsr.z = !d;
199 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
200 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
201}
202
203ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
204 cpu->cpsr.n = ARM_SIGN(d);
205 cpu->cpsr.z = !d; \
206 cpu->cpsr.c = cpu->shifterCarryOut; \
207}
208
209#define ARM_ADDITION_S(M, N, D) \
210 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
211 cpu->cpsr = cpu->spsr; \
212 _ARMReadCPSR(cpu); \
213 } else { \
214 _additionS(cpu, M, N, D); \
215 }
216
217#define ARM_SUBTRACTION_S(M, N, D) \
218 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
219 cpu->cpsr = cpu->spsr; \
220 _ARMReadCPSR(cpu); \
221 } else { \
222 _subtractionS(cpu, M, N, D); \
223 }
224
225#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
226 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
227 cpu->cpsr = cpu->spsr; \
228 _ARMReadCPSR(cpu); \
229 } else { \
230 cpu->cpsr.n = ARM_SIGN(D); \
231 cpu->cpsr.z = !(D); \
232 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
233 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
234 }
235
236#define ARM_NEUTRAL_S(M, N, D) \
237 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
238 cpu->cpsr = cpu->spsr; \
239 _ARMReadCPSR(cpu); \
240 } else { \
241 _neutralS(cpu, D); \
242 }
243
244#define ARM_NEUTRAL_HI_S(DLO, DHI) \
245 cpu->cpsr.n = ARM_SIGN(DHI); \
246 cpu->cpsr.z = !((DHI) | (DLO));
247
248#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
249#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
250#define ADDR_MODE_2_ADDRESS (address)
251#define ADDR_MODE_2_RN (cpu->gprs[rn])
252#define ADDR_MODE_2_RM (cpu->gprs[rm])
253#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
254#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
255#define ADDR_MODE_2_WRITEBACK(ADDR) \
256 cpu->gprs[rn] = ADDR; \
257 if (UNLIKELY(rn == ARM_PC)) { \
258 currentCycles += ARMWritePC(cpu); \
259 }
260
261#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
262#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
263#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
264#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
265
266#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
267#define ADDR_MODE_3_RN ADDR_MODE_2_RN
268#define ADDR_MODE_3_RM ADDR_MODE_2_RM
269#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
270#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
271#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
272
273#define ADDR_MODE_4_WRITEBACK_LDM \
274 if (!((1 << rn) & rs)) { \
275 cpu->gprs[rn] = address; \
276 }
277
278#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
279
280#define ARM_LOAD_POST_BODY \
281 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
282 if (rd == ARM_PC) { \
283 currentCycles += ARMWritePC(cpu); \
284 }
285
286#define ARM_STORE_POST_BODY \
287 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
288
289#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
290 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
291 int currentCycles = ARM_PREFETCH_CYCLES; \
292 BODY; \
293 cpu->cycles += currentCycles; \
294 }
295
296#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
297 DEFINE_INSTRUCTION_ARM(NAME, \
298 int rd = (opcode >> 12) & 0xF; \
299 int rn = (opcode >> 16) & 0xF; \
300 UNUSED(rn); \
301 SHIFTER(cpu, opcode); \
302 BODY; \
303 S_BODY; \
304 if (rd == ARM_PC) { \
305 if (cpu->executionMode == MODE_ARM) { \
306 currentCycles += ARMWritePC(cpu); \
307 } else { \
308 currentCycles += ThumbWritePC(cpu); \
309 } \
310 })
311
312#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
322 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
323
324#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
328 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
329 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
330
331#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
332 DEFINE_INSTRUCTION_ARM(NAME, \
333 int rd = (opcode >> 16) & 0xF; \
334 int rs = (opcode >> 8) & 0xF; \
335 int rm = opcode & 0xF; \
336 if (rd == ARM_PC) { \
337 return; \
338 } \
339 ARM_WAIT_MUL(cpu->gprs[rs]); \
340 BODY; \
341 S_BODY; \
342 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
343
344#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
345 DEFINE_INSTRUCTION_ARM(NAME, \
346 int rd = (opcode >> 12) & 0xF; \
347 int rdHi = (opcode >> 16) & 0xF; \
348 int rs = (opcode >> 8) & 0xF; \
349 int rm = opcode & 0xF; \
350 if (rdHi == ARM_PC || rd == ARM_PC) { \
351 return; \
352 } \
353 currentCycles += cpu->memory.stall(cpu, WAIT); \
354 BODY; \
355 S_BODY; \
356 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
357
358#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
359 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
360 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
361
362#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
363 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
364 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
365
366#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
367 DEFINE_INSTRUCTION_ARM(NAME, \
368 uint32_t address; \
369 int rn = (opcode >> 16) & 0xF; \
370 int rd = (opcode >> 12) & 0xF; \
371 int rm = opcode & 0xF; \
372 UNUSED(rm); \
373 address = ADDRESS; \
374 WRITEBACK; \
375 BODY;)
376
377#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
383 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
384
385#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
386 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
387 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
396
397#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
408 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
409 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
410
411#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
412 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
413 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
414
415#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
416 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
417 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
418 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
419 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
420 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
421 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
422
423#define ARM_MS_PRE \
424 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
425 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
426
427#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
428
429#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
430 DEFINE_INSTRUCTION_ARM(NAME, \
431 int rn = (opcode >> 16) & 0xF; \
432 int rs = opcode & 0x0000FFFF; \
433 uint32_t address = cpu->gprs[rn]; \
434 S_PRE; \
435 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
436 S_POST; \
437 POST_BODY; \
438 WRITEBACK;)
439
440
441#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
442 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
443 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
444 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
445 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
446 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
447 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
448 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
449 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
450 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
451 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
452 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
453 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
458
459// Begin ALU definitions
460
461DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
462 int32_t n = cpu->gprs[rn];
463 cpu->gprs[rd] = n + cpu->shifterOperand;)
464
465DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
466 int32_t n = cpu->gprs[rn];
467 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
468
469DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
470 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
471
472DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
473 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
474
475DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
476 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
477
478DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
479 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
480
481DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
482 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
483
484DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
485 cpu->gprs[rd] = cpu->shifterOperand;)
486
487DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
488 cpu->gprs[rd] = ~cpu->shifterOperand;)
489
490DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
491 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
492
493DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
494 int32_t n = cpu->gprs[rn];
495 cpu->gprs[rd] = cpu->shifterOperand - n;)
496
497DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
498 int32_t n = cpu->gprs[rn];
499 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
500
501DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
502 int32_t n = cpu->gprs[rn];
503 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
504
505DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
506 int32_t n = cpu->gprs[rn];
507 cpu->gprs[rd] = n - cpu->shifterOperand;)
508
509DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
510 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
511
512DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
513 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
514
515// End ALU definitions
516
517// Begin multiply definitions
518
519DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
520DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
521
522DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
523 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
524 int32_t dm = cpu->gprs[rd];
525 int32_t dn = d;
526 cpu->gprs[rd] = dm + dn;
527 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
528 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
529
530DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
531 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
532 cpu->gprs[rd] = d;
533 cpu->gprs[rdHi] = d >> 32;,
534 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
535
536DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
537 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
538 int32_t dm = cpu->gprs[rd];
539 int32_t dn = d;
540 cpu->gprs[rd] = dm + dn;
541 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
542 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
543
544DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
545 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
546 cpu->gprs[rd] = d;
547 cpu->gprs[rdHi] = d >> 32;,
548 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
549
550// End multiply definitions
551
552// Begin load/store definitions
553
554DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
555DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
556DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
557DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
558DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
559DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
560DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
561DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
562
563DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
564 enum PrivilegeMode priv = cpu->privilegeMode;
565 ARMSetPrivilegeMode(cpu, MODE_USER);
566 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
567 ARMSetPrivilegeMode(cpu, priv);
568 cpu->gprs[rd] = r;
569 ARM_LOAD_POST_BODY;)
570
571DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
572 enum PrivilegeMode priv = cpu->privilegeMode;
573 ARMSetPrivilegeMode(cpu, MODE_USER);
574 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
575 ARMSetPrivilegeMode(cpu, priv);
576 cpu->gprs[rd] = r;
577 ARM_LOAD_POST_BODY;)
578
579DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
580 enum PrivilegeMode priv = cpu->privilegeMode;
581 int32_t r = cpu->gprs[rd];
582 ARMSetPrivilegeMode(cpu, MODE_USER);
583 cpu->memory.store8(cpu, address, r, ¤tCycles);
584 ARMSetPrivilegeMode(cpu, priv);
585 ARM_STORE_POST_BODY;)
586
587DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
588 enum PrivilegeMode priv = cpu->privilegeMode;
589 int32_t r = cpu->gprs[rd];
590 ARMSetPrivilegeMode(cpu, MODE_USER);
591 cpu->memory.store32(cpu, address, r, ¤tCycles);
592 ARMSetPrivilegeMode(cpu, priv);
593 ARM_STORE_POST_BODY;)
594
595DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
596 load,
597 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
598 if (rs & 0x8000) {
599 currentCycles += ARMWritePC(cpu);
600 })
601
602DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
603 store,
604 ARM_STORE_POST_BODY;)
605
606DEFINE_INSTRUCTION_ARM(SWP,
607 int rm = opcode & 0xF;
608 int rd = (opcode >> 12) & 0xF;
609 int rn = (opcode >> 16) & 0xF;
610 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
611 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
612 cpu->gprs[rd] = d;)
613
614DEFINE_INSTRUCTION_ARM(SWPB,
615 int rm = opcode & 0xF;
616 int rd = (opcode >> 12) & 0xF;
617 int rn = (opcode >> 16) & 0xF;
618 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
619 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
620 cpu->gprs[rd] = d;)
621
622// End load/store definitions
623
624// Begin branch definitions
625
626DEFINE_INSTRUCTION_ARM(B,
627 int32_t offset = opcode << 8;
628 offset >>= 6;
629 cpu->gprs[ARM_PC] += offset;
630 currentCycles += ARMWritePC(cpu);)
631
632DEFINE_INSTRUCTION_ARM(BL,
633 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
634 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
635 cpu->gprs[ARM_PC] += immediate >> 6;
636 currentCycles += ARMWritePC(cpu);)
637
638DEFINE_INSTRUCTION_ARM(BX,
639 int rm = opcode & 0x0000000F;
640 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
641 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
642 if (cpu->executionMode == MODE_THUMB) {
643 currentCycles += ThumbWritePC(cpu);
644 } else {
645 currentCycles += ARMWritePC(cpu);
646 })
647
648// End branch definitions
649
650// Begin coprocessor definitions
651
652DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
653DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
654DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
655DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
656DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
657
658// Begin miscellaneous definitions
659
660DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
661DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
662
663DEFINE_INSTRUCTION_ARM(MSR,
664 int c = opcode & 0x00010000;
665 int f = opcode & 0x00080000;
666 int32_t operand = cpu->gprs[opcode & 0x0000000F];
667 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
668 if (mask & PSR_USER_MASK) {
669 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
670 }
671 if (mask & PSR_STATE_MASK) {
672 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
673 }
674 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
675 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
676 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
677 }
678 _ARMReadCPSR(cpu);
679 if (cpu->executionMode == MODE_THUMB) {
680 cpu->prefetch[0] = 0x46C0; // nop
681 cpu->prefetch[1] &= 0xFFFF;
682 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
683 } else {
684 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
685 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
686 })
687
688DEFINE_INSTRUCTION_ARM(MSRR,
689 int c = opcode & 0x00010000;
690 int f = opcode & 0x00080000;
691 int32_t operand = cpu->gprs[opcode & 0x0000000F];
692 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
693 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
694 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
695
696DEFINE_INSTRUCTION_ARM(MRS, \
697 int rd = (opcode >> 12) & 0xF; \
698 cpu->gprs[rd] = cpu->cpsr.packed;)
699
700DEFINE_INSTRUCTION_ARM(MRSR, \
701 int rd = (opcode >> 12) & 0xF; \
702 cpu->gprs[rd] = cpu->spsr.packed;)
703
704DEFINE_INSTRUCTION_ARM(MSRI,
705 int c = opcode & 0x00010000;
706 int f = opcode & 0x00080000;
707 int rotate = (opcode & 0x00000F00) >> 7;
708 int32_t operand = ROR(opcode & 0x000000FF, rotate);
709 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
710 if (mask & PSR_USER_MASK) {
711 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
712 }
713 if (mask & PSR_STATE_MASK) {
714 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
715 }
716 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
717 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
718 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
719 }
720 _ARMReadCPSR(cpu);
721 if (cpu->executionMode == MODE_THUMB) {
722 cpu->prefetch[0] = 0x46C0; // nop
723 cpu->prefetch[1] &= 0xFFFF;
724 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
725 } else {
726 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
727 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
728 })
729
730DEFINE_INSTRUCTION_ARM(MSRRI,
731 int c = opcode & 0x00010000;
732 int f = opcode & 0x00080000;
733 int rotate = (opcode & 0x00000F00) >> 7;
734 int32_t operand = ROR(opcode & 0x000000FF, rotate);
735 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
736 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
737 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
738
739DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
740
741const ARMInstruction _armTable[0x1000] = {
742 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
743};