1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef DS_MEMORY_H
  7#define DS_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/internal/arm/arm.h>
 14#include <mgba/core/log.h>
 15#include <mgba/internal/ds/io.h>
 16
 17enum DSMemoryRegion {
 18	DS7_REGION_BIOS = 0x0,
 19	DS9_REGION_ITCM = 0x0,
 20	DS9_REGION_ITCM_MIRROR = 0x1,
 21	DS_REGION_RAM = 0x2,
 22	DS_REGION_WORKING_RAM = 0x3,
 23	DS_REGION_IO = 0x4,
 24	DS9_REGION_PALETTE_RAM = 0x5,
 25	DS_REGION_VRAM = 0x6,
 26	DS9_REGION_OAM = 0x7,
 27	DS_REGION_SLOT2 = 0x8,
 28	DS_REGION_SLOT2_EX = 0x9,
 29	DS_REGION_SLOT2_SRAM = 0xA,
 30	DS9_REGION_BIOS = 0xFF,
 31};
 32
 33enum DSMemoryBase {
 34	DS7_BASE_BIOS = 0x00000000,
 35	DS9_BASE_ITCM = 0x00000000,
 36	DS_BASE_RAM = 0x02000000,
 37	DS9_BASE_DTCM = 0x027C0000,
 38	DS_BASE_WORKING_RAM = 0x03000000,
 39	DS7_BASE_WORKING_RAM = 0x03800000,
 40	DS_BASE_IO = 0x04000000,
 41	DS9_BASE_PALETTE_RAM = 0x05000000,
 42	DS_BASE_VRAM = 0x06000000,
 43	DS9_BASE_OAM = 0x07000000,
 44	DS_BASE_SLOT2 = 0x08000000,
 45	DS_BASE_SLOT2_EX = 0x09000000,
 46	DS9_BASE_BIOS = 0xFFFF0000,
 47};
 48
 49enum {
 50	DS9_SIZE_ITCM = 0x00008000,
 51	DS9_SIZE_DTCM = 0x00004000,
 52	DS7_SIZE_BIOS = 0x00004000,
 53	DS9_SIZE_BIOS = 0x00008000,
 54	DS_SIZE_RAM = 0x00400000,
 55	DS_SIZE_WORKING_RAM = 0x00008000,
 56	DS7_SIZE_WORKING_RAM = 0x00010000,
 57	DS9_SIZE_PALETTE_RAM = 0x00000800,
 58	DS9_SIZE_OAM = 0x00000800,
 59	DS_SIZE_SLOT2 = 0x02000000,
 60	DS_SIZE_SLOT2_SRAM = 0x00010000,
 61};
 62
 63enum {
 64	DS_OFFSET_MASK = 0x00FFFFFF,
 65	DS_BASE_OFFSET = 24
 66};
 67
 68enum DSDMAControl {
 69	DS_DMA_INCREMENT = 0,
 70	DS_DMA_DECREMENT = 1,
 71	DS_DMA_FIXED = 2,
 72	DS_DMA_INCREMENT_RELOAD = 3
 73};
 74
 75enum DSDMATiming {
 76	DS_DMA_TIMING_NOW = 0,
 77	DS_DMA_TIMING_VBLANK = 1,
 78	DS_DMA_TIMING_HBLANK = 2,
 79	DS7_DMA_TIMING_SLOT1 = 2,
 80	DS_DMA_TIMING_DISPLAY_START = 3,
 81	DS7_DMA_TIMING_CUSTOM = 3,
 82	DS_DMA_TIMING_MEMORY_DISPLAY = 4,
 83	DS9_DMA_TIMING_SLOT1 = 5,
 84	DS_DMA_TIMING_SLOT2 = 6,
 85	DS_DMA_TIMING_GEOM_FIFO = 7,
 86};
 87
 88mLOG_DECLARE_CATEGORY(DS_MEM);
 89
 90DECL_BITFIELD(DSDMARegister, uint16_t);
 91DECL_BITS(DSDMARegister, DestControl, 5, 2);
 92DECL_BITS(DSDMARegister, SrcControl, 7, 2);
 93DECL_BIT(DSDMARegister, Repeat, 9);
 94DECL_BIT(DSDMARegister, Width, 10);
 95DECL_BITS(DSDMARegister, Timing7, 12, 2);
 96DECL_BITS(DSDMARegister, Timing9, 11, 3);
 97DECL_BIT(DSDMARegister, DoIRQ, 14);
 98DECL_BIT(DSDMARegister, Enable, 15);
 99
100struct DSDMA {
101	DSDMARegister reg;
102
103	uint32_t source;
104	uint32_t dest;
105	int32_t count;
106	uint32_t nextSource;
107	uint32_t nextDest;
108	int32_t nextCount;
109	int32_t nextEvent;
110};
111
112struct DSMemory {
113	uint32_t* bios7;
114	uint32_t* bios9;
115	uint32_t* itcm;
116	uint32_t* dtcm;
117	uint32_t* ram;
118	uint32_t* wram;
119	uint32_t* wram7;
120	uint32_t* rom;
121	uint16_t io7[DS7_REG_MAX >> 1];
122	uint16_t io9[DS9_REG_MAX >> 1];
123
124	size_t romSize;
125	size_t wramSize7;
126	size_t wramSize9;
127
128	char waitstatesSeq32[256];
129	char waitstatesSeq16[256];
130	char waitstatesNonseq32[256];
131	char waitstatesNonseq16[256];
132	char waitstatesPrefetchSeq32[16];
133	char waitstatesPrefetchSeq16[16];
134	char waitstatesPrefetchNonseq32[16];
135	char waitstatesPrefetchNonseq16[16];
136};
137
138struct DSCoreMemory {
139	uint16_t* io;
140	int activeRegion;
141
142	struct DSDMA dma[4];
143	int activeDMA;
144};
145
146struct DS;
147void DSMemoryInit(struct DS* ds);
148void DSMemoryDeinit(struct DS* ds);
149
150void DSMemoryReset(struct DS* ds);
151
152uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
153uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
154uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
155
156void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
157void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
158void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
159
160uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
161                         int* cycleCounter);
162uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
163                          int* cycleCounter);
164
165uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
166uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
167uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
168
169void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
170void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
171void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
172
173uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
174                         int* cycleCounter);
175uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
176                          int* cycleCounter);
177
178#endif