src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/sm83/sm83.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value);
39
40static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
41static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
42static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
43static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
44
45static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
46
47static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
48static void _GBPocketCamCapture(struct GBMemory*);
49
50void GBMBCSwitchBank(struct GB* gb, int bank) {
51 size_t bankStart = bank * GB_SIZE_CART_BANK0;
52 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
53 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
54 bankStart &= (gb->memory.romSize - 1);
55 bank = bankStart / GB_SIZE_CART_BANK0;
56 }
57 gb->memory.romBank = &gb->memory.rom[bankStart];
58 gb->memory.currentBank = bank;
59 if (gb->cpu->pc < GB_BASE_VRAM) {
60 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
61 }
62}
63
64void GBMBCSwitchBank0(struct GB* gb, int bank) {
65 size_t bankStart = bank * GB_SIZE_CART_BANK0;
66 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
67 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
68 bankStart &= (gb->memory.romSize - 1);
69 }
70 gb->memory.romBase = &gb->memory.rom[bankStart];
71 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
72 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
73 }
74}
75
76void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
77 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
78 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
79 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
80 bankStart &= (gb->memory.romSize - 1);
81 bank = bankStart / GB_SIZE_CART_HALFBANK;
82 if (!bank) {
83 ++bank;
84 }
85 }
86 if (!half) {
87 gb->memory.romBank = &gb->memory.rom[bankStart];
88 gb->memory.currentBank = bank;
89 } else {
90 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
91 gb->memory.mbcState.mbc6.currentBank1 = bank;
92 }
93 if (gb->cpu->pc < GB_BASE_VRAM) {
94 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
95 }
96}
97
98static bool _isMulticart(const uint8_t* mem) {
99 bool success;
100 struct VFile* vf;
101
102 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
103 success = GBIsROM(vf);
104 vf->close(vf);
105
106 if (!success) {
107 return false;
108 }
109
110 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
111 success = GBIsROM(vf);
112 vf->close(vf);
113
114 if (!success) {
115 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
116 success = GBIsROM(vf);
117 vf->close(vf);
118 }
119
120 return success;
121}
122
123static bool _isWisdomTree(const uint8_t* mem, size_t size) {
124 size_t i;
125 for (i = 0x134; i < 0x14C; i += 4) {
126 if (*(uint32_t*) &mem[i] != 0) {
127 return false;
128 }
129 }
130 for (i = 0xF0; i < 0x100; i += 4) {
131 if (*(uint32_t*) &mem[i] != 0) {
132 return false;
133 }
134 }
135 if (mem[0x14D] != 0xE7) {
136 return false;
137 }
138 for (i = 0x300; i < size - 11; ++i) {
139 if (memcmp(&mem[i], "WISDOM", 6) == 0 && memcmp(&mem[i + 7], "TREE", 4) == 0) {
140 return true;
141 }
142 }
143 return false;
144}
145
146void GBMBCSwitchSramBank(struct GB* gb, int bank) {
147 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
148 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
149 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
150 bankStart &= (gb->sramSize - 1);
151 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
152 }
153 gb->memory.sramBank = &gb->memory.sram[bankStart];
154 gb->memory.sramCurrentBank = bank;
155}
156
157void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
158 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
159 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
160 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
161 bankStart &= (gb->sramSize - 1);
162 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
163 }
164 if (!half) {
165 gb->memory.sramBank = &gb->memory.sram[bankStart];
166 gb->memory.sramCurrentBank = bank;
167 } else {
168 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
169 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
170 }
171}
172
173void GBMBCInit(struct GB* gb) {
174 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
175 if (gb->memory.rom) {
176 if (gb->memory.romSize >= 0x8000) {
177 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
178 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
179 cart = cartFooter;
180 }
181 }
182 switch (cart->ramSize) {
183 case 0:
184 gb->sramSize = 0;
185 break;
186 case 1:
187 gb->sramSize = 0x800;
188 break;
189 default:
190 case 2:
191 gb->sramSize = 0x2000;
192 break;
193 case 3:
194 gb->sramSize = 0x8000;
195 break;
196 case 4:
197 gb->sramSize = 0x20000;
198 break;
199 case 5:
200 gb->sramSize = 0x10000;
201 break;
202 }
203
204 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
205 switch (cart->type) {
206 case 0:
207 if (_isWisdomTree(gb->memory.rom, gb->memory.romSize)) {
208 gb->memory.mbcType = GB_UNL_WISDOM_TREE;
209 break;
210 }
211 // Fall through
212 case 8:
213 case 9:
214 gb->memory.mbcType = GB_MBC_NONE;
215 break;
216 case 1:
217 case 2:
218 case 3:
219 gb->memory.mbcType = GB_MBC1;
220 break;
221 case 5:
222 case 6:
223 gb->memory.mbcType = GB_MBC2;
224 break;
225 case 0x0B:
226 case 0x0C:
227 case 0x0D:
228 gb->memory.mbcType = GB_MMM01;
229 break;
230 case 0x0F:
231 case 0x10:
232 gb->memory.mbcType = GB_MBC3_RTC;
233 break;
234 case 0x11:
235 case 0x12:
236 case 0x13:
237 gb->memory.mbcType = GB_MBC3;
238 break;
239 default:
240 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
241 // Fall through
242 case 0x19:
243 case 0x1A:
244 case 0x1B:
245 gb->memory.mbcType = GB_MBC5;
246 break;
247 case 0x1C:
248 case 0x1D:
249 case 0x1E:
250 gb->memory.mbcType = GB_MBC5_RUMBLE;
251 break;
252 case 0x20:
253 gb->memory.mbcType = GB_MBC6;
254 break;
255 case 0x22:
256 gb->memory.mbcType = GB_MBC7;
257 break;
258 case 0xFC:
259 gb->memory.mbcType = GB_POCKETCAM;
260 break;
261 case 0xFD:
262 gb->memory.mbcType = GB_TAMA5;
263 break;
264 case 0xFE:
265 gb->memory.mbcType = GB_HuC3;
266 break;
267 case 0xFF:
268 gb->memory.mbcType = GB_HuC1;
269 break;
270 }
271 }
272 } else {
273 gb->memory.mbcType = GB_MBC_NONE;
274 }
275 gb->memory.mbcRead = NULL;
276 switch (gb->memory.mbcType) {
277 case GB_MBC_NONE:
278 gb->memory.mbcWrite = _GBMBCNone;
279 break;
280 case GB_MBC1:
281 gb->memory.mbcWrite = _GBMBC1;
282 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
283 gb->memory.mbcState.mbc1.multicartStride = 4;
284 } else {
285 gb->memory.mbcState.mbc1.multicartStride = 5;
286 }
287 break;
288 case GB_MBC2:
289 gb->memory.mbcWrite = _GBMBC2;
290 gb->memory.mbcRead = _GBMBC2Read;
291 gb->sramSize = 0x100;
292 break;
293 case GB_MBC3:
294 gb->memory.mbcWrite = _GBMBC3;
295 break;
296 default:
297 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
298 // Fall through
299 case GB_MBC5:
300 gb->memory.mbcWrite = _GBMBC5;
301 break;
302 case GB_MBC6:
303 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
304 gb->memory.mbcWrite = _GBMBC6;
305 gb->memory.mbcRead = _GBMBC6Read;
306 break;
307 case GB_MBC7:
308 gb->memory.mbcWrite = _GBMBC7;
309 gb->memory.mbcRead = _GBMBC7Read;
310 gb->sramSize = 0x100;
311 break;
312 case GB_MMM01:
313 gb->memory.mbcWrite = _GBMMM01;
314 break;
315 case GB_HuC1:
316 gb->memory.mbcWrite = _GBHuC1;
317 break;
318 case GB_HuC3:
319 gb->memory.mbcWrite = _GBHuC3;
320 break;
321 case GB_TAMA5:
322 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
323 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
324 gb->memory.mbcWrite = _GBTAMA5;
325 gb->memory.mbcRead = _GBTAMA5Read;
326 gb->sramSize = 0x20;
327 break;
328 case GB_MBC3_RTC:
329 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
330 gb->memory.mbcWrite = _GBMBC3;
331 break;
332 case GB_MBC5_RUMBLE:
333 gb->memory.mbcWrite = _GBMBC5;
334 break;
335 case GB_POCKETCAM:
336 gb->memory.mbcWrite = _GBPocketCam;
337 gb->memory.mbcRead = _GBPocketCamRead;
338 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
339 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
340 }
341 break;
342 case GB_UNL_WISDOM_TREE:
343 gb->memory.mbcWrite = _GBWisdomTree;
344 break;
345 }
346
347 gb->memory.currentBank = 1;
348 gb->memory.sramCurrentBank = 0;
349 gb->memory.sramAccess = false;
350 gb->memory.rtcAccess = false;
351 gb->memory.activeRtcReg = 0;
352 gb->memory.rtcLatched = false;
353 gb->memory.rtcLastLatch = 0;
354 if (gb->memory.rtc) {
355 if (gb->memory.rtc->sample) {
356 gb->memory.rtc->sample(gb->memory.rtc);
357 }
358 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
359 } else {
360 gb->memory.rtcLastLatch = time(0);
361 }
362 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
363
364 GBResizeSram(gb, gb->sramSize);
365
366 if (gb->memory.mbcType == GB_MBC3_RTC) {
367 GBMBCRTCRead(gb);
368 }
369}
370
371static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
372 time_t t;
373 if (rtc) {
374 if (rtc->sample) {
375 rtc->sample(rtc);
376 }
377 t = rtc->unixTime(rtc);
378 } else {
379 t = time(0);
380 }
381 time_t currentLatch = t;
382 t -= *rtcLastLatch;
383 *rtcLastLatch = currentLatch;
384
385 int64_t diff;
386 diff = rtcRegs[0] + t % 60;
387 if (diff < 0) {
388 diff += 60;
389 t -= 60;
390 }
391 rtcRegs[0] = diff % 60;
392 t /= 60;
393 t += diff / 60;
394
395 diff = rtcRegs[1] + t % 60;
396 if (diff < 0) {
397 diff += 60;
398 t -= 60;
399 }
400 rtcRegs[1] = diff % 60;
401 t /= 60;
402 t += diff / 60;
403
404 diff = rtcRegs[2] + t % 24;
405 if (diff < 0) {
406 diff += 24;
407 t -= 24;
408 }
409 rtcRegs[2] = diff % 24;
410 t /= 24;
411 t += diff / 24;
412
413 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
414 rtcRegs[3] = diff;
415 rtcRegs[4] &= 0xFE;
416 rtcRegs[4] |= (diff >> 8) & 1;
417 if (diff & 0x200) {
418 rtcRegs[4] |= 0x80;
419 }
420}
421
422static void _GBMBC1Update(struct GB* gb) {
423 struct GBMBC1State* state = &gb->memory.mbcState.mbc1;
424 int bank = state->bankLo;
425 bank &= (1 << state->multicartStride) - 1;
426 bank |= state->bankHi << state->multicartStride;
427 if (state->mode) {
428 GBMBCSwitchBank0(gb, state->bankHi << state->multicartStride);
429 GBMBCSwitchSramBank(gb, state->bankHi & 3);
430 } else {
431 GBMBCSwitchBank0(gb, 0);
432 GBMBCSwitchSramBank(gb, 0);
433 }
434 if (!(state->bankLo & 0x1F)) {
435 ++bank;
436 }
437 GBMBCSwitchBank(gb, bank);
438}
439
440void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
441 struct GBMemory* memory = &gb->memory;
442 int bank = value & 0x1F;
443 switch (address >> 13) {
444 case 0x0:
445 switch (value & 0xF) {
446 case 0:
447 memory->sramAccess = false;
448 break;
449 case 0xA:
450 memory->sramAccess = true;
451 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
452 break;
453 default:
454 // TODO
455 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
456 break;
457 }
458 break;
459 case 0x1:
460 memory->mbcState.mbc1.bankLo = bank;
461 _GBMBC1Update(gb);
462 break;
463 case 0x2:
464 bank &= 3;
465 memory->mbcState.mbc1.bankHi = bank;
466 _GBMBC1Update(gb);
467 break;
468 case 0x3:
469 memory->mbcState.mbc1.mode = value & 1;
470 _GBMBC1Update(gb);
471 break;
472 default:
473 // TODO
474 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
475 break;
476 }
477}
478
479void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
480 struct GBMemory* memory = &gb->memory;
481 int shift = (address & 1) * 4;
482 int bank = value & 0xF;
483 switch (address >> 13) {
484 case 0x0:
485 switch (value) {
486 case 0:
487 memory->sramAccess = false;
488 break;
489 case 0xA:
490 memory->sramAccess = true;
491 break;
492 default:
493 // TODO
494 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
495 break;
496 }
497 break;
498 case 0x1:
499 if (!bank) {
500 ++bank;
501 }
502 GBMBCSwitchBank(gb, bank);
503 break;
504 case 0x5:
505 if (!memory->sramAccess) {
506 return;
507 }
508 address &= 0x1FF;
509 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
510 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
511 break;
512 default:
513 // TODO
514 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
515 break;
516 }
517}
518
519static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
520 address &= 0x1FF;
521 int shift = (address & 1) * 4;
522 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
523}
524
525void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
526 struct GBMemory* memory = &gb->memory;
527 int bank = value;
528 switch (address >> 13) {
529 case 0x0:
530 switch (value) {
531 case 0:
532 memory->sramAccess = false;
533 break;
534 case 0xA:
535 memory->sramAccess = true;
536 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
537 break;
538 default:
539 // TODO
540 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
541 break;
542 }
543 break;
544 case 0x1:
545 if (gb->memory.romSize < GB_SIZE_CART_BANK0 * 0x80) {
546 bank &= 0x7F;
547 }
548 if (!bank) {
549 ++bank;
550 }
551 GBMBCSwitchBank(gb, bank);
552 break;
553 case 0x2:
554 if (value < 8) {
555 GBMBCSwitchSramBank(gb, value);
556 memory->rtcAccess = false;
557 } else if (value <= 0xC) {
558 memory->activeRtcReg = value - 8;
559 memory->rtcAccess = true;
560 }
561 break;
562 case 0x3:
563 if (memory->rtcLatched && value == 0) {
564 memory->rtcLatched = false;
565 } else if (!memory->rtcLatched && value == 1) {
566 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
567 memory->rtcLatched = true;
568 }
569 break;
570 }
571}
572
573void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
574 struct GBMemory* memory = &gb->memory;
575 int bank;
576 switch (address >> 12) {
577 case 0x0:
578 case 0x1:
579 switch (value) {
580 case 0:
581 memory->sramAccess = false;
582 break;
583 case 0xA:
584 memory->sramAccess = true;
585 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
586 break;
587 default:
588 // TODO
589 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
590 break;
591 }
592 break;
593 case 0x2:
594 bank = (memory->currentBank & 0x100) | value;
595 GBMBCSwitchBank(gb, bank);
596 break;
597 case 0x3:
598 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
599 GBMBCSwitchBank(gb, bank);
600 break;
601 case 0x4:
602 case 0x5:
603 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
604 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
605 value &= ~8;
606 }
607 GBMBCSwitchSramBank(gb, value & 0xF);
608 break;
609 default:
610 // TODO
611 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
612 break;
613 }
614}
615
616void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
617 struct GBMemory* memory = &gb->memory;
618 int bank = value;
619 switch (address >> 10) {
620 case 0:
621 switch (value) {
622 case 0:
623 memory->mbcState.mbc6.sramAccess = false;
624 break;
625 case 0xA:
626 memory->mbcState.mbc6.sramAccess = true;
627 break;
628 default:
629 // TODO
630 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
631 break;
632 }
633 break;
634 case 0x1:
635 GBMBCSwitchSramHalfBank(gb, 0, bank);
636 break;
637 case 0x2:
638 GBMBCSwitchSramHalfBank(gb, 1, bank);
639 break;
640 case 0x8:
641 case 0x9:
642 GBMBCSwitchHalfBank(gb, 0, bank);
643 break;
644 case 0xC:
645 case 0xD:
646 GBMBCSwitchHalfBank(gb, 1, bank);
647 break;
648 case 0x28:
649 case 0x29:
650 case 0x2A:
651 case 0x2B:
652 if (memory->mbcState.mbc6.sramAccess) {
653 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
654 }
655 break;
656 case 0x2C:
657 case 0x2D:
658 case 0x2E:
659 case 0x2F:
660 if (memory->mbcState.mbc6.sramAccess) {
661 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
662 }
663 break;
664 default:
665 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
666 break;
667 }
668}
669
670uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
671 if (!memory->mbcState.mbc6.sramAccess) {
672 return 0xFF;
673 }
674 switch (address >> 12) {
675 case 0xA:
676 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
677 case 0xB:
678 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
679 }
680 return 0xFF;
681}
682
683void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
684 int bank = value & 0x7F;
685 switch (address >> 13) {
686 case 0x0:
687 switch (value) {
688 default:
689 case 0:
690 gb->memory.mbcState.mbc7.access = 0;
691 break;
692 case 0xA:
693 gb->memory.mbcState.mbc7.access |= 1;
694 break;
695 }
696 break;
697 case 0x1:
698 GBMBCSwitchBank(gb, bank);
699 break;
700 case 0x2:
701 if (value == 0x40) {
702 gb->memory.mbcState.mbc7.access |= 2;
703 } else {
704 gb->memory.mbcState.mbc7.access &= ~2;
705 }
706 break;
707 case 0x5:
708 _GBMBC7Write(&gb->memory, address, value);
709 break;
710 default:
711 // TODO
712 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
713 break;
714 }
715}
716
717uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
718 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
719 if (mbc7->access != 3) {
720 return 0xFF;
721 }
722 switch (address & 0xF0) {
723 case 0x20:
724 if (memory->rotation && memory->rotation->readTiltX) {
725 int32_t x = -memory->rotation->readTiltX(memory->rotation);
726 x >>= 21;
727 x += 0x81D0;
728 return x;
729 }
730 return 0xFF;
731 case 0x30:
732 if (memory->rotation && memory->rotation->readTiltX) {
733 int32_t x = -memory->rotation->readTiltX(memory->rotation);
734 x >>= 21;
735 x += 0x81D0;
736 return x >> 8;
737 }
738 return 7;
739 case 0x40:
740 if (memory->rotation && memory->rotation->readTiltY) {
741 int32_t y = -memory->rotation->readTiltY(memory->rotation);
742 y >>= 21;
743 y += 0x81D0;
744 return y;
745 }
746 return 0xFF;
747 case 0x50:
748 if (memory->rotation && memory->rotation->readTiltY) {
749 int32_t y = -memory->rotation->readTiltY(memory->rotation);
750 y >>= 21;
751 y += 0x81D0;
752 return y >> 8;
753 }
754 return 7;
755 case 0x60:
756 return 0;
757 case 0x80:
758 return mbc7->eeprom;
759 default:
760 return 0xFF;
761 }
762}
763
764static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
765 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
766 if (mbc7->access != 3) {
767 return;
768 }
769 switch (address & 0xF0) {
770 case 0x00:
771 mbc7->latch = (value & 0x55) == 0x55;
772 return;
773 case 0x10:
774 mbc7->latch |= (value & 0xAA);
775 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
776 memory->rotation->sample(memory->rotation);
777 }
778 mbc7->latch = 0;
779 return;
780 default:
781 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
782 return;
783 case 0x80:
784 break;
785 }
786 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
787 value = GBMBC7FieldFillDO(value); // Hi-Z
788 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
789 mbc7->state = GBMBC7_STATE_IDLE;
790 }
791 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
792 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
793 mbc7->sr <<= 1;
794 mbc7->sr |= GBMBC7FieldGetDI(value);
795 ++mbc7->srBits;
796 }
797 switch (mbc7->state) {
798 case GBMBC7_STATE_IDLE:
799 if (GBMBC7FieldIsDI(value)) {
800 mbc7->state = GBMBC7_STATE_READ_COMMAND;
801 mbc7->srBits = 0;
802 mbc7->sr = 0;
803 }
804 break;
805 case GBMBC7_STATE_READ_COMMAND:
806 if (mbc7->srBits == 10) {
807 mbc7->state = 0x10 | (mbc7->sr >> 6);
808 if (mbc7->state & 0xC) {
809 mbc7->state &= ~0x3;
810 }
811 mbc7->srBits = 0;
812 mbc7->address = mbc7->sr & 0x7F;
813 }
814 break;
815 case GBMBC7_STATE_DO:
816 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
817 mbc7->sr <<= 1;
818 --mbc7->srBits;
819 if (!mbc7->srBits) {
820 mbc7->state = GBMBC7_STATE_IDLE;
821 }
822 break;
823 default:
824 break;
825 }
826 switch (mbc7->state) {
827 case GBMBC7_STATE_EEPROM_EWEN:
828 mbc7->writable = true;
829 mbc7->state = GBMBC7_STATE_IDLE;
830 break;
831 case GBMBC7_STATE_EEPROM_EWDS:
832 mbc7->writable = false;
833 mbc7->state = GBMBC7_STATE_IDLE;
834 break;
835 case GBMBC7_STATE_EEPROM_WRITE:
836 if (mbc7->srBits == 16) {
837 if (mbc7->writable) {
838 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
839 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
840 }
841 mbc7->state = GBMBC7_STATE_IDLE;
842 }
843 break;
844 case GBMBC7_STATE_EEPROM_ERASE:
845 if (mbc7->writable) {
846 memory->sram[mbc7->address * 2] = 0xFF;
847 memory->sram[mbc7->address * 2 + 1] = 0xFF;
848 }
849 mbc7->state = GBMBC7_STATE_IDLE;
850 break;
851 case GBMBC7_STATE_EEPROM_READ:
852 mbc7->srBits = 16;
853 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
854 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
855 mbc7->state = GBMBC7_STATE_DO;
856 value = GBMBC7FieldClearDO(value);
857 break;
858 case GBMBC7_STATE_EEPROM_WRAL:
859 if (mbc7->srBits == 16) {
860 if (mbc7->writable) {
861 int i;
862 for (i = 0; i < 128; ++i) {
863 memory->sram[i * 2] = mbc7->sr >> 8;
864 memory->sram[i * 2 + 1] = mbc7->sr;
865 }
866 }
867 mbc7->state = GBMBC7_STATE_IDLE;
868 }
869 break;
870 case GBMBC7_STATE_EEPROM_ERAL:
871 if (mbc7->writable) {
872 int i;
873 for (i = 0; i < 128; ++i) {
874 memory->sram[i * 2] = 0xFF;
875 memory->sram[i * 2 + 1] = 0xFF;
876 }
877 }
878 mbc7->state = GBMBC7_STATE_IDLE;
879 break;
880 default:
881 break;
882 }
883 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
884 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
885 }
886 mbc7->eeprom = value;
887}
888
889void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
890 struct GBMemory* memory = &gb->memory;
891 if (!memory->mbcState.mmm01.locked) {
892 switch (address >> 13) {
893 case 0x0:
894 memory->mbcState.mmm01.locked = true;
895 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
896 break;
897 case 0x1:
898 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
899 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
900 break;
901 case 0x2:
902 memory->mbcState.mmm01.currentBank0 &= ~0x180;
903 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
904 break;
905 default:
906 // TODO
907 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
908 break;
909 }
910 return;
911 }
912 switch (address >> 13) {
913 case 0x0:
914 switch (value) {
915 case 0xA:
916 memory->sramAccess = true;
917 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
918 break;
919 default:
920 memory->sramAccess = false;
921 break;
922 }
923 break;
924 case 0x1:
925 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
926 break;
927 case 0x2:
928 GBMBCSwitchSramBank(gb, value);
929 break;
930 default:
931 // TODO
932 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
933 break;
934 }
935}
936
937void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
938 struct GBMemory* memory = &gb->memory;
939 int bank = value & 0x3F;
940 switch (address >> 13) {
941 case 0x0:
942 switch (value) {
943 case 0xE:
944 memory->sramAccess = false;
945 break;
946 default:
947 memory->sramAccess = true;
948 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
949 break;
950 }
951 break;
952 case 0x1:
953 GBMBCSwitchBank(gb, bank);
954 break;
955 case 0x2:
956 GBMBCSwitchSramBank(gb, value);
957 break;
958 default:
959 // TODO
960 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
961 break;
962 }
963}
964
965void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
966 struct GBMemory* memory = &gb->memory;
967 int bank = value & 0x3F;
968 if (address & 0x1FFF) {
969 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
970 }
971
972 switch (address >> 13) {
973 case 0x0:
974 switch (value) {
975 case 0xA:
976 memory->sramAccess = true;
977 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
978 break;
979 default:
980 memory->sramAccess = false;
981 break;
982 }
983 break;
984 case 0x1:
985 GBMBCSwitchBank(gb, bank);
986 break;
987 case 0x2:
988 GBMBCSwitchSramBank(gb, bank);
989 break;
990 default:
991 // TODO
992 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
993 break;
994 }
995}
996
997void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
998 struct GBMemory* memory = &gb->memory;
999 int bank = value & 0x3F;
1000 switch (address >> 13) {
1001 case 0x0:
1002 switch (value) {
1003 case 0:
1004 memory->sramAccess = false;
1005 break;
1006 case 0xA:
1007 memory->sramAccess = true;
1008 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1009 break;
1010 default:
1011 // TODO
1012 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
1013 break;
1014 }
1015 break;
1016 case 0x1:
1017 GBMBCSwitchBank(gb, bank);
1018 break;
1019 case 0x2:
1020 if (value < 0x10) {
1021 GBMBCSwitchSramBank(gb, value);
1022 memory->mbcState.pocketCam.registersActive = false;
1023 } else {
1024 memory->mbcState.pocketCam.registersActive = true;
1025 }
1026 break;
1027 case 0x5:
1028 address &= 0x7F;
1029 if (address == 0 && value & 1) {
1030 value &= 6; // TODO: Timing
1031 _GBPocketCamCapture(memory);
1032 }
1033 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
1034 memory->mbcState.pocketCam.registers[address] = value;
1035 }
1036 break;
1037 default:
1038 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
1039 break;
1040 }
1041}
1042
1043uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1044 if (memory->mbcState.pocketCam.registersActive) {
1045 if ((address & 0x7F) == 0) {
1046 return memory->mbcState.pocketCam.registers[0];
1047 }
1048 return 0;
1049 }
1050 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1051}
1052
1053void _GBPocketCamCapture(struct GBMemory* memory) {
1054 if (!memory->cam) {
1055 return;
1056 }
1057 const void* image = NULL;
1058 size_t stride;
1059 enum mColorFormat format;
1060 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1061 if (!image) {
1062 return;
1063 }
1064 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1065 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1066 size_t x, y;
1067 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1068 for (x = 0; x < GBCAM_WIDTH; ++x) {
1069 uint32_t gray;
1070 uint32_t color;
1071 switch (format) {
1072 case mCOLOR_XBGR8:
1073 case mCOLOR_XRGB8:
1074 case mCOLOR_ARGB8:
1075 case mCOLOR_ABGR8:
1076 color = ((const uint32_t*) image)[y * stride + x];
1077 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1078 break;
1079 case mCOLOR_BGRX8:
1080 case mCOLOR_RGBX8:
1081 case mCOLOR_RGBA8:
1082 case mCOLOR_BGRA8:
1083 color = ((const uint32_t*) image)[y * stride + x];
1084 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1085 break;
1086 case mCOLOR_BGR5:
1087 case mCOLOR_RGB5:
1088 case mCOLOR_ARGB5:
1089 case mCOLOR_ABGR5:
1090 color = ((const uint16_t*) image)[y * stride + x];
1091 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1092 break;
1093 case mCOLOR_BGR565:
1094 case mCOLOR_RGB565:
1095 color = ((const uint16_t*) image)[y * stride + x];
1096 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1097 break;
1098 case mCOLOR_BGRA5:
1099 case mCOLOR_RGBA5:
1100 color = ((const uint16_t*) image)[y * stride + x];
1101 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1102 break;
1103 default:
1104 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1105 return;
1106 }
1107 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1108 gray = (gray + 1) * exposure / 0x300;
1109 // TODO: Additional processing
1110 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1111 if (gray < pocketCam->registers[matrixEntry + 6]) {
1112 gray = 0x101;
1113 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1114 gray = 0x100;
1115 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1116 gray = 0x001;
1117 } else {
1118 gray = 0;
1119 }
1120 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1121 uint16_t existing;
1122 LOAD_16LE(existing, coord + 0x100, memory->sram);
1123 existing |= gray << (7 - (x & 7));
1124 STORE_16LE(existing, coord + 0x100, memory->sram);
1125 }
1126 }
1127}
1128
1129void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1130 struct GBMemory* memory = &gb->memory;
1131 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1132 switch (address >> 13) {
1133 case 0x5:
1134 if (address & 1) {
1135 tama5->reg = value;
1136 } else {
1137 value &= 0xF;
1138 if (tama5->reg < GBTAMA5_MAX) {
1139 tama5->registers[tama5->reg] = value;
1140 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1141 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1142 switch (tama5->reg) {
1143 case GBTAMA5_BANK_LO:
1144 case GBTAMA5_BANK_HI:
1145 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1146 break;
1147 case GBTAMA5_WRITE_LO:
1148 case GBTAMA5_WRITE_HI:
1149 case GBTAMA5_CS:
1150 break;
1151 case GBTAMA5_ADDR_LO:
1152 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1153 case 0x0: // RAM write
1154 memory->sram[address] = out;
1155 break;
1156 case 0x1: // RAM read
1157 break;
1158 default:
1159 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1160 }
1161 break;
1162 default:
1163 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1164 break;
1165 }
1166 } else {
1167 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1168 }
1169 }
1170 break;
1171 default:
1172 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1173 }
1174}
1175
1176uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1177 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1178 if ((address & 0x1FFF) > 1) {
1179 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1180 }
1181 if (address & 1) {
1182 return 0xFF;
1183 } else {
1184 uint8_t value = 0xF0;
1185 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1186 switch (tama5->reg) {
1187 case GBTAMA5_ACTIVE:
1188 return 0xF1;
1189 case GBTAMA5_READ_LO:
1190 case GBTAMA5_READ_HI:
1191 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1192 case 1:
1193 value = memory->sram[address];
1194 break;
1195 default:
1196 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1197 break;
1198 }
1199 if (tama5->reg == GBTAMA5_READ_HI) {
1200 value >>= 4;
1201 }
1202 value |= 0xF0;
1203 return value;
1204 default:
1205 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1206 return 0xF1;
1207 }
1208 }
1209}
1210
1211void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) {
1212 UNUSED(value);
1213 int bank = address & 0x3F;
1214 switch (address >> 14) {
1215 case 0x0:
1216 GBMBCSwitchBank0(gb, bank * 2);
1217 GBMBCSwitchBank(gb, bank * 2 + 1);
1218 break;
1219 default:
1220 // TODO
1221 mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value);
1222 break;
1223 }
1224}
1225
1226void GBMBCRTCRead(struct GB* gb) {
1227 struct GBMBCRTCSaveBuffer rtcBuffer;
1228 struct VFile* vf = gb->sramVf;
1229 if (!vf) {
1230 return;
1231 }
1232 vf->seek(vf, gb->sramSize, SEEK_SET);
1233 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1234 return;
1235 }
1236
1237 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1238 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1239 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1240 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1241 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1242 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1243}
1244
1245void GBMBCRTCWrite(struct GB* gb) {
1246 struct VFile* vf = gb->sramVf;
1247 if (!vf) {
1248 return;
1249 }
1250
1251 uint8_t rtcRegs[5];
1252 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1253 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1254 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1255
1256 struct GBMBCRTCSaveBuffer rtcBuffer;
1257 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1258 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1259 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1260 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1261 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1262 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1263 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1264 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1265 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1266 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1267 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1268
1269 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1270 // Writing past the end of the file can invalidate the file mapping
1271 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1272 gb->memory.sram = NULL;
1273 }
1274 vf->seek(vf, gb->sramSize, SEEK_SET);
1275 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1276 if (!gb->memory.sram) {
1277 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1278 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1279 }
1280}