include/mgba/internal/arm/emitter-arm.h (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef EMITTER_ARM_H
7#define EMITTER_ARM_H
8
9#include "emitter-inlines.h"
10
11#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
12 EMITTER ## NAME
13
14#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
15 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
16 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
17
18#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
19 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
20 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
21 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
22 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
23 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
24 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
25 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
26 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
27 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
28 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
29 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
30 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
31 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
32 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
33 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
34 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
35
36#define DECLARE_ARM_ALU_BLOCKv5(EMITTER, ALU, EX1, EX2, EX3, EX4, V) \
37 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
38 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
39 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
40 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
41 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
42 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
43 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
44 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
45 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
46 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
47 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
48 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
49 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
50 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, EX3), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
51 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
52 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, EX4), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)
53
54#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
55 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
56 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
57
58#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, NAME, P, U, W, V) \
59 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## I ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W), V >= 5)), \
60 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## I ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W), V >= 5))
61
62#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
63 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
64 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
65 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
66 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
67 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
68 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
69 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
70 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
71 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
72 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
73 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
74 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
75 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
76 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
77 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
78 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
79
80#define DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, NAME, P, U, W, V) \
81 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSL_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), V >= 5), \
82 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
83 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), V >= 5), \
84 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
85 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ASR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), V >= 5), \
86 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
87 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ROR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), V >= 5), \
88 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
89 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSL_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), V >= 5), \
90 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
91 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), V >= 5), \
92 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
93 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ASR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), V >= 5), \
94 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
95 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ROR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), V >= 5), \
96 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
97
98#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
99 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
100 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
101
102#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, NAME, MODE, W, V) \
103 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## MODE ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W), V >= 5)), \
104 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## MODE ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W), V >= 5))
105
106#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
107 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
108
109// TODO: Support coprocessors
110#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, N, W) \
111 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
112 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
113
114#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2, NAME3) \
115 DO_8(DO_INTERLACE( \
116 DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))), \
117 DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME3)))))
118
119#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
120 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
121
122#define DECLARE_ARM_EMITTER_BLOCK(EMITTER, V) \
123 /* -00---X- */ DECLARE_ARM_ALU_BLOCKv5(EMITTER, AND, MUL, STRH, LDRD, STRD, V), \
124 /* -01---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
125 /* -02---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, STRH, ILL, ILL), \
126 /* -03---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, LDRH, LDRSB, LDRSH), \
127 /* -04---X- */ DECLARE_ARM_ALU_BLOCKv5(EMITTER, SUB, ILL, STRHI, LDRDI, STRDI, V), \
128 /* -05---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
129 /* -06---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, STRHI, ILL, ILL), \
130 /* -07---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, LDRHI, LDRSBI, LDRSHI), \
131 /* -08---X- */ DECLARE_ARM_ALU_BLOCKv5(EMITTER, ADD, UMULL, STRHU, LDRDU, STRDU, V), \
132 /* -09---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
133 /* -0A---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, STRHU, ILL, ILL), \
134 /* -0B---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, LDRHU, LDRSBU, LDRSHU), \
135 /* -0C---X- */ DECLARE_ARM_ALU_BLOCKv5(EMITTER, SBC, SMULL, STRHIU, LDRDIU, STRDIU, V), \
136 /* -0D---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
137 /* -0E---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, STRHIU, ILL, ILL), \
138 /* -0F---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, LDRHIU, LDRSBIU, LDRSHIU), \
139 /* -10---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
140 /* -10---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
141 /* -10---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
142 /* -10---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
143 /* -10---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
144 /* -10---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL /* QADD */), \
145 /* -10---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
146 /* -10---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
147 /* -10---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
148 /* -10---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
149 /* -10---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
150 /* -10---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
151 /* -10---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
152 /* -10---D- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, LDRDP), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
153 /* -10---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
154 /* -10---F- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, STRDP), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
155 /* -11---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
156 /* -12---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
157 /* -12---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
158 /* -12---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL /* BXJ */), \
159 /* -12---3- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX2), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
160 /* -12---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
161 /* -12---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL /* QSUB */), \
162 /* -12---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
163 /* -12---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
164 /* -12---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLAWB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
165 /* -12---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
166 /* -12---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULWB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
167 /* -12---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
168 /* -12---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLAWT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
169 /* -12---D- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, LDRDPW), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
170 /* -12---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULWT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
171 /* -12---F- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, STRDPW), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
172 /* -13---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
173 /* -14---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
174 /* -14---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
175 /* -14---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
176 /* -14---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
177 /* -14---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
178 /* -14---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL /* QDADD */), \
179 /* -14---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
180 /* -14---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
181 /* -14---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
182 /* -14---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
183 /* -14---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
184 /* -14---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
185 /* -14---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
186 /* -14---D- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, LDRDIP), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
187 /* -14---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
188 /* -14---F- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, STRDIP), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
189 /* -15---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
190 /* -16---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
191 /* -16---1- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, CLZ), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
192 /* -16---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
193 /* -16---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
194 /* -16---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
195 /* -16---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL /* QDSUB */), \
196 /* -16---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
197 /* -16---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
198 /* -16---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
199 /* -16---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
200 /* -16---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
201 /* -16---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
202 /* -16---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
203 /* -16---D- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, LDRDIPW), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
204 /* -16---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
205 /* -16---F- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, STRDIPW), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
206 /* -17---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
207 /* -18---X- */ DECLARE_ARM_ALU_BLOCKv5(EMITTER, ORR, SMLAL, STRHPU, LDRDPU, STRDPU, V), \
208 /* -19---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
209 /* -1A---X- */ DECLARE_ARM_ALU_BLOCKv5(EMITTER, MOV, SMLAL, STRHPUW, LDRDPUW, STRDPUW, V), \
210 /* -1B---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
211 /* -1C---X- */ DECLARE_ARM_ALU_BLOCKv5(EMITTER, BIC, SMLAL, STRHIPU, LDRDIPU, STRDIPU, V), \
212 /* -1D---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
213 /* -1E---X- */ DECLARE_ARM_ALU_BLOCKv5(EMITTER, MVN, SMLAL, STRHIPUW, LDRDIPUW, STRDIPUW, V), \
214 /* -1F---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
215 /* -20---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
216 /* -21---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
217 /* -22---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
218 /* -23---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
219 /* -24---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
220 /* -25---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
221 /* -26---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
222 /* -27---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
223 /* -28---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
224 /* -29---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
225 /* -2A---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
226 /* -2B---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
227 /* -2C---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
228 /* -2D---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
229 /* -2E---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
230 /* -2F---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
231 /* -30---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
232 /* -31---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
233 /* -32---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
234 /* -33---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
235 /* -34---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
236 /* -35---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
237 /* -36---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
238 /* -37---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
239 /* -38---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
240 /* -39---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
241 /* -3A---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
242 /* -3B---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
243 /* -3C---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
244 /* -3D---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
245 /* -3E---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
246 /* -3F---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
247 /* -40---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
248 /* -41---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , , , V), \
249 /* -42---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
250 /* -43---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
251 /* -44---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
252 /* -45---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
253 /* -46---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
254 /* -47---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
255 /* -48---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
256 /* -49---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , U, , V), \
257 /* -4A---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
258 /* -4B---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
259 /* -4C---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
260 /* -4D---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
261 /* -4E---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
262 /* -4F---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
263 /* -50---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
264 /* -51---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , , V), \
265 /* -52---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
266 /* -53---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , W, V), \
267 /* -54---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
268 /* -55---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
269 /* -56---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
270 /* -57---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
271 /* -58---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
272 /* -59---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, , V), \
273 /* -5A---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
274 /* -5B---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, W, V), \
275 /* -5C---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
276 /* -5D---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
277 /* -5E---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
278 /* -5F---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
279 /* -60---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
280 /* -61---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , , , V), \
281 /* -62---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
282 /* -63---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
283 /* -64---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
284 /* -65---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
285 /* -66---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
286 /* -67---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
287 /* -68---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
288 /* -69---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , U, , V), \
289 /* -6A---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
290 /* -6B---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
291 /* -6C---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
292 /* -6D---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
293 /* -6E---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
294 /* -6F---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
295 /* -70---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
296 /* -71---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , , V), \
297 /* -72---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
298 /* -73---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , W, V), \
299 /* -74---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
300 /* -75---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
301 /* -76---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
302 /* -77---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
303 /* -78---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
304 /* -79---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, , V), \
305 /* -7A---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
306 /* -7B---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, W, V), \
307 /* -7C---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
308 /* -7D---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
309 /* -7E---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
310 /* -7F---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
311 /* -80---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
312 /* -81---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, , V), \
313 /* -82---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
314 /* -83---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, W, V), \
315 /* -84---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
316 /* -85---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
317 /* -86---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
318 /* -87---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
319 /* -88---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
320 /* -89---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, , V), \
321 /* -8A---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
322 /* -8B---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, W, V), \
323 /* -8C---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
324 /* -8D---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
325 /* -8E---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
326 /* -8F---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
327 /* -90---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
328 /* -91---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, , V), \
329 /* -92---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
330 /* -93---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, W, V), \
331 /* -94---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
332 /* -95---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
333 /* -96---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
334 /* -97---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
335 /* -98---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
336 /* -99---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, , V), \
337 /* -9A---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
338 /* -9B---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, W, V), \
339 /* -9C---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
340 /* -9D---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
341 /* -9E---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
342 /* -9F---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
343 /* -AX---X- */ DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
344 /* -BX---X- */ DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
345 /* -C0---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
346 /* -C1---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
347 /* -C2---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
348 /* -C3---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
349 /* -C4---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
350 /* -C5---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
351 /* -C6---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
352 /* -C7---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
353 /* -C8---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
354 /* -C9---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
355 /* -CA---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
356 /* -CB---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
357 /* -CC---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
358 /* -CD---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
359 /* -CE---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
360 /* -CF---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
361 /* -D0---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
362 /* -D1---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
363 /* -D2---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
364 /* -D3---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
365 /* -D4---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
366 /* -D5---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
367 /* -D6---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
368 /* -D7---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
369 /* -D8---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
370 /* -D9---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
371 /* -DA---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
372 /* -DB---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
373 /* -DC---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
374 /* -DD---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
375 /* -DE---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
376 /* -DF---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
377 /* -EX---X- */ DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR, MRC), \
378 /* -RX---X- */ DECLARE_ARM_SWI_BLOCK(EMITTER)
379
380#define DECLARE_ARM_F_EMITTER_BLOCK(EMITTER, V) \
381 /* F0X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
382 /* F1X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
383 /* F2X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
384 /* F3X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
385 /* F4X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
386 /* F5X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
387 /* F6X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
388 /* F7X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
389 /* F8X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
390 /* F9X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
391 /* FAX---X- */ DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \
392 /* FBX---X- */ DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \
393 /* FCX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
394 /* FDX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
395 /* FEX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
396 /* FFX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)),
397
398#endif