src/gb/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GB_SERIALIZE_H
7#define GB_SERIALIZE_H
8
9#include "util/common.h"
10
11#include "core/core.h"
12#include "gb/gb.h"
13
14extern const uint32_t GB_SAVESTATE_MAGIC;
15extern const uint32_t GB_SAVESTATE_VERSION;
16
17mLOG_DECLARE_CATEGORY(GB_STATE);
18
19/* Savestate format:
20 * 0x00000 - 0x00003: Version Magic (0x01000001)
21 * 0x00004 - 0x00007: ROM CRC32
22 * 0x00008: Game Boy model
23 * 0x00009 - 0x0000B: Reserved (leave zero)
24 * 0x0000C - 0x0000F: Master cycles
25 * 0x00010 - 0x0001F: Game title/code (e.g. PM_CRYSTALBYTE)
26 * 0x00020 - 0x00047: CPU state:
27 * | 0x00020: A register
28 * | 0x00021: F register
29 * | 0x00022: B register
30 * | 0x00023: C register
31 * | 0x00024: D register
32 * | 0x00025: E register
33 * | 0x00026: H register
34 * | 0x00027: L register
35 * | 0x00028 - 0x00029: SP register
36 * | 0x0002A - 0x0002B: PC register
37 * | 0x0002C - 0x0002F: Cycles since last event
38 * | 0x00030 - 0x00033: Cycles until next event
39 * | 0x00034 - 0x00035: Reserved (current instruction)
40 * | 0x00036 - 0x00037: Index address
41 * | 0x00038: Bus value
42 * | 0x00039: Execution state
43 * | 0x0003A - 0x0003B: IRQ vector
44 * | 0x0003C - 0x0003F: EI pending cycles
45 * | 0x00040 - 0x00043: Reserved (DI pending cycles)
46 * | 0x00044 - 0x00047: Flags
47 * | bit 0: Is condition met?
48 * | bit 1: Is condition IRQ pending?
49 * | bit 2: Double speed
50 * | bit 3: Is EI pending?
51 * | bits 4 - 31: Reserved
52 * 0x00048 - 0x0005B: Audio channel 1/framer state
53 * | 0x00048 - 0x0004B: Envelepe timing
54 * | bits 0 - 6: Remaining length
55 * | bits 7 - 9: Next step
56 * | bits 10 - 20: Shadow frequency register
57 * | bits 21 - 31: Reserved
58 * | 0x0004C - 0x0004F: Next frame
59 * | 0x00050 - 0x00053: Next channel 3 fade
60 * | 0x00054 - 0x00057: Reserved
61 * | 0x00058 - 0x0005B: Next event
62 * 0x0005C - 0x0006B: Audio channel 2 state
63 * | 0x0005C - 0x0005F: Envelepe timing
64 * | bits 0 - 2: Remaining length
65 * | bits 3 - 5: Next step
66 * | bits 6 - 31: Reserved
67 * | 0x00060 - 0x00067: Reserved
68 * | 0x00068 - 0x0006B: Next event
69 * 0x0006C - 0x00093: Audio channel 3 state
70 * | 0x0006C - 0x0008B: Wave banks
71 * | 0x0008C - 0x0008D: Remaining length
72 * | 0x0008E - 0x0008F: Reserved
73 * | 0x00090 - 0x00093: Next event
74 * 0x00094 - 0x000A3: Audio channel 4 state
75 * | 0x00094 - 0x00097: Linear feedback shift register state
76 * | 0x00098 - 0x0009B: Envelepe timing
77 * | bits 0 - 2: Remaining length
78 * | bits 3 - 5: Next step
79 * | bits 6 - 31: Reserved
80 * | 0x00098 - 0x0009F: Reserved
81 * | 0x000A0 - 0x000A3: Next event
82 * 0x000A4 - 0x000B7: Audio miscellaneous state
83 * | TODO: Fix this, they're in big-endian order, but field is little-endian
84 * | 0x000A4: Channel 1 envelope state
85 * | bits 0 - 3: Current volume
86 * | bits 4 - 5: Is dead?
87 * | bit 6: Is high?
88 * | 0x000A5: Channel 2 envelope state
89 * | bits 0 - 3: Current volume
90 * | bits 4 - 5: Is dead?
91 * | bit 6: Is high?
92* | bits 7: Reserved
93 * | 0x000A6: Channel 4 envelope state
94 * | bits 0 - 3: Current volume
95 * | bits 4 - 5: Is dead?
96 * | bit 6: Is high?
97* | bits 7: Reserved
98 * | 0x000A7: Miscellaneous audio flags
99 * | bits 0 - 3: Current frame
100 * | bit 4: Is channel 1 sweep enabled?
101 * | bit 5: Has channel 1 sweep occurred?
102 * | bit 6: Is channel 3's memory readable?
103 * | bit 7: Reserved
104 * | 0x000A8 - 0x000AF: Rserved
105 * | 0x000B0 - 0x000B3: Next sample
106 * 0x000B4 - 0x000153: Video state
107 * | 0x000B4 - 0x000B5: Current x
108 * | 0x000B6 - 0x000B7: Current y (ly)
109 * | 0x000B8 - 0x000BB: Next frame
110 * | 0x000BC - 0x000BF: Reserved
111 * | 0x000C0 - 0x000C3: Next mode
112 * | 0x000C4 - 0x000C7: Dot cycle counter
113 * | 0x000C8 - 0x000CB: Frame counter
114 * | 0x000CC: Current VRAM bank
115 * | 0x000CD: Palette flags
116 * | bit 0: BCP increment
117 * | bit 1: OCP increment
118 * | bits 2 - 3: Mode
119 * | bits 4 - 7: Reserved
120 * | 0x000CE - 0x000CF: Reserved
121 * | 0x000D0 - 0x000D1: BCP index
122 * | 0x000D1 - 0x000D3: OCP index
123 * | 0x000D4 - 0x00153: Palette entries
124 * 0x00154 - 0x000167: Timer state
125 * | 0x00154 - 0x00157: Next event
126 * | 0x00158 - 0x0015B: Next IRQ
127 * | 0x0015C - 0x0015F: Next DIV
128 * | 0x00160 - 0x00163: Inernal DIV
129 * | 0x00164: TIMA period
130 * | 0x00165: Flags
131 * | bit 0: Is IRQ pending?
132 * | 0x00166 - 0x00167: Reserved
133 * 0x000168 - 0x000197: Memory state
134 * | 0x00168 - 0x00169: Current ROM bank
135 * | 0x0016A: Current WRAM bank
136 * | 0x0016B: Current SRAM bank
137 * | 0x0016C - 0x0016F: Next DMA
138 * | 0x00170 - 0x00171: Next DMA source
139 * | 0x00172 - 0x00173: Next DMA destination
140 * | 0x00174 - 0x00177: Next HDMA
141 * | 0x00178 - 0x00179: Next HDMA source
142 * | 0x0017A - 0x0017B: Next HDMA destination
143 * | 0x0017C - 0x0017D: HDMA remaining
144 * | 0x0017E: DMA remaining
145 * | 0x0017F - 0x00183: RTC registers
146 * | 0x00184 - 0x00193: MBC state (TODO)
147 * | 0x00194 - 0x00195: Flags
148 * | bit 0: SRAM accessable
149 * | bit 1: RTC accessible
150 * | bit 2: RTC latched
151 * | bit 3: IME
152 * | bit 4: Is HDMA active?
153 * | bits 5 - 7: Active RTC register
154 * | 0x00196 - 0x00197: Reserved (leave zero)
155 * 0x00198 - 0x0019F: Savestate creation time (usec since 1970)
156 * 0x001A0 - 0x0025F: Reserved (leave zero)
157 * 0x00260 - 0x002FF: OAM
158 * 0x00300 - 0x0037F: I/O memory
159 * 0x00380 - 0x003FE: HRAM
160 * 0x003FF: Interrupts enabled
161 * 0x00400 - 0x043FF: VRAM
162 * 0x04400 - 0x0C3FF: WRAM
163 * Total size: 0xC400 (50,176) bytes
164*/
165
166DECL_BITFIELD(GBSerializedAudioFlags, uint32_t);
167DECL_BITS(GBSerializedAudioFlags, Ch1Volume, 0, 4);
168DECL_BITS(GBSerializedAudioFlags, Ch1Dead, 4, 2);
169DECL_BIT(GBSerializedAudioFlags, Ch1Hi, 6);
170DECL_BITS(GBSerializedAudioFlags, Ch2Volume, 8, 4);
171DECL_BITS(GBSerializedAudioFlags, Ch2Dead, 12, 2);
172DECL_BIT(GBSerializedAudioFlags, Ch2Hi, 14);
173DECL_BITS(GBSerializedAudioFlags, Ch4Volume, 16, 4);
174DECL_BITS(GBSerializedAudioFlags, Ch4Dead, 20, 2);
175DECL_BITS(GBSerializedAudioFlags, Frame, 22, 3);
176DECL_BIT(GBSerializedAudioFlags, Ch1SweepEnabled, 25);
177DECL_BIT(GBSerializedAudioFlags, Ch1SweepOccurred, 26);
178DECL_BIT(GBSerializedAudioFlags, Ch3Readable, 27);
179
180DECL_BITFIELD(GBSerializedAudioEnvelope, uint32_t);
181DECL_BITS(GBSerializedAudioEnvelope, Length, 0, 7);
182DECL_BITS(GBSerializedAudioEnvelope, NextStep, 7, 3);
183DECL_BITS(GBSerializedAudioEnvelope, Frequency, 10, 11);
184
185struct GBSerializedPSGState {
186 struct {
187 GBSerializedAudioEnvelope envelope;
188 int32_t nextFrame;
189 int32_t nextCh3Fade;
190 int32_t reserved;
191 uint32_t nextEvent;
192 } ch1;
193 struct {
194 GBSerializedAudioEnvelope envelope;
195 int32_t reserved[2];
196 int32_t nextEvent;
197 } ch2;
198 struct {
199 uint32_t wavebanks[8];
200 int16_t length;
201 int16_t reserved;
202 uint32_t nextEvent;
203 } ch3;
204 struct {
205 int32_t lfsr;
206 GBSerializedAudioEnvelope envelope;
207 int32_t reserved;
208 uint32_t nextEvent;
209 } ch4;
210};
211
212DECL_BITFIELD(GBSerializedCpuFlags, uint32_t);
213DECL_BIT(GBSerializedCpuFlags, Condition, 0);
214DECL_BIT(GBSerializedCpuFlags, IrqPending, 1);
215DECL_BIT(GBSerializedCpuFlags, DoubleSpeed, 2);
216DECL_BIT(GBSerializedCpuFlags, EiPending, 1);
217
218DECL_BITFIELD(GBSerializedTimerFlags, uint8_t);
219DECL_BIT(GBSerializedTimerFlags, IrqPending, 0);
220
221DECL_BITFIELD(GBSerializedVideoFlags, uint8_t);
222DECL_BIT(GBSerializedVideoFlags, BcpIncrement, 0);
223DECL_BIT(GBSerializedVideoFlags, OcpIncrement, 1);
224DECL_BITS(GBSerializedVideoFlags, Mode, 2, 2);
225DECL_BIT(GBSerializedVideoFlags, NotModeEventScheduled, 4);
226DECL_BIT(GBSerializedVideoFlags, NotFrameEventScheduled, 5);
227
228DECL_BITFIELD(GBSerializedMBC7Flags, uint8_t);
229DECL_BITS(GBSerializedMBC7Flags, Command, 0, 2);
230DECL_BIT(GBSerializedMBC7Flags, Writable, 2);
231
232DECL_BITFIELD(GBSerializedMemoryFlags, uint16_t);
233DECL_BIT(GBSerializedMemoryFlags, SramAccess, 0);
234DECL_BIT(GBSerializedMemoryFlags, RtcAccess, 1);
235DECL_BIT(GBSerializedMemoryFlags, RtcLatched, 2);
236DECL_BIT(GBSerializedMemoryFlags, Ime, 3);
237DECL_BIT(GBSerializedMemoryFlags, IsHdma, 4);
238DECL_BITS(GBSerializedMemoryFlags, ActiveRtcReg, 5, 3);
239
240#pragma pack(push, 1)
241struct GBSerializedState {
242 uint32_t versionMagic;
243 uint32_t romCrc32;
244 uint8_t model;
245 uint8_t reservedHeader[3];
246 uint32_t masterCycles;
247
248 char title[16];
249
250 struct {
251 uint8_t a;
252 uint8_t f;
253 uint8_t b;
254 uint8_t c;
255 uint8_t d;
256 uint8_t e;
257 uint8_t h;
258 uint8_t l;
259 uint16_t sp;
260 uint16_t pc;
261
262 int32_t cycles;
263 int32_t nextEvent;
264
265 uint16_t reservedInstruction;
266 uint16_t index;
267 uint8_t bus;
268 uint8_t executionState;
269
270 uint16_t irqVector;
271
272 uint32_t eiPending;
273 int32_t reservedDiPending;
274 GBSerializedCpuFlags flags;
275 } cpu;
276
277 struct {
278 struct GBSerializedPSGState psg;
279 GBSerializedAudioFlags flags;
280 int32_t reserved[2];
281 uint32_t nextSample;
282 } audio;
283
284 struct {
285 int16_t x;
286 int16_t ly;
287 uint32_t nextFrame;
288 uint32_t reserved;
289 uint32_t nextMode;
290 int32_t dotCounter;
291 int32_t frameCounter;
292
293 uint8_t vramCurrentBank;
294 GBSerializedVideoFlags flags;
295 uint16_t reserved2;
296
297 uint16_t bcpIndex;
298 uint16_t ocpIndex;
299
300 uint16_t palette[64];
301 } video;
302
303 struct {
304 uint32_t nextEvent;
305 uint32_t nextIRQ;
306
307 uint32_t nextDiv;
308 uint32_t internalDiv;
309 uint8_t timaPeriod;
310 GBSerializedTimerFlags flags;
311 uint16_t reserved;
312 } timer;
313
314 struct {
315 uint16_t currentBank;
316 uint8_t wramCurrentBank;
317 uint8_t sramCurrentBank;
318
319 uint32_t dmaNext;
320 uint16_t dmaSource;
321 uint16_t dmaDest;
322
323 uint32_t hdmaNext;
324 uint16_t hdmaSource;
325 uint16_t hdmaDest;
326
327 uint16_t hdmaRemaining;
328 uint8_t dmaRemaining;
329 uint8_t rtcRegs[5];
330
331 union {
332 struct {
333 uint32_t mode;
334 } mbc1;
335 struct {
336 uint64_t lastLatch;
337 } rtc;
338 struct {
339 int8_t machineState;
340 GBMBC7Field field;
341 int8_t address;
342 uint8_t srBits;
343 uint32_t sr;
344 GBSerializedMBC7Flags flags;
345 } mbc7;
346 struct {
347 uint8_t reserved[16];
348 } padding;
349 };
350
351 GBSerializedMemoryFlags flags;
352 uint16_t reserved;
353 } memory;
354
355 uint64_t creationUsec;
356
357 uint32_t reserved[48];
358
359 uint8_t oam[GB_SIZE_OAM];
360
361 uint8_t io[GB_SIZE_IO];
362 uint8_t hram[GB_SIZE_HRAM];
363 uint8_t ie;
364
365 uint8_t vram[GB_SIZE_VRAM];
366 uint8_t wram[GB_SIZE_WORKING_RAM];
367};
368#pragma pack(pop)
369
370bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state);
371void GBSerialize(struct GB* gb, struct GBSerializedState* state);
372
373#endif