1#ifndef ARM_DECODER_H
  2#define ARM_DECODER_H
  3
  4#include <stdint.h>
  5
  6// Bit 0: a register is involved with this operand
  7// Bit 1: an immediate is invovled with this operand
  8// Bit 2: a memory access is invovled with this operand
  9// Bit 3: the destination of this operand is affected by this opcode
 10// Bit 4: this operand is shifted by a register
 11// Bit 5: this operand is shifted by an immediate
 12enum ARMOperandFormat {
 13	ARM_OPERAND_NONE =               0x00000000,
 14	ARM_OPERAND_REGISTER_1 =         0x00000001,
 15	ARM_OPERAND_IMMEDIATE_1 =        0x00000002,
 16	ARM_OPERAND_MEMORY_1 =           0x00000004,
 17	ARM_OPERAND_AFFECTED_1 =         0x00000008,
 18	ARM_OPERAND_SHIFT_REGISTER_1 =   0x00000010,
 19	ARM_OPERAND_SHIFT_IMMEDIATE_1 =  0x00000020,
 20	ARM_OPERAND_1 =                  0x000000FF,
 21
 22	ARM_OPERAND_REGISTER_2 =         0x00000100,
 23	ARM_OPERAND_IMMEDIATE_2 =        0x00000200,
 24	ARM_OPERAND_MEMORY_2 =           0x00000400,
 25	ARM_OPERAND_AFFECTED_2 =         0x00000800,
 26	ARM_OPERAND_SHIFT_REGISTER_2 =   0x00001000,
 27	ARM_OPERAND_SHIFT_IMMEDIATE_2 =  0x00002000,
 28	ARM_OPERAND_2 =                  0x0000FF00,
 29
 30	ARM_OPERAND_REGISTER_3 =         0x00010000,
 31	ARM_OPERAND_IMMEDIATE_3 =        0x00020000,
 32	ARM_OPERAND_MEMORY_3 =           0x00040000,
 33	ARM_OPERAND_AFFECTED_3 =         0x00080000,
 34	ARM_OPERAND_SHIFT_REGISTER_3 =   0x00100000,
 35	ARM_OPERAND_SHIFT_IMMEDIATE_3 =  0x00200000,
 36	ARM_OPERAND_3 =                  0x00FF0000
 37};
 38
 39enum ARMMemoryFormat {
 40	ARM_MEMORY_REGISTER_BASE =    0x0001,
 41	ARM_MEMORY_IMMEDIATE_OFFSET = 0x0002,
 42	ARM_MEMORY_REGISTER_OFFSET  = 0x0004,
 43	ARM_MEMORY_SHIFTED_OFFSET =   0x0008,
 44	ARM_MEMORY_PRE_INCREMENT =    0x0010,
 45	ARM_MEMORY_POST_INCREMENT =   0x0020,
 46	ARM_MEMORY_OFFSET_SUBTRACT =  0x0040
 47};
 48
 49enum ARMCondition {
 50	ARM_CONDITION_EQ = 0x0,
 51	ARM_CONDITION_NE = 0x1,
 52	ARM_CONDITION_CS = 0x2,
 53	ARM_CONDITION_CC = 0x3,
 54	ARM_CONDITION_MI = 0x4,
 55	ARM_CONDITION_PL = 0x5,
 56	ARM_CONDITION_VS = 0x6,
 57	ARM_CONDITION_VC = 0x7,
 58	ARM_CONDITION_HI = 0x8,
 59	ARM_CONDITION_LS = 0x9,
 60	ARM_CONDITION_GE = 0xA,
 61	ARM_CONDITION_LT = 0xB,
 62	ARM_CONDITION_GT = 0xC,
 63	ARM_CONDITION_LE = 0xD,
 64	ARM_CONDITION_AL = 0xE,
 65	ARM_CONDITION_NV = 0xF
 66};
 67
 68union ARMOperand {
 69	struct {
 70		uint8_t reg;
 71		uint8_t shifterOp;
 72		union {
 73			uint8_t shifterReg;
 74			uint8_t shifterImm;
 75		};
 76	};
 77	int32_t immediate;
 78};
 79
 80struct ARMMemoryAccess {
 81	uint8_t baseReg;
 82	uint16_t format;
 83	union ARMOperand offset;
 84};
 85
 86enum ThumbMnemonic {
 87	THUMB_MN_ILL = 0,
 88	THUMB_MN_ADC,
 89	THUMB_MN_ADD,
 90	THUMB_MN_AND,
 91	THUMB_MN_ASR,
 92	THUMB_MN_B,
 93	THUMB_MN_BIC,
 94	THUMB_MN_BKPT,
 95	THUMB_MN_BL,
 96	THUMB_MN_BLH,
 97	THUMB_MN_BX,
 98	THUMB_MN_CMN,
 99	THUMB_MN_CMP,
100	THUMB_MN_EOR,
101	THUMB_MN_LDMIA,
102	THUMB_MN_LDR,
103	THUMB_MN_LDRB,
104	THUMB_MN_LDRH,
105	THUMB_MN_LDRSB,
106	THUMB_MN_LDRSH,
107	THUMB_MN_LSL,
108	THUMB_MN_LSR,
109	THUMB_MN_MOV,
110	THUMB_MN_MUL,
111	THUMB_MN_MVN,
112	THUMB_MN_NEG,
113	THUMB_MN_ORR,
114	THUMB_MN_POP,
115	THUMB_MN_PUSH,
116	THUMB_MN_ROR,
117	THUMB_MN_SBC,
118	THUMB_MN_STMIA,
119	THUMB_MN_STR,
120	THUMB_MN_STRB,
121	THUMB_MN_STRH,
122	THUMB_MN_SUB,
123	THUMB_MN_SWI,
124	THUMB_MN_TST,
125
126	THUMB_MN_MAX
127};
128
129struct ThumbInstructionInfo {
130	uint16_t opcode;
131	enum ThumbMnemonic mnemonic;
132	union ARMOperand op1;
133	union ARMOperand op2;
134	union ARMOperand op3;
135	struct ARMMemoryAccess memory;
136	int operandFormat;
137	int branches;
138	int traps;
139	int accessesSpecialRegisters;
140	int affectsCPSR;
141	int condition;
142	int sDataCycles;
143	int nDataCycles;
144	int sInstructionCycles;
145	int nInstructionCycles;
146	int iCycles;
147	int cCycles;
148};
149
150void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info);
151int ARMDisassembleThumb(uint16_t opcode, uint32_t pc, char* buffer, int blen);
152
153#endif