src/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
24
25#define THUMB_NEUTRAL_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D);
28
29#define APPLY(F, ...) F(__VA_ARGS__)
30
31#define COUNT_1(EMITTER, PREFIX, ...) \
32 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
33 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
34
35#define COUNT_2(EMITTER, PREFIX, ...) \
36 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
37 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
38 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
39
40#define COUNT_3(EMITTER, PREFIX, ...) \
41 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
42 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
43 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
44 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
45 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
46
47#define COUNT_4(EMITTER, PREFIX, ...) \
48 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
49 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
50 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
51 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
52 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
53 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
54 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
55 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
56 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
57
58#define COUNT_5(EMITTER, PREFIX, ...) \
59 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
60 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
61 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
62 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
63 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
64 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
65 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
66 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
67 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
68 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
69 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
70 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
71 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
72 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
73 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
74 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
75 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
76
77#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
78 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
79 BODY; \
80 }
81
82#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
83 DEFINE_INSTRUCTION_THUMB(NAME, \
84 int immediate = IMMEDIATE; \
85 int rd = opcode & 0x0007; \
86 int rm = (opcode >> 3) & 0x0007; \
87 BODY;)
88
89#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
90 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
91
92DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
93 if (!immediate) { \
94 cpu->gprs[rd] = cpu->gprs[rm]; \
95 } else { \
96 cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \
97 cpu->gprs[rd] = cpu->gprs[rm] << immediate; \
98 } \
99 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
100
101DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, ARM_STUB)
102DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
103
104DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, ARM_STUB)
105DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
106DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
107DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, ARM_STUB)
108DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, ARM_STUB)
109DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd]))
110
111#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
112 DEFINE_INSTRUCTION_THUMB(NAME, \
113 int rm = RM; \
114 BODY;)
115
116#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
117 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
118
119DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, ARM_STUB)
120DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
121
122#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
123 DEFINE_INSTRUCTION_THUMB(NAME, \
124 int immediate = IMMEDIATE; \
125 BODY;)
126
127#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
128 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
129
130DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, ARM_STUB)
131DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
132
133#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
134 DEFINE_INSTRUCTION_THUMB(NAME, \
135 int rd = RD; \
136 int immediate = opcode & 0x00FF; \
137 BODY;)
138
139#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
140 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
141
142DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, \
143 int d = cpu->gprs[rd]; \
144 cpu->gprs[rd] = d + immediate; \
145 THUMB_ADDITION_S(d, immediate, cpu->gprs[rd]))
146
147DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, ARM_STUB)
148DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
149DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
150
151#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
152 DEFINE_INSTRUCTION_THUMB(NAME, \
153 int rd = opcode & 0x0007; \
154 int rn = (opcode >> 3) & 0x0007; \
155 BODY;)
156
157DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, ARM_STUB)
158DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, ARM_STUB)
159DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
160DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, ARM_STUB)
161DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, ARM_STUB)
162DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
163DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
164DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
165DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
166DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
167DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
168DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
169DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, ARM_STUB)
170DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
171DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
172DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
173
174#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
175 DEFINE_INSTRUCTION_THUMB(NAME, \
176 int rd = opcode & 0x0007 | H1; \
177 int rm = (opcode >> 3) & 0x0007 | H2; \
178 BODY;)
179
180#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
181 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
182 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
183 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
184 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
185
186DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, ARM_STUB)
187DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, ARM_STUB)
188DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
189
190#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
191 DEFINE_INSTRUCTION_THUMB(NAME, \
192 int rd = RD; \
193 int immediate = (opcode & 0x00FF) << 2; \
194 BODY;)
195
196#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
197 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
198
199DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_PC] + immediate))
200DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, ARM_STUB)
201DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd]))
202
203DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
204DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
205
206#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
207 DEFINE_INSTRUCTION_THUMB(NAME, \
208 int rm = RM; \
209 BODY;)
210
211#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
212 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
213
214DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
215DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
216DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
217DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
218DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
219DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
220DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
221DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
222
223#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
224 DEFINE_INSTRUCTION_THUMB(NAME, \
225 int rn = (opcode >> 8) & 0x000F; \
226 int rs = RS; \
227 int32_t address = ADDRESS; \
228 int m; \
229 int i; \
230 PRE_BODY; \
231 for LOOP { \
232 if (rs & m) { \
233 BODY; \
234 address OP 4; \
235 } \
236 } \
237 POST_BODY; \
238 WRITEBACK;)
239
240#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
241 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
242
243DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
244 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
245 if (!((1 << rn) & rs)) { \
246 cpu->gprs[rn] = address; \
247 })
248
249DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
250 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
251 cpu->gprs[rn] = address)
252
253#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
254 DEFINE_INSTRUCTION_THUMB(B ## COND, \
255 if (ARM_COND_ ## COND) { \
256 ARM_STUB; \
257 })
258
259DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
260DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
261DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
262DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
263DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
264DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
265DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
266DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
267DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
268DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
269DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
270DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
271DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
272DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
273
274DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
275DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
276
277DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
278 opcode & 0x00FF, \
279 cpu->gprs[ARM_SP], \
280 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
281 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
282 +=, \
283 , , \
284 cpu->gprs[ARM_SP] = address)
285
286DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
287 opcode & 0x00FF, \
288 cpu->gprs[ARM_SP], \
289 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
290 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
291 +=, \
292 , \
293 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
294 address += 4;, \
295 cpu->gprs[ARM_SP] = address)
296
297DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
298 opcode & 0x00FF, \
299 cpu->gprs[ARM_SP] - 4, \
300 (m = 0x80, i = 7; m; m >>= 1, --i), \
301 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
302 -=, \
303 , , \
304 cpu->gprs[ARM_SP] = address + 4)
305
306DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
307 opcode & 0x00FF, \
308 cpu->gprs[ARM_SP] - 4, \
309 (m = 0x80, i = 7; m; m >>= 1, --i), \
310 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
311 -=, \
312 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
313 address -= 4;, \
314 , \
315 cpu->gprs[ARM_SP] = address + 4)
316
317DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
318DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
319DEFINE_INSTRUCTION_THUMB(B, ARM_STUB)
320DEFINE_INSTRUCTION_THUMB(BL1, \
321 int16_t immediate = (opcode & 0x07FF) << 7; \
322 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 4);)
323
324DEFINE_INSTRUCTION_THUMB(BL2, \
325 uint16_t immediate = (opcode & 0x07FF) << 1; \
326 uint32_t pc = cpu->gprs[ARM_PC]; \
327 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
328 cpu->gprs[ARM_LR] = pc - 1; \
329 THUMB_WRITE_PC;)
330
331DEFINE_INSTRUCTION_THUMB(BX, ARM_STUB)
332DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
333
334#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
335 EMITTER ## NAME
336
337#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
338 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
339 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
340 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
341 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
342
343#define DUMMY(X, ...) X,
344#define DUMMY_4(...) \
345 DUMMY(__VA_ARGS__) \
346 DUMMY(__VA_ARGS__) \
347 DUMMY(__VA_ARGS__) \
348 DUMMY(__VA_ARGS__)
349
350#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
351 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
352 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
353 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
354 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
355 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
356 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
357 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
358 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
359 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
360 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
361 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
362 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
363 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
364 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
365 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
366 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
367 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
368 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
369 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
370 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
371 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
372 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
373 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
374 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
375 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
376 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
377 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
378 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
379 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
380 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
381 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
382 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
383 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
384 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
385 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
386 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
387 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
388 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
389 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
390 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
391 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
392 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
393 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
394 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
395 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
396 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
397 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
398 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
399 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
400 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
401 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
402 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
403 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
404 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
405 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
406 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
407 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
408 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
409 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
410 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
411 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
412 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
413 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
414 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
415 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
416 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
417 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
418 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
419 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
420 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
421 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
422 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
423 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
424 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
425 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
426 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
427 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
428 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
429 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
430 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
431 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
432 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
433 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
434 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
435 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
436 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
437 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
438 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
439 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
440 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
441 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
442
443static const ThumbInstruction _thumbTable[0x400] = {
444 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
445};