src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13
14static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
17static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
18static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
19
20void GBAMemoryInit(struct GBAMemory* memory) {
21 memory->d.load32 = GBALoad32;
22 memory->d.load16 = GBALoad16;
23 memory->d.loadU16 = GBALoadU16;
24 memory->d.load8 = GBALoad8;
25 memory->d.loadU8 = GBALoadU8;
26 memory->d.store32 = GBAStore32;
27 memory->d.store16 = GBAStore16;
28 memory->d.store8 = GBAStore8;
29
30 memory->bios = (uint32_t*) hleBios;
31 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
32 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
33 memory->rom = 0;
34 memset(memory->io, 0, sizeof(memory->io));
35 memset(memory->dma, 0, sizeof(memory->dma));
36
37 if (!memory->wram || !memory->iwram) {
38 GBAMemoryDeinit(memory);
39 memory->p->errno = GBA_OUT_OF_MEMORY;
40 memory->p->errstr = GBA_CANNOT_MMAP;
41 }
42
43 GBASavedataInit(&memory->savedata, "test.sav");
44
45 int i;
46 for (i = 0; i < 16; ++i) {
47 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
48 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
49 memory->waitstates32[i] = GBA_BASE_WAITSTATES[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
50 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
51 }
52 for (; i < 256; ++i) {
53 memory->waitstates16[i] = 0;
54 memory->waitstatesSeq16[i] = 0;
55 memory->waitstates32[i] = 0;
56 memory->waitstatesSeq32[i] = 0;
57 }
58
59 memory->activeRegion = 0;
60 memory->d.activeRegion = 0;
61 memory->d.activeMask = 0;
62 memory->d.setActiveRegion = GBASetActiveRegion;
63 memory->d.activePrefetchCycles32 = 0;
64 memory->d.activePrefetchCycles16 = 0;
65}
66
67void GBAMemoryDeinit(struct GBAMemory* memory) {
68 munmap(memory->wram, SIZE_WORKING_RAM);
69 munmap(memory->iwram, SIZE_WORKING_IRAM);
70 GBASavedataDeinit(&memory->savedata);
71}
72
73static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
74 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
75
76 memory->activePrefetchCycles32 = gbaMemory->waitstates32[address >> BASE_OFFSET];
77 memory->activePrefetchCycles16 = gbaMemory->waitstates16[address >> BASE_OFFSET];
78 gbaMemory->activeRegion = address >> BASE_OFFSET;
79 switch (address & ~OFFSET_MASK) {
80 case BASE_BIOS:
81 memory->activeRegion = gbaMemory->bios;
82 memory->activeMask = SIZE_BIOS - 1;
83 break;
84 case BASE_WORKING_RAM:
85 memory->activeRegion = gbaMemory->wram;
86 memory->activeMask = SIZE_WORKING_RAM - 1;
87 break;
88 case BASE_WORKING_IRAM:
89 memory->activeRegion = gbaMemory->iwram;
90 memory->activeMask = SIZE_WORKING_IRAM - 1;
91 break;
92 case BASE_CART0:
93 case BASE_CART0_EX:
94 case BASE_CART1:
95 case BASE_CART1_EX:
96 case BASE_CART2:
97 case BASE_CART2_EX:
98 memory->activeRegion = gbaMemory->rom;
99 memory->activeMask = SIZE_CART0 - 1;
100 break;
101 default:
102 memory->activeRegion = 0;
103 memory->activeMask = 0;
104 break;
105 }
106}
107
108int32_t GBALoad32(struct ARMMemory* memory, uint32_t address) {
109 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
110
111 switch (address & ~OFFSET_MASK) {
112 case BASE_BIOS:
113 break;
114 case BASE_WORKING_RAM:
115 return gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
116 case BASE_WORKING_IRAM:
117 return gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
118 case BASE_IO:
119 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1)) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
120 case BASE_PALETTE_RAM:
121 return ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2];
122 case BASE_VRAM:
123 return ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2];
124 case BASE_OAM:
125 break;
126 case BASE_CART0:
127 case BASE_CART0_EX:
128 case BASE_CART1:
129 case BASE_CART1_EX:
130 case BASE_CART2:
131 case BASE_CART2_EX:
132 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
133 return gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
134 }
135 case BASE_CART_SRAM:
136 break;
137 default:
138 break;
139 }
140
141 return 0;
142}
143
144int16_t GBALoad16(struct ARMMemory* memory, uint32_t address) {
145 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
146
147 switch (address & ~OFFSET_MASK) {
148 case BASE_BIOS:
149 break;
150 case BASE_WORKING_RAM:
151 return ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
152 case BASE_WORKING_IRAM:
153 return ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
154 case BASE_IO:
155 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
156 case BASE_PALETTE_RAM:
157 return gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
158 case BASE_VRAM:
159 return gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
160 case BASE_OAM:
161 break;
162 case BASE_CART0:
163 case BASE_CART0_EX:
164 case BASE_CART1:
165 case BASE_CART1_EX:
166 case BASE_CART2:
167 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
168 return ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
169 }
170 case BASE_CART2_EX:
171 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
172 return GBASavedataReadEEPROM(&gbaMemory->savedata);
173 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
174 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
175 }
176 case BASE_CART_SRAM:
177 break;
178 default:
179 break;
180 }
181
182 return 0;
183}
184
185uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address) {
186 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
187
188 switch (address & ~OFFSET_MASK) {
189 case BASE_BIOS:
190 break;
191 case BASE_WORKING_RAM:
192 return ((uint16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
193 case BASE_WORKING_IRAM:
194 return ((uint16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
195 case BASE_IO:
196 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
197 case BASE_PALETTE_RAM:
198 return gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
199 case BASE_VRAM:
200 return gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
201 case BASE_OAM:
202 break;
203 case BASE_CART0:
204 case BASE_CART0_EX:
205 case BASE_CART1:
206 case BASE_CART1_EX:
207 case BASE_CART2:
208 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
209 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
210 }
211 case BASE_CART2_EX:
212 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
213 return GBASavedataReadEEPROM(&gbaMemory->savedata);
214 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
215 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
216 }
217 case BASE_CART_SRAM:
218 break;
219 default:
220 break;
221 }
222
223 return 0;
224}
225
226int8_t GBALoad8(struct ARMMemory* memory, uint32_t address) {
227 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
228
229 switch (address & ~OFFSET_MASK) {
230 case BASE_BIOS:
231 break;
232 case BASE_WORKING_RAM:
233 return ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
234 case BASE_WORKING_IRAM:
235 return ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
236 case BASE_IO:
237 break;
238 case BASE_PALETTE_RAM:
239 break;
240 case BASE_VRAM:
241 break;
242 case BASE_OAM:
243 break;
244 case BASE_CART0:
245 case BASE_CART0_EX:
246 case BASE_CART1:
247 case BASE_CART1_EX:
248 case BASE_CART2:
249 case BASE_CART2_EX:
250 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
251 return ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
252 }
253 case BASE_CART_SRAM:
254 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
255 GBASavedataInitSRAM(&gbaMemory->savedata);
256 }
257 return gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
258 default:
259 break;
260 }
261
262 return 0;
263}
264
265uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address) {
266 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
267
268 switch (address & ~OFFSET_MASK) {
269 case BASE_BIOS:
270 break;
271 case BASE_WORKING_RAM:
272 return ((uint8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
273 break;
274 case BASE_WORKING_IRAM:
275 return ((uint8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
276 break;
277 case BASE_IO:
278 return (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
279 case BASE_PALETTE_RAM:
280 break;
281 case BASE_VRAM:
282 break;
283 case BASE_OAM:
284 break;
285 case BASE_CART0:
286 case BASE_CART0_EX:
287 case BASE_CART1:
288 case BASE_CART1_EX:
289 case BASE_CART2:
290 case BASE_CART2_EX:
291 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
292 return ((uint8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
293 }
294 case BASE_CART_SRAM:
295 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
296 GBASavedataInitSRAM(&gbaMemory->savedata);
297 }
298 return gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
299 default:
300 break;
301 }
302
303 return 0;
304}
305
306void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value) {
307 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
308
309 switch (address & ~OFFSET_MASK) {
310 case BASE_WORKING_RAM:
311 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
312 break;
313 case BASE_WORKING_IRAM:
314 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
315 break;
316 case BASE_IO:
317 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
318 break;
319 case BASE_PALETTE_RAM:
320 ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2] = value;
321 break;
322 case BASE_VRAM:
323 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
324 ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2] = value;
325 }
326 break;
327 case BASE_OAM:
328 ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2] = value;
329 break;
330 case BASE_CART0:
331 break;
332 case BASE_CART_SRAM:
333 break;
334 default:
335 break;
336 }
337}
338
339void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value) {
340 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
341
342 switch (address & ~OFFSET_MASK) {
343 case BASE_WORKING_RAM:
344 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
345 break;
346 case BASE_WORKING_IRAM:
347 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
348 break;
349 case BASE_IO:
350 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
351 break;
352 case BASE_PALETTE_RAM:
353 gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1] = value;
354 break;
355 case BASE_VRAM:
356 if ((address & OFFSET_MASK) < SIZE_VRAM) {
357 gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1] = value;
358 }
359 break;
360 case BASE_OAM:
361 gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1] = value;
362 break;
363 case BASE_CART0:
364 break;
365 case BASE_CART2_EX:
366 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
367 GBASavedataInitEEPROM(&gbaMemory->savedata);
368 }
369 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
370 break;
371 case BASE_CART_SRAM:
372 break;
373 default:
374 break;
375 }
376}
377
378void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value) {
379 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
380
381 switch (address & ~OFFSET_MASK) {
382 case BASE_WORKING_RAM:
383 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
384 break;
385 case BASE_WORKING_IRAM:
386 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
387 break;
388 case BASE_IO:
389 break;
390 case BASE_PALETTE_RAM:
391 break;
392 case BASE_VRAM:
393 break;
394 case BASE_OAM:
395 break;
396 case BASE_CART0:
397 break;
398 case BASE_CART_SRAM:
399 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
400 if (address == SAVEDATA_FLASH_BASE) {
401 GBASavedataInitFlash(&gbaMemory->savedata);
402 } else {
403 GBASavedataInitSRAM(&gbaMemory->savedata);
404 }
405 }
406 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
407 GBASavedataWriteFlash(&gbaMemory->savedata, value);
408 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
409 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
410 }
411 break;
412 default:
413 break;
414 }
415}
416
417void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
418 int sram = parameters & 0x0003;
419 int ws0 = (parameters & 0x000C) >> 2;
420 int ws0seq = (parameters & 0x0010) >> 4;
421 int ws1 = (parameters & 0x0060) >> 5;
422 int ws1seq = (parameters & 0x0080) >> 7;
423 int ws2 = (parameters & 0x0300) >> 8;
424 int ws2seq = (parameters & 0x0400) >> 10;
425 int prefetch = parameters & 0x4000;
426
427 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
428 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
429 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
430 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
431
432 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
433 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
434 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
435
436 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
437 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
438 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
439
440 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
441 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
442 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
443
444 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0 + 1] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
445 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1 + 1] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
446 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2 + 1] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
447
448 memory->d.activePrefetchCycles32 = memory->waitstates32[memory->activeRegion];
449 memory->d.activePrefetchCycles16 = memory->waitstates16[memory->activeRegion];
450}
451
452int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
453 struct GBADMA* dma;
454 int32_t test = INT_MAX;
455
456 dma = &memory->dma[0];
457 dma->nextIRQ -= cycles;
458 if (dma->enable && dma->doIrq && dma->nextIRQ) {
459 if (dma->nextIRQ <= 0) {
460 dma->nextIRQ = INT_MAX;
461 GBARaiseIRQ(memory->p, IRQ_DMA0);
462 } else if (dma->nextIRQ < test) {
463 test = dma->nextIRQ;
464 }
465 }
466
467 dma = &memory->dma[1];
468 dma->nextIRQ -= cycles;
469 if (dma->enable && dma->doIrq && dma->nextIRQ) {
470 if (dma->nextIRQ <= 0) {
471 dma->nextIRQ = INT_MAX;
472 GBARaiseIRQ(memory->p, IRQ_DMA1);
473 } else if (dma->nextIRQ < test) {
474 test = dma->nextIRQ;
475 }
476 }
477
478 dma = &memory->dma[2];
479 dma->nextIRQ -= cycles;
480 if (dma->enable && dma->doIrq && dma->nextIRQ) {
481 if (dma->nextIRQ <= 0) {
482 dma->nextIRQ = INT_MAX;
483 GBARaiseIRQ(memory->p, IRQ_DMA2);
484 } else if (dma->nextIRQ < test) {
485 test = dma->nextIRQ;
486 }
487 }
488
489 dma = &memory->dma[3];
490 dma->nextIRQ -= cycles;
491 if (dma->enable && dma->doIrq && dma->nextIRQ) {
492 if (dma->nextIRQ <= 0) {
493 dma->nextIRQ = INT_MAX;
494 GBARaiseIRQ(memory->p, IRQ_DMA3);
495 } else if (dma->nextIRQ < test) {
496 test = dma->nextIRQ;
497 }
498 }
499
500 return test;
501}
502
503void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
504 memory->dma[dma].source = address & 0xFFFFFFFE;
505}
506
507void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
508 memory->dma[dma].dest = address & 0xFFFFFFFE;
509}
510
511void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
512 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
513}
514
515uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
516 struct GBADMA* currentDma = &memory->dma[dma];
517 int wasEnabled = currentDma->enable;
518 currentDma->packed = control;
519 currentDma->nextIRQ = 0;
520
521 if (currentDma->drq) {
522 GBALog(GBA_LOG_STUB, "DRQ not implemented");
523 }
524
525 if (!wasEnabled && currentDma->enable) {
526 currentDma->nextSource = currentDma->source;
527 currentDma->nextDest = currentDma->dest;
528 currentDma->nextCount = currentDma->count;
529 GBAMemoryScheduleDMA(memory, dma, currentDma);
530 }
531 // If the DMA has already occurred, this value might have changed since the function started
532 return currentDma->packed;
533};
534
535void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
536 switch (info->timing) {
537 case DMA_TIMING_NOW:
538 GBAMemoryServiceDMA(memory, number, info);
539 break;
540 case DMA_TIMING_HBLANK:
541 // Handled implicitly
542 break;
543 case DMA_TIMING_VBLANK:
544 // Handled implicitly
545 break;
546 case DMA_TIMING_CUSTOM:
547 switch (number) {
548 case 0:
549 GBALog(GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
550 break;
551 case 1:
552 case 2:
553 //this.cpu.irq.audio.scheduleFIFODma(number, info);
554 break;
555 case 3:
556 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
557 break;
558 }
559 }
560}
561
562void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
563 struct GBADMA* dma;
564 int i;
565 for (i = 0; i < 4; ++i) {
566 dma = &memory->dma[i];
567 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
568 GBAMemoryServiceDMA(memory, i, dma);
569 }
570 }
571}
572
573void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
574 struct GBADMA* dma;
575 int i;
576 for (i = 0; i < 4; ++i) {
577 dma = &memory->dma[i];
578 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
579 GBAMemoryServiceDMA(memory, i, dma);
580 }
581 }
582}
583
584void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
585 if (!info->enable) {
586 // There was a DMA scheduled that got canceled
587 return;
588 }
589
590 uint32_t width = info->width ? 4 : 2;
591 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
592 int destOffset = DMA_OFFSET[info->dstControl] * width;
593 int32_t wordsRemaining = info->nextCount;
594 uint32_t source = info->nextSource;
595 uint32_t dest = info->nextDest;
596 uint32_t sourceRegion = source >> BASE_OFFSET;
597 uint32_t destRegion = dest >> BASE_OFFSET;
598
599 if (width == 4) {
600 int32_t word;
601 source &= 0xFFFFFFFC;
602 dest &= 0xFFFFFFFC;
603 while (wordsRemaining--) {
604 word = GBALoad32(&memory->d, source);
605 GBAStore32(&memory->d, dest, word);
606 source += sourceOffset;
607 dest += destOffset;
608 }
609 } else {
610 uint16_t word;
611 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
612 while (wordsRemaining--) {
613 word = GBASavedataReadEEPROM(&memory->savedata);
614 GBAStore16(&memory->d, dest, word);
615 source += sourceOffset;
616 dest += destOffset;
617 }
618 } else if (destRegion == REGION_CART2_EX) {
619 if (memory->savedata.type != SAVEDATA_EEPROM) {
620 GBASavedataInitEEPROM(&memory->savedata);
621 }
622 while (wordsRemaining) {
623 word = GBALoadU16(&memory->d, source);
624 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
625 source += sourceOffset;
626 dest += destOffset;
627 --wordsRemaining;
628 }
629 } else {
630 while (wordsRemaining--) {
631 word = GBALoadU16(&memory->d, source);
632 GBAStore16(&memory->d, dest, word);
633 source += sourceOffset;
634 dest += destOffset;
635 }
636 }
637 }
638
639 if (info->doIrq) {
640 info->nextIRQ = memory->p->cpu.cycles + 2;
641 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
642 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
643 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
644 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
645 }
646
647 info->nextSource = source;
648 info->nextDest = dest;
649 info->nextCount = wordsRemaining;
650
651 if (!info->repeat) {
652 info->enable = 0;
653
654 // Clear the enable bit in memory
655 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
656 } else {
657 info->nextCount = info->count;
658 if (info->dstControl == DMA_INCREMENT_RELOAD) {
659 info->nextDest = info->dest;
660 }
661 GBAMemoryScheduleDMA(memory, number, info);
662 }
663}