src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 cpu->cpsr.n = ARM_SIGN(D); \
194 cpu->cpsr.z = !(D); \
195 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
196 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
197 }
198
199#define ARM_SUBTRACTION_S(M, N, D) \
200 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
201 cpu->cpsr = cpu->spsr; \
202 _ARMReadCPSR(cpu); \
203 } else { \
204 cpu->cpsr.n = ARM_SIGN(D); \
205 cpu->cpsr.z = !(D); \
206 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
207 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
208 }
209
210#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
211 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
212 cpu->cpsr = cpu->spsr; \
213 _ARMReadCPSR(cpu); \
214 } else { \
215 cpu->cpsr.n = ARM_SIGN(D); \
216 cpu->cpsr.z = !(D); \
217 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
218 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
219 }
220
221#define ARM_NEUTRAL_S(M, N, D) \
222 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
223 cpu->cpsr = cpu->spsr; \
224 _ARMReadCPSR(cpu); \
225 } else { \
226 cpu->cpsr.n = ARM_SIGN(D); \
227 cpu->cpsr.z = !(D); \
228 cpu->cpsr.c = cpu->shifterCarryOut; \
229 }
230
231#define ARM_NEUTRAL_HI_S(DLO, DHI) \
232 cpu->cpsr.n = ARM_SIGN(DHI); \
233 cpu->cpsr.z = !((DHI) | (DLO));
234
235#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
236#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
237#define ADDR_MODE_2_ADDRESS (address)
238#define ADDR_MODE_2_RN (cpu->gprs[rn])
239#define ADDR_MODE_2_RM (cpu->gprs[rm])
240#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
241#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
242#define ADDR_MODE_2_WRITEBACK(ADDR) \
243 cpu->gprs[rn] = ADDR; \
244 if (UNLIKELY(rn == ARM_PC)) { \
245 ARM_WRITE_PC; \
246 }
247
248#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
249#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
250#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
251#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
252
253#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
254#define ADDR_MODE_3_RN ADDR_MODE_2_RN
255#define ADDR_MODE_3_RM ADDR_MODE_2_RM
256#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
257#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
258#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
259#define ADDR_MODE_3_WRITEBACK_64(ADDR) ADDR_MODE_2_WRITEBACK(ADDR + 4)
260
261#define ADDR_MODE_4_WRITEBACK_LDM \
262 if (!((1 << rn) & rs)) { \
263 cpu->gprs[rn] = address; \
264 }
265
266#define ADDR_MODE_4_WRITEBACK_LDMv5 \
267 if (!((1 << rn) & rs) || !(((1 << rn) - 1) & rs)) { \
268 cpu->gprs[rn] = address; \
269 }
270
271#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
272
273#define ARM_LOAD_POST_BODY \
274 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
275 if (rd == ARM_PC) { \
276 ARM_WRITE_PC; \
277 }
278
279#define ARM_LOAD_POST_BODY_v5 \
280 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
281 if (rd == ARM_PC) { \
282 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001); \
283 cpu->gprs[ARM_PC] &= 0xFFFFFFFE; \
284 if (cpu->executionMode == MODE_THUMB) { \
285 THUMB_WRITE_PC; \
286 } else { \
287 ARM_WRITE_PC; \
288 } \
289 }
290
291#define ARM_STORE_POST_BODY \
292 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
293
294#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
295 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
296 int currentCycles = ARM_PREFETCH_CYCLES; \
297 BODY; \
298 cpu->cycles += currentCycles; \
299 }
300
301#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
302 DEFINE_INSTRUCTION_ARM(NAME, \
303 int rd = (opcode >> 12) & 0xF; \
304 int rn = (opcode >> 16) & 0xF; \
305 UNUSED(rn); \
306 SHIFTER(cpu, opcode); \
307 BODY; \
308 S_BODY; \
309 if (rd == ARM_PC) { \
310 if (cpu->executionMode == MODE_ARM) { \
311 ARM_WRITE_PC; \
312 } else { \
313 THUMB_WRITE_PC; \
314 } \
315 })
316
317#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
322 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
323 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
324 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
328
329#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
331 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
332 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
334 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
335
336#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
337 DEFINE_INSTRUCTION_ARM(NAME, \
338 int rd = (opcode >> 16) & 0xF; \
339 int rs = (opcode >> 8) & 0xF; \
340 int rm = opcode & 0xF; \
341 if (rd == ARM_PC) { \
342 return; \
343 } \
344 ARM_WAIT_MUL(cpu->gprs[rs]); \
345 BODY; \
346 S_BODY; \
347 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
348
349#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
350 DEFINE_INSTRUCTION_ARM(NAME, \
351 int rd = (opcode >> 12) & 0xF; \
352 int rdHi = (opcode >> 16) & 0xF; \
353 int rs = (opcode >> 8) & 0xF; \
354 int rm = opcode & 0xF; \
355 if (rdHi == ARM_PC || rd == ARM_PC) { \
356 return; \
357 } \
358 currentCycles += cpu->memory.stall(cpu, WAIT); \
359 BODY; \
360 S_BODY; \
361 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
362
363#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
364 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
365 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
366
367#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
368 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
369 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
370
371#define DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME, BODY) \
372 DEFINE_INSTRUCTION_ARM(NAME, \
373 int rd = (opcode >> 16) & 0xF; \
374 int rs = (opcode >> 8) & 0xF; \
375 int rn = (opcode >> 12) & 0xF; \
376 int rm = opcode & 0xF; \
377 UNUSED(rn); \
378 if (rd == ARM_PC) { \
379 return; \
380 } \
381 /* TODO: Timing */ \
382 int32_t x; \
383 int32_t y; \
384 BODY; \
385 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
386
387#define DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(NAME, BODY) \
388 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BB, \
389 x = ARM_SXT_16(cpu->gprs[rm]); \
390 y = ARM_SXT_16(cpu->gprs[rs]); \
391 BODY) \
392 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BT, \
393 x = ARM_SXT_16(cpu->gprs[rm]); \
394 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
395 BODY) \
396 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TB, \
397 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
398 y = ARM_SXT_16(cpu->gprs[rs]); \
399 BODY) \
400 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TT, \
401 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
402 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
403 BODY)
404
405#define DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(NAME, BODY) \
406 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## B, \
407 UNUSED(x); \
408 y = ARM_SXT_16(cpu->gprs[rs]); \
409 BODY) \
410 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## T, \
411 UNUSED(x); \
412 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
413 BODY) \
414
415#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
416 DEFINE_INSTRUCTION_ARM(NAME, \
417 uint32_t address; \
418 int rn = (opcode >> 16) & 0xF; \
419 int rd = (opcode >> 12) & 0xF; \
420 int rm = opcode & 0xF; \
421 UNUSED(rm); \
422 address = ADDRESS; \
423 WRITEBACK; \
424 BODY;)
425
426#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
427 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
428 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
429 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
430 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
431 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
432 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
433
434#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
435 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
436 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
437 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
438 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
439 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
440 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
441 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
442 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
443 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
444 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
445
446#define DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, WRITEBACK) \
447 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
448 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
449 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
450 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
451 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
456 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
457 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
458 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
459
460#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, ADDR_MODE_3_WRITEBACK)
461#define DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(NAME, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, ADDR_MODE_3_WRITEBACK_64)
462
463#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
465 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
466
467#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
468 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
469 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
470 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
471 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
472 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
473 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
474
475#define ARM_MS_PRE \
476 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
477 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
478
479#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
480
481#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
482 DEFINE_INSTRUCTION_ARM(NAME, \
483 int rn = (opcode >> 16) & 0xF; \
484 int rs = opcode & 0x0000FFFF; \
485 uint32_t address = cpu->gprs[rn]; \
486 S_PRE; \
487 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
488 S_POST; \
489 POST_BODY; \
490 WRITEBACK;)
491
492
493#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
494 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
495 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
496 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
497 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
498 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
499 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
500 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
501 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
502
503#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
504 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
505 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
506 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
507 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
508 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
509 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
510 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
511 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
512 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
513
514// Begin ALU definitions
515
516DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
517 int32_t n = cpu->gprs[rn];
518 cpu->gprs[rd] = n + cpu->shifterOperand;)
519
520DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
521 int32_t n = cpu->gprs[rn];
522 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
523
524DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
525 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
526
527DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
528 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
529
530DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
531 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
532
533DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
534 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
535
536DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
537 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
538
539DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
540 cpu->gprs[rd] = cpu->shifterOperand;)
541
542DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
543 cpu->gprs[rd] = ~cpu->shifterOperand;)
544
545DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
546 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
547
548DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
549 int32_t n = cpu->gprs[rn];
550 cpu->gprs[rd] = cpu->shifterOperand - n;)
551
552DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
553 int32_t n = cpu->gprs[rn];
554 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
555
556DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
557 int32_t n = cpu->gprs[rn];
558 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
559
560DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
561 int32_t n = cpu->gprs[rn];
562 cpu->gprs[rd] = n - cpu->shifterOperand;)
563
564DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
565 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
566
567DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
568 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
569
570// End ALU definitions
571
572// Begin multiply definitions
573
574DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
575DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
576
577DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
578 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
579 int32_t dm = cpu->gprs[rd];
580 int32_t dn = d;
581 cpu->gprs[rd] = dm + dn;
582 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
583 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
584
585DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMLA,
586 int32_t dn = cpu->gprs[rn]; \
587 int32_t d = x * y; \
588 cpu->gprs[rd] = d + dn; \
589 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
590
591DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMUL, cpu->gprs[rd] = x * y;)
592
593DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMLAW,
594 int32_t dn = cpu->gprs[rn]; \
595 int32_t d = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16; \
596 cpu->gprs[rd] = d + dn; \
597 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
598
599DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMULW, cpu->gprs[rd] = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16;)
600
601DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
602 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
603 cpu->gprs[rd] = d;
604 cpu->gprs[rdHi] = d >> 32;,
605 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
606
607DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
608 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
609 int32_t dm = cpu->gprs[rd];
610 int32_t dn = d;
611 cpu->gprs[rd] = dm + dn;
612 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
613 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
614
615DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
616 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
617 cpu->gprs[rd] = d;
618 cpu->gprs[rdHi] = d >> 32;,
619 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
620
621// End multiply definitions
622
623// Begin load/store definitions
624
625DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
626DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRv5, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY_v5;)
627DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
628DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(LDRD, cpu->gprs[rd & ~1] = cpu->memory.load32(cpu, address, ¤tCycles); cpu->gprs[rd | 1] = cpu->memory.load32(cpu, address + 4, ¤tCycles); ARM_LOAD_POST_BODY;)
629DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
630DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
631DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
632DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
633DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
634DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(STRD, cpu->memory.store32(cpu, address, cpu->gprs[rd & ~1], ¤tCycles); cpu->memory.store32(cpu, address + 4, cpu->gprs[rd | 1], ¤tCycles); ARM_STORE_POST_BODY;)
635DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
636
637DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
638 enum PrivilegeMode priv = cpu->privilegeMode;
639 ARMSetPrivilegeMode(cpu, MODE_USER);
640 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
641 ARMSetPrivilegeMode(cpu, priv);
642 cpu->gprs[rd] = r;
643 ARM_LOAD_POST_BODY;)
644
645DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
646 enum PrivilegeMode priv = cpu->privilegeMode;
647 ARMSetPrivilegeMode(cpu, MODE_USER);
648 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
649 ARMSetPrivilegeMode(cpu, priv);
650 cpu->gprs[rd] = r;
651 ARM_LOAD_POST_BODY;)
652
653DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
654 enum PrivilegeMode priv = cpu->privilegeMode;
655 int32_t r = cpu->gprs[rd];
656 ARMSetPrivilegeMode(cpu, MODE_USER);
657 cpu->memory.store8(cpu, address, r, ¤tCycles);
658 ARMSetPrivilegeMode(cpu, priv);
659 ARM_STORE_POST_BODY;)
660
661DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
662 enum PrivilegeMode priv = cpu->privilegeMode;
663 int32_t r = cpu->gprs[rd];
664 ARMSetPrivilegeMode(cpu, MODE_USER);
665 cpu->memory.store32(cpu, address, r, ¤tCycles);
666 ARMSetPrivilegeMode(cpu, priv);
667 ARM_STORE_POST_BODY;)
668
669DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
670 load,
671 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
672 if (rs & 0x8000) {
673 ARM_WRITE_PC;
674 })
675
676DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
677 load,
678 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
679 if (rs & 0x8000) {
680 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
681 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
682 if (cpu->executionMode == MODE_THUMB) {
683 THUMB_WRITE_PC;
684 } else {
685 ARM_WRITE_PC;
686
687 }
688 })
689
690DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
691 store,
692 ARM_STORE_POST_BODY;)
693
694DEFINE_INSTRUCTION_ARM(SWP,
695 int rm = opcode & 0xF;
696 int rd = (opcode >> 12) & 0xF;
697 int rn = (opcode >> 16) & 0xF;
698 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
699 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
700 cpu->gprs[rd] = d;)
701
702DEFINE_INSTRUCTION_ARM(SWPB,
703 int rm = opcode & 0xF;
704 int rd = (opcode >> 12) & 0xF;
705 int rn = (opcode >> 16) & 0xF;
706 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
707 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
708 cpu->gprs[rd] = d;)
709
710// End load/store definitions
711
712// Begin branch definitions
713
714DEFINE_INSTRUCTION_ARM(B,
715 int32_t offset = opcode << 8;
716 offset >>= 6;
717 cpu->gprs[ARM_PC] += offset;
718 ARM_WRITE_PC;)
719
720DEFINE_INSTRUCTION_ARM(BL,
721 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
722 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
723 cpu->gprs[ARM_PC] += immediate >> 6;
724 ARM_WRITE_PC;)
725
726DEFINE_INSTRUCTION_ARM(BX,
727 int rm = opcode & 0x0000000F;
728 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
729 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
730 if (cpu->executionMode == MODE_THUMB) {
731 THUMB_WRITE_PC;
732 } else {
733 ARM_WRITE_PC;
734
735 })
736
737DEFINE_INSTRUCTION_ARM(BLX,
738 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
739 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
740 cpu->gprs[ARM_PC] += (immediate >> 6) + ((opcode >> 23) & 2);
741 _ARMSetMode(cpu, MODE_THUMB);
742 THUMB_WRITE_PC;)
743
744DEFINE_INSTRUCTION_ARM(BLX2,
745 int rm = opcode & 0x0000000F;
746 int address = cpu->gprs[rm];
747 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
748 _ARMSetMode(cpu, address & 0x00000001);
749 cpu->gprs[ARM_PC] = address & 0xFFFFFFFE;
750 if (cpu->executionMode == MODE_THUMB) {
751 THUMB_WRITE_PC;
752 } else {
753 ARM_WRITE_PC;
754 })
755
756// End branch definitions
757
758// Begin coprocessor definitions
759
760#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
761 DEFINE_INSTRUCTION_ARM(NAME, \
762 int op1 = (opcode >> 21) & 7; \
763 int op2 = (opcode >> 5) & 7; \
764 int rd = (opcode >> 12) & 0xF; \
765 int cp = (opcode >> 8) & 0xF; \
766 int crn = (opcode >> 16) & 0xF; \
767 int crm = opcode & 0xF; \
768 UNUSED(op1); \
769 UNUSED(op2); \
770 UNUSED(rd); \
771 UNUSED(crn); \
772 UNUSED(crm); \
773 BODY;)
774
775DEFINE_COPROCESSOR_INSTRUCTION(MRC,
776 if (cp == 15 && cpu->irqh.readCP15) {
777 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
778 } else {
779 ARM_STUB;
780 })
781
782DEFINE_COPROCESSOR_INSTRUCTION(MCR,
783 if (cp == 15 && cpu->irqh.writeCP15) {
784 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
785 } else {
786 ARM_STUB;
787 })
788
789DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
790DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
791DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
792
793// Begin miscellaneous definitions
794
795DEFINE_INSTRUCTION_ARM(CLZ,
796 int rm = opcode & 0xF;
797 int rd = (opcode >> 12) & 0xF;
798 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
799
800DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
801DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
802
803DEFINE_INSTRUCTION_ARM(MSR,
804 int c = opcode & 0x00010000;
805 int f = opcode & 0x00080000;
806 int32_t operand = cpu->gprs[opcode & 0x0000000F];
807 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
808 if (mask & PSR_USER_MASK) {
809 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
810 }
811 if (mask & PSR_STATE_MASK) {
812 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
813 }
814 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
815 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
816 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
817 }
818 _ARMReadCPSR(cpu);
819 if (cpu->executionMode == MODE_THUMB) {
820 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
821 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
822 } else {
823 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
824 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
825 })
826
827DEFINE_INSTRUCTION_ARM(MSRR,
828 int c = opcode & 0x00010000;
829 int f = opcode & 0x00080000;
830 int32_t operand = cpu->gprs[opcode & 0x0000000F];
831 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
832 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
833 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
834
835DEFINE_INSTRUCTION_ARM(MRS, \
836 int rd = (opcode >> 12) & 0xF; \
837 cpu->gprs[rd] = cpu->cpsr.packed;)
838
839DEFINE_INSTRUCTION_ARM(MRSR, \
840 int rd = (opcode >> 12) & 0xF; \
841 cpu->gprs[rd] = cpu->spsr.packed;)
842
843DEFINE_INSTRUCTION_ARM(MSRI,
844 int c = opcode & 0x00010000;
845 int f = opcode & 0x00080000;
846 int rotate = (opcode & 0x00000F00) >> 7;
847 int32_t operand = ROR(opcode & 0x000000FF, rotate);
848 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
849 if (mask & PSR_USER_MASK) {
850 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
851 }
852 if (mask & PSR_STATE_MASK) {
853 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
854 }
855 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
856 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
857 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
858 }
859 _ARMReadCPSR(cpu);
860 if (cpu->executionMode == MODE_THUMB) {
861 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
862 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
863 } else {
864 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
865 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
866 })
867
868DEFINE_INSTRUCTION_ARM(MSRRI,
869 int c = opcode & 0x00010000;
870 int f = opcode & 0x00080000;
871 int rotate = (opcode & 0x00000F00) >> 7;
872 int32_t operand = ROR(opcode & 0x000000FF, rotate);
873 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
874 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
875 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
876
877DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
878
879const ARMInstruction _armv4Table[0x1000] = {
880 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
881};
882
883const ARMInstruction _armv5Table[0x1000] = {
884 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
885};
886
887const ARMInstruction _armv4FTable[0x1000] = {
888 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 4)
889};
890
891const ARMInstruction _armv5FTable[0x1000] = {
892 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 5)
893};