src/lr35902/isa-lr35902.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-lr35902.h"
7
8#include "lr35902/emitter-lr35902.h"
9#include "lr35902/lr35902.h"
10
11#define DEFINE_INSTRUCTION_LR35902(NAME, BODY) \
12 static void _LR35902Instruction ## NAME (struct LR35902Core* cpu) { \
13 UNUSED(cpu); \
14 BODY; \
15 }
16
17DEFINE_INSTRUCTION_LR35902(NOP,);
18
19#define DEFINE_CONDITIONAL_INSTRUCTION_LR35902(NAME) \
20 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(, true) \
21 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(C, cpu->f.c) \
22 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(Z, cpu->f.z) \
23 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(NC, !cpu->f.c) \
24 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(NZ, !cpu->f.z)
25
26DEFINE_INSTRUCTION_LR35902(JPFinish,
27 if (cpu->condition) {
28 cpu->pc = (cpu->bus << 8) | cpu->index;
29 cpu->memory.setActiveRegion(cpu, cpu->pc);
30 cpu->executionState = LR35902_CORE_STALL;
31 })
32
33DEFINE_INSTRUCTION_LR35902(JPDelay,
34 cpu->executionState = LR35902_CORE_READ_PC;
35 cpu->instruction = _LR35902InstructionJPFinish;
36 cpu->index = cpu->bus;)
37
38#define DEFINE_JP_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
39 DEFINE_INSTRUCTION_LR35902(JP ## CONDITION_NAME, \
40 cpu->executionState = LR35902_CORE_READ_PC; \
41 cpu->instruction = _LR35902InstructionJPDelay; \
42 cpu->condition = CONDITION;)
43
44DEFINE_CONDITIONAL_INSTRUCTION_LR35902(JP);
45
46DEFINE_INSTRUCTION_LR35902(JPHL,
47 cpu->pc = LR35902ReadHL(cpu);
48 cpu->memory.setActiveRegion(cpu, cpu->pc);)
49
50DEFINE_INSTRUCTION_LR35902(JRFinish,
51 if (cpu->condition) {
52 cpu->pc += (int8_t) cpu->bus;
53 cpu->memory.setActiveRegion(cpu, cpu->pc);
54 cpu->executionState = LR35902_CORE_STALL;
55 })
56
57#define DEFINE_JR_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
58 DEFINE_INSTRUCTION_LR35902(JR ## CONDITION_NAME, \
59 cpu->executionState = LR35902_CORE_READ_PC; \
60 cpu->instruction = _LR35902InstructionJRFinish; \
61 cpu->condition = CONDITION;)
62
63DEFINE_CONDITIONAL_INSTRUCTION_LR35902(JR);
64
65DEFINE_INSTRUCTION_LR35902(CALLFinish,
66 if (cpu->condition) {
67 cpu->pc = (cpu->bus << 8) | cpu->index;
68 cpu->memory.setActiveRegion(cpu, cpu->pc);
69 cpu->executionState = LR35902_CORE_STALL;
70 })
71
72DEFINE_INSTRUCTION_LR35902(CALLUpdatePC,
73 cpu->executionState = LR35902_CORE_READ_PC;
74 cpu->index = cpu->bus;
75 cpu->instruction = _LR35902InstructionCALLFinish;)
76
77DEFINE_INSTRUCTION_LR35902(CALLUpdateSPL,
78 cpu->executionState = LR35902_CORE_READ_PC; \
79 cpu->instruction = _LR35902InstructionCALLUpdatePC;)
80
81DEFINE_INSTRUCTION_LR35902(CALLUpdateSPH,
82 cpu->index = cpu->sp + 1;
83 cpu->bus = (cpu->pc + 2) >> 8;
84 cpu->executionState = LR35902_CORE_MEMORY_STORE;
85 cpu->instruction = _LR35902InstructionCALLUpdateSPL;)
86
87#define DEFINE_CALL_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
88 DEFINE_INSTRUCTION_LR35902(CALL ## CONDITION_NAME, \
89 cpu->condition = CONDITION; \
90 if (CONDITION) { \
91 cpu->sp -= 2; /* TODO: Atomic incrementing? */ \
92 cpu->index = cpu->sp; \
93 cpu->bus = cpu->pc + 2; \
94 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
95 cpu->instruction = _LR35902InstructionCALLUpdateSPH; \
96 } else { \
97 cpu->executionState = LR35902_CORE_READ_PC; \
98 cpu->instruction = _LR35902InstructionCALLUpdatePC; \
99 })
100
101DEFINE_CONDITIONAL_INSTRUCTION_LR35902(CALL)
102
103DEFINE_INSTRUCTION_LR35902(RETUpdateSPL,
104 cpu->pc |= cpu->bus << 8;
105 cpu->sp += 2; /* TODO: Atomic incrementing? */
106 cpu->memory.setActiveRegion(cpu, cpu->pc);
107 cpu->executionState = LR35902_CORE_STALL;)
108
109DEFINE_INSTRUCTION_LR35902(RETUpdateSPH,
110 if (cpu->condition) {
111 cpu->index = cpu->sp + 1;
112 cpu->pc = cpu->bus;
113 cpu->executionState = LR35902_CORE_MEMORY_LOAD;
114 cpu->instruction = _LR35902InstructionRETUpdateSPL;
115 })
116
117#define DEFINE_RET_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
118 DEFINE_INSTRUCTION_LR35902(RET ## CONDITION_NAME, \
119 cpu->condition = CONDITION; \
120 cpu->index = cpu->sp; \
121 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
122 cpu->instruction = _LR35902InstructionRETUpdateSPH;)
123
124DEFINE_CONDITIONAL_INSTRUCTION_LR35902(RET)
125
126#define DEFINE_AND_INSTRUCTION_LR35902(NAME, OPERAND) \
127 DEFINE_INSTRUCTION_LR35902(AND ## NAME, \
128 cpu->a &= OPERAND; \
129 cpu->f.z = !cpu->a; \
130 cpu->f.n = 0; \
131 cpu->f.c = 0; \
132 cpu->f.h = 1;)
133
134#define DEFINE_XOR_INSTRUCTION_LR35902(NAME, OPERAND) \
135 DEFINE_INSTRUCTION_LR35902(XOR ## NAME, \
136 cpu->a ^= OPERAND; \
137 cpu->f.z = !cpu->a; \
138 cpu->f.n = 0; \
139 cpu->f.c = 0; \
140 cpu->f.h = 0;)
141
142#define DEFINE_OR_INSTRUCTION_LR35902(NAME, OPERAND) \
143 DEFINE_INSTRUCTION_LR35902(OR ## NAME, \
144 cpu->a |= OPERAND; \
145 cpu->f.z = !cpu->a; \
146 cpu->f.n = 0; \
147 cpu->f.c = 0; \
148 cpu->f.h = 0;)
149
150#define DEFINE_CP_INSTRUCTION_LR35902(NAME, OPERAND) \
151 DEFINE_INSTRUCTION_LR35902(CP ## NAME, \
152 int diff = cpu->a - OPERAND; \
153 cpu->f.n = 1; \
154 cpu->f.z = !diff; \
155 cpu->f.c = diff < 0; \
156 /* TODO: Find explanation of H flag */)
157
158#define DEFINE_LDB__INSTRUCTION_LR35902(NAME, OPERAND) \
159 DEFINE_INSTRUCTION_LR35902(LDB_ ## NAME, \
160 cpu->b = OPERAND;)
161
162#define DEFINE_LDC__INSTRUCTION_LR35902(NAME, OPERAND) \
163 DEFINE_INSTRUCTION_LR35902(LDC_ ## NAME, \
164 cpu->c = OPERAND;)
165
166#define DEFINE_LDD__INSTRUCTION_LR35902(NAME, OPERAND) \
167 DEFINE_INSTRUCTION_LR35902(LDD_ ## NAME, \
168 cpu->d = OPERAND;)
169
170#define DEFINE_LDE__INSTRUCTION_LR35902(NAME, OPERAND) \
171 DEFINE_INSTRUCTION_LR35902(LDE_ ## NAME, \
172 cpu->e = OPERAND;)
173
174#define DEFINE_LDH__INSTRUCTION_LR35902(NAME, OPERAND) \
175 DEFINE_INSTRUCTION_LR35902(LDH_ ## NAME, \
176 cpu->h = OPERAND;)
177
178#define DEFINE_LDL__INSTRUCTION_LR35902(NAME, OPERAND) \
179 DEFINE_INSTRUCTION_LR35902(LDL_ ## NAME, \
180 cpu->l = OPERAND;)
181
182#define DEFINE_LDHL__INSTRUCTION_LR35902(NAME, OPERAND) \
183 DEFINE_INSTRUCTION_LR35902(LDHL_ ## NAME, \
184 cpu->bus = OPERAND; \
185 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
186 cpu->instruction = _LR35902InstructionLDHL_Bus;)
187
188#define DEFINE_LDA__INSTRUCTION_LR35902(NAME, OPERAND) \
189 DEFINE_INSTRUCTION_LR35902(LDA_ ## NAME, \
190 cpu->a = OPERAND;)
191
192#define DEFINE_ALU_INSTRUCTION_LR35902_NOHL(NAME) \
193 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(A, cpu->a); \
194 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(B, cpu->b); \
195 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(C, cpu->c); \
196 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(D, cpu->d); \
197 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(E, cpu->e); \
198 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(H, cpu->h); \
199 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(L, cpu->l);
200
201DEFINE_INSTRUCTION_LR35902(LDHL_Bus, \
202 cpu->index = LR35902ReadHL(cpu); \
203 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
204 cpu->instruction = _LR35902InstructionNOP;)
205
206DEFINE_INSTRUCTION_LR35902(LDHL_, \
207 cpu->executionState = LR35902_CORE_READ_PC; \
208 cpu->instruction = _LR35902InstructionLDHL_Bus;)
209
210#define DEFINE_ALU_INSTRUCTION_LR35902(NAME) \
211 DEFINE_ ## NAME ## _INSTRUCTION_LR35902(Bus, cpu->bus); \
212 DEFINE_INSTRUCTION_LR35902(NAME ## HL, \
213 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
214 cpu->index = LR35902ReadHL(cpu); \
215 cpu->instruction = _LR35902Instruction ## NAME ## Bus;) \
216 DEFINE_INSTRUCTION_LR35902(NAME, \
217 cpu->executionState = LR35902_CORE_READ_PC; \
218 cpu->instruction = _LR35902Instruction ## NAME ## Bus;) \
219 DEFINE_ALU_INSTRUCTION_LR35902_NOHL(NAME)
220
221DEFINE_ALU_INSTRUCTION_LR35902(AND);
222DEFINE_ALU_INSTRUCTION_LR35902(XOR);
223DEFINE_ALU_INSTRUCTION_LR35902(OR);
224DEFINE_ALU_INSTRUCTION_LR35902(CP);
225
226static void _LR35902InstructionLDB_Bus(struct LR35902Core*);
227static void _LR35902InstructionLDC_Bus(struct LR35902Core*);
228static void _LR35902InstructionLDD_Bus(struct LR35902Core*);
229static void _LR35902InstructionLDE_Bus(struct LR35902Core*);
230static void _LR35902InstructionLDH_Bus(struct LR35902Core*);
231static void _LR35902InstructionLDL_Bus(struct LR35902Core*);
232static void _LR35902InstructionLDHL_Bus(struct LR35902Core*);
233static void _LR35902InstructionLDA_Bus(struct LR35902Core*);
234
235DEFINE_ALU_INSTRUCTION_LR35902(LDB_);
236DEFINE_ALU_INSTRUCTION_LR35902(LDC_);
237DEFINE_ALU_INSTRUCTION_LR35902(LDD_);
238DEFINE_ALU_INSTRUCTION_LR35902(LDE_);
239DEFINE_ALU_INSTRUCTION_LR35902(LDH_);
240DEFINE_ALU_INSTRUCTION_LR35902(LDL_);
241DEFINE_ALU_INSTRUCTION_LR35902_NOHL(LDHL_);
242DEFINE_ALU_INSTRUCTION_LR35902(LDA_);
243
244DEFINE_INSTRUCTION_LR35902(LDBCDelay, \
245 cpu->c = cpu->bus; \
246 cpu->executionState = LR35902_CORE_READ_PC; \
247 cpu->instruction = _LR35902InstructionLDB_Bus;)
248
249DEFINE_INSTRUCTION_LR35902(LDBC, \
250 cpu->executionState = LR35902_CORE_READ_PC; \
251 cpu->instruction = _LR35902InstructionLDBCDelay;)
252
253DEFINE_INSTRUCTION_LR35902(LDBC_A, \
254 cpu->index = LR35902ReadBC(cpu); \
255 cpu->bus = cpu->a; \
256 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
257 cpu->instruction = _LR35902InstructionNOP;)
258
259DEFINE_INSTRUCTION_LR35902(LDDEDelay, \
260 cpu->e = cpu->bus; \
261 cpu->executionState = LR35902_CORE_READ_PC; \
262 cpu->instruction = _LR35902InstructionLDD_Bus;)
263
264DEFINE_INSTRUCTION_LR35902(LDDE, \
265 cpu->executionState = LR35902_CORE_READ_PC; \
266 cpu->instruction = _LR35902InstructionLDDEDelay;)
267
268DEFINE_INSTRUCTION_LR35902(LDDE_A, \
269 cpu->index = LR35902ReadDE(cpu); \
270 cpu->bus = cpu->a; \
271 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
272 cpu->instruction = _LR35902InstructionNOP;)
273
274DEFINE_INSTRUCTION_LR35902(LDHLDelay, \
275 cpu->l = cpu->bus; \
276 cpu->executionState = LR35902_CORE_READ_PC; \
277 cpu->instruction = _LR35902InstructionLDH_Bus;)
278
279DEFINE_INSTRUCTION_LR35902(LDHL, \
280 cpu->executionState = LR35902_CORE_READ_PC; \
281 cpu->instruction = _LR35902InstructionLDHLDelay;)
282
283DEFINE_INSTRUCTION_LR35902(LDSPFinish, cpu->sp |= cpu->bus << 8;)
284
285DEFINE_INSTRUCTION_LR35902(LDSPDelay, \
286 cpu->sp = cpu->bus; \
287 cpu->executionState = LR35902_CORE_READ_PC; \
288 cpu->instruction = _LR35902InstructionLDSPFinish;)
289
290DEFINE_INSTRUCTION_LR35902(LDSP, \
291 cpu->executionState = LR35902_CORE_READ_PC; \
292 cpu->instruction = _LR35902InstructionLDSPDelay;)
293
294DEFINE_INSTRUCTION_LR35902(LDIHLA, \
295 cpu->index = LR35902ReadHL(cpu); \
296 LR35902WriteHL(cpu, cpu->index + 1); \
297 cpu->bus = cpu->a; \
298 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
299 cpu->instruction = _LR35902InstructionNOP;)
300
301DEFINE_INSTRUCTION_LR35902(LDDHLA, \
302 cpu->index = LR35902ReadHL(cpu); \
303 LR35902WriteHL(cpu, cpu->index - 1); \
304 cpu->bus = cpu->a; \
305 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
306 cpu->instruction = _LR35902InstructionNOP;)
307
308DEFINE_INSTRUCTION_LR35902(LDIAFinish, \
309 cpu->index |= cpu->bus << 8;
310 cpu->bus = cpu->a; \
311 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
312 cpu->instruction = _LR35902InstructionNOP;)
313
314DEFINE_INSTRUCTION_LR35902(LDIADelay, \
315 cpu->index = cpu->bus;
316 cpu->executionState = LR35902_CORE_READ_PC; \
317 cpu->instruction = _LR35902InstructionLDIAFinish;)
318
319DEFINE_INSTRUCTION_LR35902(LDIA, \
320 cpu->executionState = LR35902_CORE_READ_PC; \
321 cpu->instruction = _LR35902InstructionLDIADelay;)
322
323DEFINE_INSTRUCTION_LR35902(LDAIFinish, \
324 cpu->index |= cpu->bus << 8;
325 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
326 cpu->instruction = _LR35902InstructionLDA_Bus;)
327
328DEFINE_INSTRUCTION_LR35902(LDAIDelay, \
329 cpu->index = cpu->bus;
330 cpu->executionState = LR35902_CORE_READ_PC; \
331 cpu->instruction = _LR35902InstructionLDAIFinish;)
332
333DEFINE_INSTRUCTION_LR35902(LDAI, \
334 cpu->executionState = LR35902_CORE_READ_PC; \
335 cpu->instruction = _LR35902InstructionLDAIDelay;)
336
337DEFINE_INSTRUCTION_LR35902(LDAIOC, \
338 cpu->index = 0xFF00 | cpu->c; \
339 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
340 cpu->instruction = _LR35902InstructionLDA_Bus;)
341
342DEFINE_INSTRUCTION_LR35902(LDIOCA, \
343 cpu->index = 0xFF00 | cpu->c; \
344 cpu->bus = cpu->a; \
345 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
346 cpu->instruction = _LR35902InstructionNOP;)
347
348DEFINE_INSTRUCTION_LR35902(LDAIODelay, \
349 cpu->index = 0xFF00 | cpu->bus; \
350 cpu->executionState = LR35902_CORE_MEMORY_LOAD; \
351 cpu->instruction = _LR35902InstructionLDA_Bus;)
352
353DEFINE_INSTRUCTION_LR35902(LDAIO, \
354 cpu->executionState = LR35902_CORE_READ_PC; \
355 cpu->instruction = _LR35902InstructionLDAIODelay;)
356
357DEFINE_INSTRUCTION_LR35902(LDIOADelay, \
358 cpu->index = 0xFF00 | cpu->bus; \
359 cpu->bus = cpu->a; \
360 cpu->executionState = LR35902_CORE_MEMORY_STORE; \
361 cpu->instruction = _LR35902InstructionNOP;)
362
363DEFINE_INSTRUCTION_LR35902(LDIOA, \
364 cpu->executionState = LR35902_CORE_READ_PC; \
365 cpu->instruction = _LR35902InstructionLDIOADelay;)
366
367#define DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(REG) \
368 DEFINE_INSTRUCTION_LR35902(INC ## REG, \
369 uint16_t reg = LR35902Read ## REG (cpu); \
370 LR35902Write ## REG (cpu, reg + 1); \
371 cpu->executionState = LR35902_CORE_STALL;) \
372 DEFINE_INSTRUCTION_LR35902(DEC ## REG, \
373 uint16_t reg = LR35902Read ## REG (cpu); \
374 LR35902Write ## REG (cpu, reg - 1); \
375 cpu->executionState = LR35902_CORE_STALL;)
376
377DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(BC);
378DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(DE);
379DEFINE_INCDEC_WIDE_INSTRUCTION_LR35902(HL);
380
381
382#define DEFINE_INC_INSTRUCTION_LR35902(NAME, OPERAND) \
383 DEFINE_INSTRUCTION_LR35902(INC ## NAME, \
384 int diff = OPERAND + 1; \
385 OPERAND = diff; \
386 cpu->f.n = 0; \
387 cpu->f.z = !diff; \
388 /* TODO: Find explanation of H flag */)
389
390#define DEFINE_DEC_INSTRUCTION_LR35902(NAME, OPERAND) \
391 DEFINE_INSTRUCTION_LR35902(DEC ## NAME, \
392 int diff = OPERAND - 1; \
393 OPERAND = diff; \
394 cpu->f.n = 1; \
395 cpu->f.z = !diff; \
396 /* TODO: Find explanation of H flag */)
397
398DEFINE_ALU_INSTRUCTION_LR35902_NOHL(INC);
399DEFINE_ALU_INSTRUCTION_LR35902_NOHL(DEC);
400
401DEFINE_INSTRUCTION_LR35902(INC_HLDelay,
402 int diff = cpu->bus + 1;
403 cpu->bus = diff;
404 cpu->f.n = 0;
405 cpu->f.z = !diff;
406 /* TODO: Find explanation of H flag */
407 cpu->instruction = _LR35902InstructionNOP;
408 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
409
410DEFINE_INSTRUCTION_LR35902(INC_HL,
411 cpu->index = LR35902ReadHL(cpu);
412 cpu->instruction = _LR35902InstructionINC_HLDelay;
413 cpu->executionState = LR35902_CORE_MEMORY_LOAD;)
414
415DEFINE_INSTRUCTION_LR35902(DEC_HLDelay,
416 int diff = cpu->bus - 1;
417 cpu->bus = diff;
418 cpu->f.n = 1;
419 cpu->f.z = !diff;
420 /* TODO: Find explanation of H flag */
421 cpu->instruction = _LR35902InstructionNOP;
422 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
423
424DEFINE_INSTRUCTION_LR35902(DEC_HL,
425 cpu->index = LR35902ReadHL(cpu);
426 cpu->instruction = _LR35902InstructionDEC_HLDelay;
427 cpu->executionState = LR35902_CORE_MEMORY_LOAD;)
428
429DEFINE_INSTRUCTION_LR35902(INCSP,
430 ++cpu->sp;
431 cpu->executionState = LR35902_CORE_STALL;)
432
433DEFINE_INSTRUCTION_LR35902(DECSP,
434 --cpu->sp;
435 cpu->executionState = LR35902_CORE_STALL;)
436
437
438#define DEFINE_POPPUSH_INSTRUCTION_LR35902(REG, HH, H, L) \
439 DEFINE_INSTRUCTION_LR35902(POP ## REG ## Delay, \
440 cpu-> L = cpu->bus; \
441 cpu->index = cpu->sp; \
442 ++cpu->sp; \
443 cpu->instruction = _LR35902InstructionLD ## HH ## _Bus; \
444 cpu->executionState = LR35902_CORE_MEMORY_LOAD;) \
445 DEFINE_INSTRUCTION_LR35902(POP ## REG, \
446 cpu->index = cpu->sp; \
447 ++cpu->sp; \
448 cpu->instruction = _LR35902InstructionPOP ## REG ## Delay; \
449 cpu->executionState = LR35902_CORE_MEMORY_LOAD;) \
450 DEFINE_INSTRUCTION_LR35902(PUSH ## REG ## Finish, \
451 cpu->instruction = _LR35902InstructionNOP; \
452 cpu->executionState = LR35902_CORE_STALL;) \
453 DEFINE_INSTRUCTION_LR35902(PUSH ## REG ## Delay, \
454 --cpu->sp; \
455 cpu->index = cpu->sp; \
456 cpu->bus = cpu-> L; \
457 cpu->instruction = _LR35902InstructionPUSH ## REG ## Finish; \
458 cpu->executionState = LR35902_CORE_MEMORY_STORE;) \
459 DEFINE_INSTRUCTION_LR35902(PUSH ## REG, \
460 --cpu->sp; \
461 cpu->index = cpu->sp; \
462 cpu->bus = cpu-> H; \
463 cpu->instruction = _LR35902InstructionPUSH ## REG ## Delay; \
464 cpu->executionState = LR35902_CORE_MEMORY_STORE;)
465
466DEFINE_POPPUSH_INSTRUCTION_LR35902(BC, B, b, c);
467DEFINE_POPPUSH_INSTRUCTION_LR35902(DE, D, d, e);
468DEFINE_POPPUSH_INSTRUCTION_LR35902(HL, H, h, l);
469DEFINE_POPPUSH_INSTRUCTION_LR35902(AF, A, a, f.packed);
470
471DEFINE_INSTRUCTION_LR35902(DI, cpu->irqh.setInterrupts(cpu, false));
472DEFINE_INSTRUCTION_LR35902(EI, cpu->irqh.setInterrupts(cpu, true));
473
474DEFINE_INSTRUCTION_LR35902(STUB, cpu->irqh.hitStub(cpu));
475
476static const LR35902Instruction _lr35902CBInstructionTable[0x100] = {
477 DECLARE_LR35902_CB_EMITTER_BLOCK(_LR35902Instruction)
478};
479
480DEFINE_INSTRUCTION_LR35902(CBDelegate, _lr35902CBInstructionTable[cpu->bus](cpu))
481
482DEFINE_INSTRUCTION_LR35902(CB, \
483 cpu->executionState = LR35902_CORE_READ_PC; \
484 cpu->instruction = _LR35902InstructionCBDelegate;)
485
486const LR35902Instruction _lr35902InstructionTable[0x100] = {
487 DECLARE_LR35902_EMITTER_BLOCK(_LR35902Instruction)
488};