src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
14 int rm = opcode & 0x0000000F;
15 int immediate = (opcode & 0x00000F80) >> 7;
16 if (!immediate) {
17 cpu->shifterOperand = cpu->gprs[rm];
18 cpu->shifterCarryOut = cpu->cpsr.c;
19 } else {
20 cpu->shifterOperand = cpu->gprs[rm] << immediate;
21 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
22 }
23}
24
25static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
26 int rm = opcode & 0x0000000F;
27 int rs = (opcode >> 8) & 0x0000000F;
28 ++cpu->cycles;
29 int shift = cpu->gprs[rs];
30 if (rs == ARM_PC) {
31 shift += 4;
32 }
33 shift &= 0xFF;
34 int32_t shiftVal = cpu->gprs[rm];
35 if (rm == ARM_PC) {
36 shiftVal += 4;
37 }
38 if (!shift) {
39 cpu->shifterOperand = shiftVal;
40 cpu->shifterCarryOut = cpu->cpsr.c;
41 } else if (shift < 32) {
42 cpu->shifterOperand = shiftVal << shift;
43 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
44 } else if (shift == 32) {
45 cpu->shifterOperand = 0;
46 cpu->shifterCarryOut = shiftVal & 1;
47 } else {
48 cpu->shifterOperand = 0;
49 cpu->shifterCarryOut = 0;
50 }
51}
52
53static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
54 int rm = opcode & 0x0000000F;
55 int immediate = (opcode & 0x00000F80) >> 7;
56 if (immediate) {
57 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
58 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
59 } else {
60 cpu->shifterOperand = 0;
61 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
62 }
63}
64
65static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
66 int rm = opcode & 0x0000000F;
67 int rs = (opcode >> 8) & 0x0000000F;
68 ++cpu->cycles;
69 int shift = cpu->gprs[rs];
70 if (rs == ARM_PC) {
71 shift += 4;
72 }
73 shift &= 0xFF;
74 uint32_t shiftVal = cpu->gprs[rm];
75 if (rm == ARM_PC) {
76 shiftVal += 4;
77 }
78 if (!shift) {
79 cpu->shifterOperand = shiftVal;
80 cpu->shifterCarryOut = cpu->cpsr.c;
81 } else if (shift < 32) {
82 cpu->shifterOperand = shiftVal >> shift;
83 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
84 } else if (shift == 32) {
85 cpu->shifterOperand = 0;
86 cpu->shifterCarryOut = shiftVal >> 31;
87 } else {
88 cpu->shifterOperand = 0;
89 cpu->shifterCarryOut = 0;
90 }
91}
92
93static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
94 int rm = opcode & 0x0000000F;
95 int immediate = (opcode & 0x00000F80) >> 7;
96 if (immediate) {
97 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
98 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
99 } else {
100 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
101 cpu->shifterOperand = cpu->shifterCarryOut;
102 }
103}
104
105static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
106 int rm = opcode & 0x0000000F;
107 ARM_STUB;
108}
109
110static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
111 int rm = opcode & 0x0000000F;
112 int immediate = (opcode & 0x00000F80) >> 7;
113 if (immediate) {
114 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
115 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
116 } else {
117 // RRX
118 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
119 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
120 }
121}
122
123static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
124 int rm = opcode & 0x0000000F;
125 int rs = (opcode >> 8) & 0x0000000F;
126 ++cpu->cycles;
127 int shift = cpu->gprs[rs];
128 if (rs == ARM_PC) {
129 shift += 4;
130 }
131 shift &= 0xFF;
132 int shiftVal = cpu->gprs[rm];
133 if (rm == ARM_PC) {
134 shiftVal += 4;
135 }
136 int rotate = shift & 0x1F;
137 if (!shift) {
138 cpu->shifterOperand = shiftVal;
139 cpu->shifterCarryOut = cpu->cpsr.c;
140 } else if (rotate) {
141 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
142 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
143 } else {
144 cpu->shifterOperand = shiftVal;
145 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
146 }
147}
148
149static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
150 int rotate = (opcode & 0x00000F00) >> 7;
151 int immediate = opcode & 0x000000FF;
152 if (!rotate) {
153 cpu->shifterOperand = immediate;
154 cpu->shifterCarryOut = cpu->cpsr.c;
155 } else {
156 cpu->shifterOperand = ARM_ROR(immediate, rotate);
157 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
158 }
159}
160
161static const ARMInstruction _armTable[0x1000];
162
163static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
164 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
165 *opcodeOut = opcode;
166 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
167}
168
169void ARMStep(struct ARMCore* cpu) {
170 // TODO
171 uint32_t opcode;
172 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
173 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
174
175 int condition = opcode >> 28;
176 if (condition == 0xE) {
177 instruction(cpu, opcode);
178 return;
179 } else {
180 switch (condition) {
181 case 0x0:
182 if (!ARM_COND_EQ) {
183 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
184 return;
185 }
186 break;
187 case 0x1:
188 if (!ARM_COND_NE) {
189 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
190 return;
191 }
192 break;
193 case 0x2:
194 if (!ARM_COND_CS) {
195 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
196 return;
197 }
198 break;
199 case 0x3:
200 if (!ARM_COND_CC) {
201 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
202 return;
203 }
204 break;
205 case 0x4:
206 if (!ARM_COND_MI) {
207 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
208 return;
209 }
210 break;
211 case 0x5:
212 if (!ARM_COND_PL) {
213 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
214 return;
215 }
216 break;
217 case 0x6:
218 if (!ARM_COND_VS) {
219 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
220 return;
221 }
222 break;
223 case 0x7:
224 if (!ARM_COND_VC) {
225 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
226 return;
227 }
228 break;
229 case 0x8:
230 if (!ARM_COND_HI) {
231 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
232 return;
233 }
234 break;
235 case 0x9:
236 if (!ARM_COND_LS) {
237 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
238 return;
239 }
240 break;
241 case 0xA:
242 if (!ARM_COND_GE) {
243 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
244 return;
245 }
246 break;
247 case 0xB:
248 if (!ARM_COND_LT) {
249 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
250 return;
251 }
252 break;
253 case 0xC:
254 if (!ARM_COND_GT) {
255 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
256 return;
257 }
258 break;
259 case 0xD:
260 if (!ARM_COND_LE) {
261 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
262 return;
263 }
264 break;
265 default:
266 break;
267 }
268 }
269 instruction(cpu, opcode);
270}
271
272// Instruction definitions
273// Beware pre-processor antics
274
275#define ARM_ADDITION_S(M, N, D) \
276 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
277 cpu->cpsr = cpu->spsr; \
278 _ARMReadCPSR(cpu); \
279 } else { \
280 cpu->cpsr.n = ARM_SIGN(D); \
281 cpu->cpsr.z = !(D); \
282 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
283 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
284 }
285
286#define ARM_SUBTRACTION_S(M, N, D) \
287 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
288 cpu->cpsr = cpu->spsr; \
289 _ARMReadCPSR(cpu); \
290 } else { \
291 cpu->cpsr.n = ARM_SIGN(D); \
292 cpu->cpsr.z = !(D); \
293 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
294 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
295 }
296
297#define ARM_NEUTRAL_S(M, N, D) \
298 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
299 cpu->cpsr = cpu->spsr; \
300 _ARMReadCPSR(cpu); \
301 } else { \
302 cpu->cpsr.n = ARM_SIGN(D); \
303 cpu->cpsr.z = !(D); \
304 cpu->cpsr.c = cpu->shifterCarryOut; \
305 }
306
307#define ARM_NEUTRAL_HI_S(DLO, DHI) \
308 cpu->cpsr.n = ARM_SIGN(DHI); \
309 cpu->cpsr.z = !((DHI) | (DLO));
310
311#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
312#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
313#define ADDR_MODE_2_ADDRESS (address)
314#define ADDR_MODE_2_RN (cpu->gprs[rn])
315#define ADDR_MODE_2_RM (cpu->gprs[rm])
316#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
317#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
318#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
319#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
320#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
321#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
322#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
323
324#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
325#define ADDR_MODE_3_RN ADDR_MODE_2_RN
326#define ADDR_MODE_3_RM ADDR_MODE_2_RM
327#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
328#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
329#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
330
331#define ARM_LOAD_POST_BODY \
332 if (rd == ARM_PC) { \
333 ARM_WRITE_PC; \
334 }
335
336#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
337 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
338 BODY; \
339 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32; \
340 }
341
342#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
343 DEFINE_INSTRUCTION_ARM(NAME, \
344 int rd = (opcode >> 12) & 0xF; \
345 int rn = (opcode >> 16) & 0xF; \
346 UNUSED(rn); \
347 SHIFTER(cpu, opcode); \
348 BODY; \
349 S_BODY; \
350 if (rd == ARM_PC) { \
351 if (cpu->executionMode == MODE_ARM) { \
352 ARM_WRITE_PC; \
353 } else { \
354 THUMB_WRITE_PC; \
355 } \
356 })
357
358#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
359 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
360 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
361 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
362 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
363 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
364 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
365 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
366 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
367 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
368 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
369 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
370 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
371 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
372 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
373 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
374 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
375 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
376 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
377
378#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
379 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
380 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
381 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
382 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
383 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
384 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
385 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
386 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
387 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
388
389#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
390 DEFINE_INSTRUCTION_ARM(NAME, \
391 int rd = (opcode >> 12) & 0xF; \
392 int rdHi = (opcode >> 16) & 0xF; \
393 int rs = (opcode >> 8) & 0xF; \
394 int rm = opcode & 0xF; \
395 UNUSED(rdHi); \
396 BODY; \
397 S_BODY; \
398 if (rd == ARM_PC) { \
399 ARM_WRITE_PC; \
400 })
401
402#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
403 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
404 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
405
406#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
407 DEFINE_INSTRUCTION_ARM(NAME, \
408 uint32_t address; \
409 int rn = (opcode >> 16) & 0xF; \
410 int rd = (opcode >> 12) & 0xF; \
411 int rm = opcode & 0xF; \
412 UNUSED(rm); \
413 address = ADDRESS; \
414 BODY; \
415 WRITEBACK;)
416
417#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
420 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
421 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
422 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
423 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
424
425#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
426 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
427 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
428 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
429 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
430 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
431 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
432 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
433 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
434 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
435 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
436
437#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
438 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
439 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
440 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
441 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
442 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
443 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
444 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
445 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
446 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
447 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
448 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
449 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
450
451#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
454
455#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
456 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
457 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
458 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
459 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
460 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
461 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
462
463#define ARM_MS_PRE \
464 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
465 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
466
467#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
468
469#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
470#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
471#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
472#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
473#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
474#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
475#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
476#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
477
478#define ARM_M_INCREMENT(BODY) \
479 for (m = rs, i = 0; m; m >>= 1, ++i) { \
480 if (m & 1) { \
481 BODY; \
482 addr += 4; \
483 } \
484 }
485
486#define ARM_M_DECREMENT(BODY) \
487 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
488 if (rs & m) { \
489 BODY; \
490 addr -= 4; \
491 } \
492 }
493
494#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
495 DEFINE_INSTRUCTION_ARM(NAME, \
496 int rn = (opcode >> 16) & 0xF; \
497 int rs = opcode & 0x0000FFFF; \
498 int m; \
499 int i; \
500 ADDRESS; \
501 S_PRE; \
502 LOOP(BODY); \
503 S_POST; \
504 WRITEBACK; \
505 POST_BODY;)
506
507
508#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
509 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
510 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
511 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
512 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
513 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
514 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
515 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
516 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
517 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
518 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
519 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
520 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
521 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
522 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
523 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
524 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
525
526// Begin ALU definitions
527
528DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
529 int32_t n = cpu->gprs[rn];
530 cpu->gprs[rd] = n + cpu->shifterOperand;)
531
532DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
533 int32_t n = cpu->gprs[rn];
534 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
535 cpu->gprs[rd] = n + shifterOperand;)
536
537DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
538 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
539
540DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
541 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
542
543DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
544 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
545
546DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
547 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
548
549DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
550 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
551
552DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
553 cpu->gprs[rd] = cpu->shifterOperand;)
554
555DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
556 cpu->gprs[rd] = ~cpu->shifterOperand;)
557
558DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
559 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
560
561DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
562 int32_t n = cpu->gprs[rn];
563 cpu->gprs[rd] = cpu->shifterOperand - n;)
564
565DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
566 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
567 cpu->gprs[rd] = cpu->shifterOperand - n;)
568
569DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
570 int32_t n = cpu->gprs[rn];
571 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
572 cpu->gprs[rd] = n - shifterOperand;)
573
574DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
575 int32_t n = cpu->gprs[rn];
576 cpu->gprs[rd] = n - cpu->shifterOperand;)
577
578DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
579 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
580
581DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
582 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
583
584// End ALU definitions
585
586// Begin multiply definitions
587
588DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
589DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
590DEFINE_INSTRUCTION_ARM(SMLAL, ARM_STUB)
591DEFINE_INSTRUCTION_ARM(SMLALS, ARM_STUB)
592DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
593 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
594 cpu->gprs[rd] = d;
595 cpu->gprs[rdHi] = d >> 32;,
596 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
597DEFINE_INSTRUCTION_ARM(UMLAL, ARM_STUB)
598DEFINE_INSTRUCTION_ARM(UMLALS, ARM_STUB)
599DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
600 uint64_t d = ((uint64_t) cpu->gprs[rm]) * ((uint64_t) cpu->gprs[rs]);
601 cpu->gprs[rd] = d;
602 cpu->gprs[rdHi] = d >> 32;,
603 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
604
605// End multiply definitions
606
607// Begin load/store definitions
608
609DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); ARM_LOAD_POST_BODY;)
610DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); ARM_LOAD_POST_BODY;)
611DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address); ARM_LOAD_POST_BODY;)
612DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address); ARM_LOAD_POST_BODY;)
613DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address); ARM_LOAD_POST_BODY;)
614DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
615DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
616DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
617
618DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
619 enum PrivilegeMode priv = cpu->privilegeMode;
620 ARMSetPrivilegeMode(cpu, MODE_USER);
621 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address);
622 ARMSetPrivilegeMode(cpu, priv);
623 ARM_LOAD_POST_BODY;)
624
625DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
626 enum PrivilegeMode priv = cpu->privilegeMode;
627 ARMSetPrivilegeMode(cpu, MODE_USER);
628 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address);
629 ARMSetPrivilegeMode(cpu, priv);
630 ARM_LOAD_POST_BODY;)
631
632DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
633 enum PrivilegeMode priv = cpu->privilegeMode;
634 ARMSetPrivilegeMode(cpu, MODE_USER);
635 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]);
636 ARMSetPrivilegeMode(cpu, priv);)
637
638DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
639 enum PrivilegeMode priv = cpu->privilegeMode;
640 ARMSetPrivilegeMode(cpu, MODE_USER);
641 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]);
642 ARMSetPrivilegeMode(cpu, priv);)
643
644DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
645 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr);,
646 if (rs & 0x8000) {
647 ARM_WRITE_PC;
648 })
649
650DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, cpu->memory->store32(cpu->memory, addr, cpu->gprs[i]);, )
651
652DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
653DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
654
655// End load/store definitions
656
657// Begin branch definitions
658
659DEFINE_INSTRUCTION_ARM(B,
660 int32_t offset = opcode << 8;
661 offset >>= 6;
662 cpu->gprs[ARM_PC] += offset;
663 ARM_WRITE_PC;)
664
665DEFINE_INSTRUCTION_ARM(BL,
666 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
667 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
668 cpu->gprs[ARM_PC] += immediate >> 6;
669 ARM_WRITE_PC;)
670
671DEFINE_INSTRUCTION_ARM(BX,
672 int rm = opcode & 0x0000000F;
673 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
674 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
675 if (cpu->executionMode == MODE_THUMB) {
676 THUMB_WRITE_PC;
677 } else {
678 ARM_WRITE_PC;
679 })
680
681// End branch definitions
682
683// Begin miscellaneous definitions
684
685DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
686DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
687
688DEFINE_INSTRUCTION_ARM(MSR,
689 int c = opcode & 0x00010000;
690 int f = opcode & 0x00080000;
691 int32_t operand = cpu->gprs[opcode & 0x0000000F];
692 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
693 if (mask & PSR_USER_MASK) {
694 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
695 }
696 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
697 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
698 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
699 })
700
701DEFINE_INSTRUCTION_ARM(MSRR,
702 int c = opcode & 0x00010000;
703 int f = opcode & 0x00080000;
704 int32_t operand = cpu->gprs[opcode & 0x0000000F];
705 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
706 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
707 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
708
709DEFINE_INSTRUCTION_ARM(MRS, \
710 int rd = (opcode >> 12) & 0xF; \
711 cpu->gprs[rd] = cpu->cpsr.packed;)
712
713DEFINE_INSTRUCTION_ARM(MRSR, \
714 int rd = (opcode >> 12) & 0xF; \
715 cpu->gprs[rd] = cpu->spsr.packed;)
716
717DEFINE_INSTRUCTION_ARM(MSRI,
718 int c = opcode & 0x00010000;
719 int f = opcode & 0x00080000;
720 int rotate = (opcode & 0x00000F00) >> 8;
721 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
722 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
723 if (mask & PSR_USER_MASK) {
724 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
725 }
726 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
727 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
728 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
729 })
730
731DEFINE_INSTRUCTION_ARM(MSRRI,
732 int c = opcode & 0x00010000;
733 int f = opcode & 0x00080000;
734 int rotate = (opcode & 0x00000F00) >> 8;
735 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
736 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
737 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
738 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
739
740DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
741
742#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
743 EMITTER ## NAME
744
745#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
746 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
747 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
748
749#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
750 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
751 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
752 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
753 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
754 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
755 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
756 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
757 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
758 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
759 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
760 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
761 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
762 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
763 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
764 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
765 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
766
767#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
768 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
769 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
770
771#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
772 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
773 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
774 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
775 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
776 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
777 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
778 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
779 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
780 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
781 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
782 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
783 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
784 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
785 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
786 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
787 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
788
789#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
790 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
791 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
792
793#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
794 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
795
796// TODO: Support coprocessors
797#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
798 DO_8(0), \
799 DO_8(0)
800
801#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
802 DO_8(DO_8(DO_INTERLACE(0, 0))), \
803 DO_8(DO_8(DO_INTERLACE(0, 0)))
804
805#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
806 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
807
808#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
809 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
810 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
811 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
812 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
813 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
814 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
815 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
816 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
817 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
818 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
819 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
820 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
821 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
822 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
823 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
824 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
825 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
826 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
827 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
828 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
829 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
830 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
831 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
832 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
833 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
834 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
835 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
836 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
837 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
838 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
839 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
840 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
841 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
842 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
843 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
844 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
845 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
846 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
847 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
848 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
849 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
850 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
851 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
852 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
853 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
854 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
855 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
856 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
857 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
858 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
859 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
860 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
861 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
862 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
863 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
864 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
865 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
866 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
867 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
868 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
869 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
870 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
871 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
872 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
873 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
874 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
875 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
876 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
877 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
878 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
879 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
880 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
881 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
882 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
883 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
884 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
885 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
886 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
887 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
888 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
889 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
890 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
891 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
892 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
893 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
894 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
895 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
896 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
897 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
898 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
899 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
900 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
901 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
902 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
903 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
904 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
905 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
906 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
907 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
908 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
909 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
910 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
911 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
912 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
913 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
914 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
915 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
916 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
917 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
918 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
919 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
920 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
921 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
922 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
923 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
924 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
925 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
926 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
927 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
928 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
929 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
930 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
931 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
932 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
933 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
934 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
935 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
936 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
937 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
938 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
939 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
940 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
941 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
942 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
943 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
944 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
945 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
946 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
947 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
948 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
949 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
950 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
951 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
952 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
953 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
954 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
955 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
956 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
957 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
958 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
959 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
960 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
961 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
962 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
963 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
964 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
965 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
966 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
967 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
968 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
969 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
970 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
971 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
972 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
973 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
974 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
975 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
976 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
977 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
978 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
979 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
980 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
981 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
982 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
983 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
984 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
985 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
986 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
987 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
988 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
989 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
990 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
991 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
992 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
993 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
994 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
995 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
996 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
997 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
998 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
999 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
1000 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
1001 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
1002 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
1003 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
1004 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
1005 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
1006 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
1007 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
1008 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
1009 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
1010 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
1011 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
1012 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
1013 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
1014 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
1015 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
1016 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
1017 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
1018 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
1019 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
1020 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
1021 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
1022 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
1023 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
1024 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
1025 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
1026 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
1027 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
1028 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
1029 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
1030 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
1031 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
1032 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
1033 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
1034 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
1035 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
1036 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
1037 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
1038 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
1039 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
1040 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
1041 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
1042 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
1043 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
1044 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
1045 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
1046 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
1047 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
1048 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
1049 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
1050 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
1051 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1052 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1053 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1054 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1055 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
1056 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
1057 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
1058 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
1059 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1060 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1061 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1062 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1063 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
1064 DECLARE_ARM_SWI_BLOCK(EMITTER)
1065
1066static const ARMInstruction _armTable[0x1000] = {
1067 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
1068};