src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/sm83/sm83.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value);
39static void _GBPKJD(struct GB* gb, uint16_t address, uint8_t value);
40
41static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
42static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
43static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
44static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
45
46static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
47static uint8_t _GBPKJDRead(struct GBMemory*, uint16_t address);
48
49static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
50static void _GBPocketCamCapture(struct GBMemory*);
51
52void GBMBCSwitchBank(struct GB* gb, int bank) {
53 size_t bankStart = bank * GB_SIZE_CART_BANK0;
54 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
55 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
56 bankStart &= (gb->memory.romSize - 1);
57 bank = bankStart / GB_SIZE_CART_BANK0;
58 }
59 gb->memory.romBank = &gb->memory.rom[bankStart];
60 gb->memory.currentBank = bank;
61 if (gb->cpu->pc < GB_BASE_VRAM) {
62 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
63 }
64}
65
66void GBMBCSwitchBank0(struct GB* gb, int bank) {
67 size_t bankStart = bank * GB_SIZE_CART_BANK0;
68 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
69 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
70 bankStart &= (gb->memory.romSize - 1);
71 }
72 gb->memory.romBase = &gb->memory.rom[bankStart];
73 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
74 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
75 }
76}
77
78void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
79 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
80 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
81 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
82 bankStart &= (gb->memory.romSize - 1);
83 bank = bankStart / GB_SIZE_CART_HALFBANK;
84 if (!bank) {
85 ++bank;
86 }
87 }
88 if (!half) {
89 gb->memory.romBank = &gb->memory.rom[bankStart];
90 gb->memory.currentBank = bank;
91 } else {
92 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
93 gb->memory.mbcState.mbc6.currentBank1 = bank;
94 }
95 if (gb->cpu->pc < GB_BASE_VRAM) {
96 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
97 }
98}
99
100static bool _isMulticart(const uint8_t* mem) {
101 bool success;
102 struct VFile* vf;
103
104 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
105 success = GBIsROM(vf);
106 vf->close(vf);
107
108 if (!success) {
109 return false;
110 }
111
112 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
113 success = GBIsROM(vf);
114 vf->close(vf);
115
116 if (!success) {
117 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
118 success = GBIsROM(vf);
119 vf->close(vf);
120 }
121
122 return success;
123}
124
125static bool _isWisdomTree(const uint8_t* mem, size_t size) {
126 size_t i;
127 for (i = 0x134; i < 0x14C; i += 4) {
128 if (*(uint32_t*) &mem[i] != 0) {
129 return false;
130 }
131 }
132 for (i = 0xF0; i < 0x100; i += 4) {
133 if (*(uint32_t*) &mem[i] != 0) {
134 return false;
135 }
136 }
137 if (mem[0x14D] != 0xE7) {
138 return false;
139 }
140 for (i = 0x300; i < size - 11; ++i) {
141 if (memcmp(&mem[i], "WISDOM", 6) == 0 && memcmp(&mem[i + 7], "TREE", 4) == 0) {
142 return true;
143 }
144 }
145 return false;
146}
147
148void GBMBCSwitchSramBank(struct GB* gb, int bank) {
149 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
150 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
151 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
152 bankStart &= (gb->sramSize - 1);
153 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
154 }
155 gb->memory.sramBank = &gb->memory.sram[bankStart];
156 gb->memory.sramCurrentBank = bank;
157}
158
159void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
160 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
161 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
162 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
163 bankStart &= (gb->sramSize - 1);
164 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
165 }
166 if (!half) {
167 gb->memory.sramBank = &gb->memory.sram[bankStart];
168 gb->memory.sramCurrentBank = bank;
169 } else {
170 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
171 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
172 }
173}
174
175void GBMBCInit(struct GB* gb) {
176 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
177 if (gb->memory.rom) {
178 if (gb->memory.romSize >= 0x8000) {
179 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
180 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
181 cart = cartFooter;
182 }
183 }
184 switch (cart->ramSize) {
185 case 0:
186 gb->sramSize = 0;
187 break;
188 case 1:
189 gb->sramSize = 0x800;
190 break;
191 default:
192 case 2:
193 gb->sramSize = 0x2000;
194 break;
195 case 3:
196 gb->sramSize = 0x8000;
197 break;
198 case 4:
199 gb->sramSize = 0x20000;
200 break;
201 case 5:
202 gb->sramSize = 0x10000;
203 break;
204 }
205
206 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
207 switch (cart->type) {
208 case 0:
209 if (_isWisdomTree(gb->memory.rom, gb->memory.romSize)) {
210 gb->memory.mbcType = GB_UNL_WISDOM_TREE;
211 break;
212 }
213 // Fall through
214 case 8:
215 case 9:
216 gb->memory.mbcType = GB_MBC_NONE;
217 break;
218 case 1:
219 case 2:
220 case 3:
221 gb->memory.mbcType = GB_MBC1;
222 break;
223 case 5:
224 case 6:
225 gb->memory.mbcType = GB_MBC2;
226 break;
227 case 0x0B:
228 case 0x0C:
229 case 0x0D:
230 gb->memory.mbcType = GB_MMM01;
231 break;
232 case 0x0F:
233 case 0x10:
234 gb->memory.mbcType = GB_MBC3_RTC;
235 break;
236 case 0x11:
237 case 0x12:
238 case 0x13:
239 gb->memory.mbcType = GB_MBC3;
240 break;
241 default:
242 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
243 // Fall through
244 case 0x19:
245 case 0x1A:
246 case 0x1B:
247 gb->memory.mbcType = GB_MBC5;
248 break;
249 case 0x1C:
250 case 0x1D:
251 case 0x1E:
252 gb->memory.mbcType = GB_MBC5_RUMBLE;
253 break;
254 case 0x20:
255 gb->memory.mbcType = GB_MBC6;
256 break;
257 case 0x22:
258 gb->memory.mbcType = GB_MBC7;
259 break;
260 case 0xFC:
261 gb->memory.mbcType = GB_POCKETCAM;
262 break;
263 case 0xFD:
264 gb->memory.mbcType = GB_TAMA5;
265 break;
266 case 0xFE:
267 gb->memory.mbcType = GB_HuC3;
268 break;
269 case 0xFF:
270 gb->memory.mbcType = GB_HuC1;
271 break;
272 }
273 }
274 } else {
275 gb->memory.mbcType = GB_MBC_NONE;
276 }
277 gb->memory.mbcRead = NULL;
278 gb->memory.directSramAccess = true;
279 switch (gb->memory.mbcType) {
280 case GB_MBC_NONE:
281 gb->memory.mbcWrite = _GBMBCNone;
282 break;
283 case GB_MBC1:
284 gb->memory.mbcWrite = _GBMBC1;
285 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
286 gb->memory.mbcState.mbc1.multicartStride = 4;
287 } else {
288 gb->memory.mbcState.mbc1.multicartStride = 5;
289 }
290 break;
291 case GB_MBC2:
292 gb->memory.mbcWrite = _GBMBC2;
293 gb->memory.mbcRead = _GBMBC2Read;
294 gb->memory.directSramAccess = false;
295 gb->sramSize = 0x100;
296 break;
297 case GB_MBC3:
298 gb->memory.mbcWrite = _GBMBC3;
299 break;
300 default:
301 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
302 // Fall through
303 case GB_MBC5:
304 gb->memory.mbcWrite = _GBMBC5;
305 break;
306 case GB_MBC6:
307 gb->memory.mbcWrite = _GBMBC6;
308 gb->memory.mbcRead = _GBMBC6Read;
309 gb->memory.directSramAccess = false;
310 break;
311 case GB_MBC7:
312 gb->memory.mbcWrite = _GBMBC7;
313 gb->memory.mbcRead = _GBMBC7Read;
314 gb->sramSize = 0x100;
315 break;
316 case GB_MMM01:
317 gb->memory.mbcWrite = _GBMMM01;
318 break;
319 case GB_HuC1:
320 gb->memory.mbcWrite = _GBHuC1;
321 break;
322 case GB_HuC3:
323 gb->memory.mbcWrite = _GBHuC3;
324 break;
325 case GB_TAMA5:
326 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
327 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
328 gb->memory.mbcWrite = _GBTAMA5;
329 gb->memory.mbcRead = _GBTAMA5Read;
330 gb->sramSize = 0x20;
331 break;
332 case GB_MBC3_RTC:
333 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
334 gb->memory.mbcWrite = _GBMBC3;
335 break;
336 case GB_MBC5_RUMBLE:
337 gb->memory.mbcWrite = _GBMBC5;
338 break;
339 case GB_POCKETCAM:
340 gb->memory.mbcWrite = _GBPocketCam;
341 gb->memory.mbcRead = _GBPocketCamRead;
342 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
343 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
344 }
345 break;
346 case GB_UNL_WISDOM_TREE:
347 gb->memory.mbcWrite = _GBWisdomTree;
348 break;
349 case GB_UNL_PKJD:
350 gb->memory.mbcWrite = _GBPKJD;
351 gb->memory.mbcRead = _GBPKJDRead;
352 break;
353 }
354
355 gb->memory.currentBank = 1;
356 gb->memory.sramCurrentBank = 0;
357 gb->memory.sramAccess = false;
358 gb->memory.rtcAccess = false;
359 gb->memory.activeRtcReg = 0;
360 gb->memory.rtcLatched = false;
361 gb->memory.rtcLastLatch = 0;
362 if (gb->memory.rtc) {
363 if (gb->memory.rtc->sample) {
364 gb->memory.rtc->sample(gb->memory.rtc);
365 }
366 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
367 } else {
368 gb->memory.rtcLastLatch = time(0);
369 }
370 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
371
372 GBResizeSram(gb, gb->sramSize);
373
374 if (gb->memory.mbcType == GB_MBC3_RTC) {
375 GBMBCRTCRead(gb);
376 }
377}
378
379static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
380 time_t t;
381 if (rtc) {
382 if (rtc->sample) {
383 rtc->sample(rtc);
384 }
385 t = rtc->unixTime(rtc);
386 } else {
387 t = time(0);
388 }
389 time_t currentLatch = t;
390 t -= *rtcLastLatch;
391 *rtcLastLatch = currentLatch;
392
393 int64_t diff;
394 diff = rtcRegs[0] + t % 60;
395 if (diff < 0) {
396 diff += 60;
397 t -= 60;
398 }
399 rtcRegs[0] = diff % 60;
400 t /= 60;
401 t += diff / 60;
402
403 diff = rtcRegs[1] + t % 60;
404 if (diff < 0) {
405 diff += 60;
406 t -= 60;
407 }
408 rtcRegs[1] = diff % 60;
409 t /= 60;
410 t += diff / 60;
411
412 diff = rtcRegs[2] + t % 24;
413 if (diff < 0) {
414 diff += 24;
415 t -= 24;
416 }
417 rtcRegs[2] = diff % 24;
418 t /= 24;
419 t += diff / 24;
420
421 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
422 rtcRegs[3] = diff;
423 rtcRegs[4] &= 0xFE;
424 rtcRegs[4] |= (diff >> 8) & 1;
425 if (diff & 0x200) {
426 rtcRegs[4] |= 0x80;
427 }
428}
429
430static void _GBMBC1Update(struct GB* gb) {
431 struct GBMBC1State* state = &gb->memory.mbcState.mbc1;
432 int bank = state->bankLo;
433 bank &= (1 << state->multicartStride) - 1;
434 bank |= state->bankHi << state->multicartStride;
435 if (state->mode) {
436 GBMBCSwitchBank0(gb, state->bankHi << state->multicartStride);
437 GBMBCSwitchSramBank(gb, state->bankHi & 3);
438 } else {
439 GBMBCSwitchBank0(gb, 0);
440 GBMBCSwitchSramBank(gb, 0);
441 }
442 if (!(state->bankLo & 0x1F)) {
443 ++bank;
444 }
445 GBMBCSwitchBank(gb, bank);
446}
447
448void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
449 struct GBMemory* memory = &gb->memory;
450 int bank = value & 0x1F;
451 switch (address >> 13) {
452 case 0x0:
453 switch (value & 0xF) {
454 case 0:
455 memory->sramAccess = false;
456 break;
457 case 0xA:
458 memory->sramAccess = true;
459 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
460 break;
461 default:
462 // TODO
463 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
464 break;
465 }
466 break;
467 case 0x1:
468 memory->mbcState.mbc1.bankLo = bank;
469 _GBMBC1Update(gb);
470 break;
471 case 0x2:
472 bank &= 3;
473 memory->mbcState.mbc1.bankHi = bank;
474 _GBMBC1Update(gb);
475 break;
476 case 0x3:
477 memory->mbcState.mbc1.mode = value & 1;
478 _GBMBC1Update(gb);
479 break;
480 default:
481 // TODO
482 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
483 break;
484 }
485}
486
487void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
488 struct GBMemory* memory = &gb->memory;
489 int shift = (address & 1) * 4;
490 int bank = value & 0xF;
491 switch ((address & 0xC100) >> 8) {
492 case 0x0:
493 switch (value & 0x0F) {
494 case 0:
495 memory->sramAccess = false;
496 break;
497 case 0xA:
498 memory->sramAccess = true;
499 break;
500 default:
501 // TODO
502 mLOG(GB_MBC, STUB, "MBC2 unknown value %02X", value);
503 break;
504 }
505 break;
506 case 0x1:
507 if (!bank) {
508 ++bank;
509 }
510 GBMBCSwitchBank(gb, bank);
511 break;
512 case 0x80:
513 case 0x81:
514 case 0x82:
515 case 0x83:
516 if (!memory->sramAccess) {
517 return;
518 }
519 address &= 0x1FF;
520 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
521 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
522 break;
523 default:
524 // TODO
525 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
526 break;
527 }
528}
529
530static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
531 if (!memory->sramAccess) {
532 return 0xFF;
533 }
534 address &= 0x1FF;
535 int shift = (address & 1) * 4;
536 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
537}
538
539void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
540 struct GBMemory* memory = &gb->memory;
541 int bank = value;
542 switch (address >> 13) {
543 case 0x0:
544 switch (value) {
545 case 0:
546 memory->sramAccess = false;
547 break;
548 case 0xA:
549 memory->sramAccess = true;
550 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
551 break;
552 default:
553 // TODO
554 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
555 break;
556 }
557 break;
558 case 0x1:
559 if (gb->memory.romSize < GB_SIZE_CART_BANK0 * 0x80) {
560 bank &= 0x7F;
561 }
562 if (!bank) {
563 ++bank;
564 }
565 GBMBCSwitchBank(gb, bank);
566 break;
567 case 0x2:
568 if (value < 8) {
569 GBMBCSwitchSramBank(gb, value);
570 memory->rtcAccess = false;
571 } else if (value <= 0xC) {
572 memory->activeRtcReg = value - 8;
573 memory->rtcAccess = true;
574 }
575 break;
576 case 0x3:
577 if (memory->rtcLatched && value == 0) {
578 memory->rtcLatched = false;
579 } else if (!memory->rtcLatched && value == 1) {
580 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
581 memory->rtcLatched = true;
582 }
583 break;
584 }
585}
586
587void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
588 struct GBMemory* memory = &gb->memory;
589 int bank;
590 switch (address >> 12) {
591 case 0x0:
592 case 0x1:
593 switch (value) {
594 case 0:
595 memory->sramAccess = false;
596 break;
597 case 0xA:
598 memory->sramAccess = true;
599 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
600 break;
601 default:
602 // TODO
603 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
604 break;
605 }
606 break;
607 case 0x2:
608 bank = (memory->currentBank & 0x100) | value;
609 GBMBCSwitchBank(gb, bank);
610 break;
611 case 0x3:
612 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
613 GBMBCSwitchBank(gb, bank);
614 break;
615 case 0x4:
616 case 0x5:
617 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
618 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
619 value &= ~8;
620 }
621 GBMBCSwitchSramBank(gb, value & 0xF);
622 break;
623 default:
624 // TODO
625 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
626 break;
627 }
628}
629
630void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
631 struct GBMemory* memory = &gb->memory;
632 int bank = value;
633 switch (address >> 10) {
634 case 0:
635 switch (value) {
636 case 0:
637 memory->sramAccess = false;
638 break;
639 case 0xA:
640 memory->sramAccess = true;
641 break;
642 default:
643 // TODO
644 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
645 break;
646 }
647 break;
648 case 0x1:
649 GBMBCSwitchSramHalfBank(gb, 0, bank);
650 break;
651 case 0x2:
652 GBMBCSwitchSramHalfBank(gb, 1, bank);
653 break;
654 case 0x8:
655 case 0x9:
656 GBMBCSwitchHalfBank(gb, 0, bank);
657 break;
658 case 0xC:
659 case 0xD:
660 GBMBCSwitchHalfBank(gb, 1, bank);
661 break;
662 case 0x28:
663 case 0x29:
664 case 0x2A:
665 case 0x2B:
666 if (memory->sramAccess) {
667 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
668 }
669 break;
670 case 0x2C:
671 case 0x2D:
672 case 0x2E:
673 case 0x2F:
674 if (memory->sramAccess) {
675 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
676 }
677 break;
678 default:
679 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
680 break;
681 }
682}
683
684uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
685 if (!memory->sramAccess) {
686 return 0xFF;
687 }
688 switch (address >> 12) {
689 case 0xA:
690 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
691 case 0xB:
692 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
693 }
694 return 0xFF;
695}
696
697void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
698 int bank = value & 0x7F;
699 switch (address >> 13) {
700 case 0x0:
701 switch (value) {
702 default:
703 case 0:
704 gb->memory.mbcState.mbc7.access = 0;
705 break;
706 case 0xA:
707 gb->memory.mbcState.mbc7.access |= 1;
708 break;
709 }
710 break;
711 case 0x1:
712 GBMBCSwitchBank(gb, bank);
713 break;
714 case 0x2:
715 if (value == 0x40) {
716 gb->memory.mbcState.mbc7.access |= 2;
717 } else {
718 gb->memory.mbcState.mbc7.access &= ~2;
719 }
720 break;
721 case 0x5:
722 _GBMBC7Write(&gb->memory, address, value);
723 break;
724 default:
725 // TODO
726 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
727 break;
728 }
729}
730
731uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
732 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
733 if (mbc7->access != 3) {
734 return 0xFF;
735 }
736 switch (address & 0xF0) {
737 case 0x20:
738 if (memory->rotation && memory->rotation->readTiltX) {
739 int32_t x = -memory->rotation->readTiltX(memory->rotation);
740 x >>= 21;
741 x += 0x81D0;
742 return x;
743 }
744 return 0xFF;
745 case 0x30:
746 if (memory->rotation && memory->rotation->readTiltX) {
747 int32_t x = -memory->rotation->readTiltX(memory->rotation);
748 x >>= 21;
749 x += 0x81D0;
750 return x >> 8;
751 }
752 return 7;
753 case 0x40:
754 if (memory->rotation && memory->rotation->readTiltY) {
755 int32_t y = -memory->rotation->readTiltY(memory->rotation);
756 y >>= 21;
757 y += 0x81D0;
758 return y;
759 }
760 return 0xFF;
761 case 0x50:
762 if (memory->rotation && memory->rotation->readTiltY) {
763 int32_t y = -memory->rotation->readTiltY(memory->rotation);
764 y >>= 21;
765 y += 0x81D0;
766 return y >> 8;
767 }
768 return 7;
769 case 0x60:
770 return 0;
771 case 0x80:
772 return mbc7->eeprom;
773 default:
774 return 0xFF;
775 }
776}
777
778static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
779 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
780 if (mbc7->access != 3) {
781 return;
782 }
783 switch (address & 0xF0) {
784 case 0x00:
785 mbc7->latch = (value & 0x55) == 0x55;
786 return;
787 case 0x10:
788 mbc7->latch |= (value & 0xAA);
789 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
790 memory->rotation->sample(memory->rotation);
791 }
792 mbc7->latch = 0;
793 return;
794 default:
795 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
796 return;
797 case 0x80:
798 break;
799 }
800 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
801 value = GBMBC7FieldFillDO(value); // Hi-Z
802 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
803 mbc7->state = GBMBC7_STATE_IDLE;
804 }
805 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
806 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
807 mbc7->sr <<= 1;
808 mbc7->sr |= GBMBC7FieldGetDI(value);
809 ++mbc7->srBits;
810 }
811 switch (mbc7->state) {
812 case GBMBC7_STATE_IDLE:
813 if (GBMBC7FieldIsDI(value)) {
814 mbc7->state = GBMBC7_STATE_READ_COMMAND;
815 mbc7->srBits = 0;
816 mbc7->sr = 0;
817 }
818 break;
819 case GBMBC7_STATE_READ_COMMAND:
820 if (mbc7->srBits == 10) {
821 mbc7->state = 0x10 | (mbc7->sr >> 6);
822 if (mbc7->state & 0xC) {
823 mbc7->state &= ~0x3;
824 }
825 mbc7->srBits = 0;
826 mbc7->address = mbc7->sr & 0x7F;
827 }
828 break;
829 case GBMBC7_STATE_DO:
830 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
831 mbc7->sr <<= 1;
832 --mbc7->srBits;
833 if (!mbc7->srBits) {
834 mbc7->state = GBMBC7_STATE_IDLE;
835 }
836 break;
837 default:
838 break;
839 }
840 switch (mbc7->state) {
841 case GBMBC7_STATE_EEPROM_EWEN:
842 mbc7->writable = true;
843 mbc7->state = GBMBC7_STATE_IDLE;
844 break;
845 case GBMBC7_STATE_EEPROM_EWDS:
846 mbc7->writable = false;
847 mbc7->state = GBMBC7_STATE_IDLE;
848 break;
849 case GBMBC7_STATE_EEPROM_WRITE:
850 if (mbc7->srBits == 16) {
851 if (mbc7->writable) {
852 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
853 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
854 }
855 mbc7->state = GBMBC7_STATE_IDLE;
856 }
857 break;
858 case GBMBC7_STATE_EEPROM_ERASE:
859 if (mbc7->writable) {
860 memory->sram[mbc7->address * 2] = 0xFF;
861 memory->sram[mbc7->address * 2 + 1] = 0xFF;
862 }
863 mbc7->state = GBMBC7_STATE_IDLE;
864 break;
865 case GBMBC7_STATE_EEPROM_READ:
866 mbc7->srBits = 16;
867 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
868 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
869 mbc7->state = GBMBC7_STATE_DO;
870 value = GBMBC7FieldClearDO(value);
871 break;
872 case GBMBC7_STATE_EEPROM_WRAL:
873 if (mbc7->srBits == 16) {
874 if (mbc7->writable) {
875 int i;
876 for (i = 0; i < 128; ++i) {
877 memory->sram[i * 2] = mbc7->sr >> 8;
878 memory->sram[i * 2 + 1] = mbc7->sr;
879 }
880 }
881 mbc7->state = GBMBC7_STATE_IDLE;
882 }
883 break;
884 case GBMBC7_STATE_EEPROM_ERAL:
885 if (mbc7->writable) {
886 int i;
887 for (i = 0; i < 128; ++i) {
888 memory->sram[i * 2] = 0xFF;
889 memory->sram[i * 2 + 1] = 0xFF;
890 }
891 }
892 mbc7->state = GBMBC7_STATE_IDLE;
893 break;
894 default:
895 break;
896 }
897 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
898 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
899 }
900 mbc7->eeprom = value;
901}
902
903void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
904 struct GBMemory* memory = &gb->memory;
905 if (!memory->mbcState.mmm01.locked) {
906 switch (address >> 13) {
907 case 0x0:
908 memory->mbcState.mmm01.locked = true;
909 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
910 break;
911 case 0x1:
912 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
913 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
914 break;
915 case 0x2:
916 memory->mbcState.mmm01.currentBank0 &= ~0x180;
917 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
918 break;
919 default:
920 // TODO
921 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
922 break;
923 }
924 return;
925 }
926 switch (address >> 13) {
927 case 0x0:
928 switch (value) {
929 case 0xA:
930 memory->sramAccess = true;
931 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
932 break;
933 default:
934 memory->sramAccess = false;
935 break;
936 }
937 break;
938 case 0x1:
939 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
940 break;
941 case 0x2:
942 GBMBCSwitchSramBank(gb, value);
943 break;
944 default:
945 // TODO
946 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
947 break;
948 }
949}
950
951void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
952 struct GBMemory* memory = &gb->memory;
953 int bank = value & 0x3F;
954 switch (address >> 13) {
955 case 0x0:
956 switch (value) {
957 case 0xE:
958 memory->sramAccess = false;
959 break;
960 default:
961 memory->sramAccess = true;
962 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
963 break;
964 }
965 break;
966 case 0x1:
967 GBMBCSwitchBank(gb, bank);
968 break;
969 case 0x2:
970 GBMBCSwitchSramBank(gb, value);
971 break;
972 default:
973 // TODO
974 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
975 break;
976 }
977}
978
979void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
980 struct GBMemory* memory = &gb->memory;
981 int bank = value & 0x3F;
982 if (address & 0x1FFF) {
983 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
984 }
985
986 switch (address >> 13) {
987 case 0x0:
988 switch (value) {
989 case 0xA:
990 memory->sramAccess = true;
991 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
992 break;
993 default:
994 memory->sramAccess = false;
995 break;
996 }
997 break;
998 case 0x1:
999 GBMBCSwitchBank(gb, bank);
1000 break;
1001 case 0x2:
1002 GBMBCSwitchSramBank(gb, bank);
1003 break;
1004 default:
1005 // TODO
1006 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
1007 break;
1008 }
1009}
1010
1011void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
1012 struct GBMemory* memory = &gb->memory;
1013 int bank = value & 0x3F;
1014 switch (address >> 13) {
1015 case 0x0:
1016 switch (value) {
1017 case 0:
1018 memory->sramAccess = false;
1019 break;
1020 case 0xA:
1021 memory->sramAccess = true;
1022 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1023 break;
1024 default:
1025 // TODO
1026 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
1027 break;
1028 }
1029 break;
1030 case 0x1:
1031 GBMBCSwitchBank(gb, bank);
1032 break;
1033 case 0x2:
1034 if (value < 0x10) {
1035 GBMBCSwitchSramBank(gb, value);
1036 memory->mbcState.pocketCam.registersActive = false;
1037 } else {
1038 memory->mbcState.pocketCam.registersActive = true;
1039 }
1040 break;
1041 case 0x5:
1042 address &= 0x7F;
1043 if (address == 0 && value & 1) {
1044 value &= 6; // TODO: Timing
1045 _GBPocketCamCapture(memory);
1046 }
1047 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
1048 memory->mbcState.pocketCam.registers[address] = value;
1049 }
1050 break;
1051 default:
1052 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
1053 break;
1054 }
1055}
1056
1057uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1058 if (memory->mbcState.pocketCam.registersActive) {
1059 if ((address & 0x7F) == 0) {
1060 return memory->mbcState.pocketCam.registers[0];
1061 }
1062 return 0;
1063 }
1064 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1065}
1066
1067void _GBPocketCamCapture(struct GBMemory* memory) {
1068 if (!memory->cam) {
1069 return;
1070 }
1071 const void* image = NULL;
1072 size_t stride;
1073 enum mColorFormat format;
1074 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1075 if (!image) {
1076 return;
1077 }
1078 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1079 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1080 size_t x, y;
1081 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1082 for (x = 0; x < GBCAM_WIDTH; ++x) {
1083 uint32_t gray;
1084 uint32_t color;
1085 switch (format) {
1086 case mCOLOR_XBGR8:
1087 case mCOLOR_XRGB8:
1088 case mCOLOR_ARGB8:
1089 case mCOLOR_ABGR8:
1090 color = ((const uint32_t*) image)[y * stride + x];
1091 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1092 break;
1093 case mCOLOR_BGRX8:
1094 case mCOLOR_RGBX8:
1095 case mCOLOR_RGBA8:
1096 case mCOLOR_BGRA8:
1097 color = ((const uint32_t*) image)[y * stride + x];
1098 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1099 break;
1100 case mCOLOR_BGR5:
1101 case mCOLOR_RGB5:
1102 case mCOLOR_ARGB5:
1103 case mCOLOR_ABGR5:
1104 color = ((const uint16_t*) image)[y * stride + x];
1105 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1106 break;
1107 case mCOLOR_BGR565:
1108 case mCOLOR_RGB565:
1109 color = ((const uint16_t*) image)[y * stride + x];
1110 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1111 break;
1112 case mCOLOR_BGRA5:
1113 case mCOLOR_RGBA5:
1114 color = ((const uint16_t*) image)[y * stride + x];
1115 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1116 break;
1117 default:
1118 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1119 return;
1120 }
1121 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1122 gray = (gray + 1) * exposure / 0x300;
1123 // TODO: Additional processing
1124 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1125 if (gray < pocketCam->registers[matrixEntry + 6]) {
1126 gray = 0x101;
1127 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1128 gray = 0x100;
1129 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1130 gray = 0x001;
1131 } else {
1132 gray = 0;
1133 }
1134 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1135 uint16_t existing;
1136 LOAD_16LE(existing, coord + 0x100, memory->sram);
1137 existing |= gray << (7 - (x & 7));
1138 STORE_16LE(existing, coord + 0x100, memory->sram);
1139 }
1140 }
1141}
1142
1143void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1144 struct GBMemory* memory = &gb->memory;
1145 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1146 switch (address >> 13) {
1147 case 0x5:
1148 if (address & 1) {
1149 tama5->reg = value;
1150 } else {
1151 value &= 0xF;
1152 if (tama5->reg < GBTAMA5_MAX) {
1153 tama5->registers[tama5->reg] = value;
1154 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1155 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1156 switch (tama5->reg) {
1157 case GBTAMA5_BANK_LO:
1158 case GBTAMA5_BANK_HI:
1159 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1160 break;
1161 case GBTAMA5_WRITE_LO:
1162 case GBTAMA5_WRITE_HI:
1163 case GBTAMA5_CS:
1164 break;
1165 case GBTAMA5_ADDR_LO:
1166 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1167 case 0x0: // RAM write
1168 memory->sram[address] = out;
1169 break;
1170 case 0x1: // RAM read
1171 break;
1172 default:
1173 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1174 }
1175 break;
1176 default:
1177 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1178 break;
1179 }
1180 } else {
1181 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1182 }
1183 }
1184 break;
1185 default:
1186 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1187 }
1188}
1189
1190uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1191 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1192 if ((address & 0x1FFF) > 1) {
1193 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1194 }
1195 if (address & 1) {
1196 return 0xFF;
1197 } else {
1198 uint8_t value = 0xF0;
1199 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1200 switch (tama5->reg) {
1201 case GBTAMA5_ACTIVE:
1202 return 0xF1;
1203 case GBTAMA5_READ_LO:
1204 case GBTAMA5_READ_HI:
1205 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1206 case 1:
1207 value = memory->sram[address];
1208 break;
1209 default:
1210 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1211 break;
1212 }
1213 if (tama5->reg == GBTAMA5_READ_HI) {
1214 value >>= 4;
1215 }
1216 value |= 0xF0;
1217 return value;
1218 default:
1219 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1220 return 0xF1;
1221 }
1222 }
1223}
1224
1225void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) {
1226 UNUSED(value);
1227 int bank = address & 0x3F;
1228 switch (address >> 14) {
1229 case 0x0:
1230 GBMBCSwitchBank0(gb, bank * 2);
1231 GBMBCSwitchBank(gb, bank * 2 + 1);
1232 break;
1233 default:
1234 // TODO
1235 mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value);
1236 break;
1237 }
1238}
1239
1240void _GBPKJD(struct GB* gb, uint16_t address, uint8_t value) {
1241 struct GBMemory* memory = &gb->memory;
1242 switch (address >> 13) {
1243 case 0x2:
1244 if (value < 8) {
1245 memory->directSramAccess = true;
1246 memory->activeRtcReg = 0;
1247 } else if (value >= 0xD && value <= 0xF) {
1248 memory->directSramAccess = false;
1249 memory->rtcAccess = false;
1250 memory->activeRtcReg = value - 8;
1251 }
1252 break;
1253 case 0x5:
1254 if (!memory->sramAccess) {
1255 return;
1256 }
1257 switch (memory->activeRtcReg) {
1258 case 0:
1259 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
1260 break;
1261 case 5:
1262 case 6:
1263 memory->mbcState.pkjd.reg[memory->activeRtcReg - 5] = value;
1264 break;
1265 case 7:
1266 switch (value) {
1267 case 0x11:
1268 memory->mbcState.pkjd.reg[0]--;
1269 break;
1270 case 0x12:
1271 memory->mbcState.pkjd.reg[1]--;
1272 break;
1273 case 0x41:
1274 memory->mbcState.pkjd.reg[0] += memory->mbcState.pkjd.reg[1];
1275 break;
1276 case 0x42:
1277 memory->mbcState.pkjd.reg[1] += memory->mbcState.pkjd.reg[0];
1278 break;
1279 case 0x51:
1280 memory->mbcState.pkjd.reg[0]++;
1281 break;
1282 case 0x52:
1283 memory->mbcState.pkjd.reg[1]--;
1284 break;
1285 }
1286 break;
1287 }
1288 return;
1289 }
1290 _GBMBC3(gb, address, value);
1291}
1292
1293static uint8_t _GBPKJDRead(struct GBMemory* memory, uint16_t address) {
1294 if (!memory->sramAccess) {
1295 return 0xFF;
1296 }
1297 switch (memory->activeRtcReg) {
1298 case 0:
1299 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1300 case 5:
1301 case 6:
1302 return memory->mbcState.pkjd.reg[memory->activeRtcReg - 5];
1303 default:
1304 return 0;
1305 }
1306}
1307
1308void GBMBCRTCRead(struct GB* gb) {
1309 struct GBMBCRTCSaveBuffer rtcBuffer;
1310 struct VFile* vf = gb->sramVf;
1311 if (!vf) {
1312 return;
1313 }
1314 vf->seek(vf, gb->sramSize, SEEK_SET);
1315 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1316 return;
1317 }
1318
1319 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1320 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1321 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1322 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1323 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1324 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1325}
1326
1327void GBMBCRTCWrite(struct GB* gb) {
1328 struct VFile* vf = gb->sramVf;
1329 if (!vf) {
1330 return;
1331 }
1332
1333 uint8_t rtcRegs[5];
1334 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1335 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1336 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1337
1338 struct GBMBCRTCSaveBuffer rtcBuffer;
1339 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1340 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1341 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1342 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1343 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1344 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1345 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1346 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1347 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1348 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1349 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1350
1351 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1352 // Writing past the end of the file can invalidate the file mapping
1353 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1354 gb->memory.sram = NULL;
1355 }
1356 vf->seek(vf, gb->sramSize, SEEK_SET);
1357 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1358 if (!gb->memory.sram) {
1359 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1360 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1361 }
1362}