src/gb/memory.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/memory.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/gb/gb.h>
10#include <mgba/internal/gb/io.h>
11#include <mgba/internal/gb/mbc.h>
12#include <mgba/internal/gb/serialize.h>
13#include <mgba/internal/lr35902/lr35902.h>
14
15#include <mgba-util/memory.h>
16
17mLOG_DEFINE_CATEGORY(GB_MEM, "GB Memory", "gb.memory");
18
19enum GBBus {
20 GB_BUS_CPU,
21 GB_BUS_MAIN,
22 GB_BUS_VRAM,
23 GB_BUS_RAM
24};
25
26static const enum GBBus _oamBlockDMG[] = {
27 GB_BUS_MAIN, // 0x0000
28 GB_BUS_MAIN, // 0x2000
29 GB_BUS_MAIN, // 0x4000
30 GB_BUS_MAIN, // 0x6000
31 GB_BUS_VRAM, // 0x8000
32 GB_BUS_MAIN, // 0xA000
33 GB_BUS_MAIN, // 0xC000
34 GB_BUS_CPU, // 0xE000
35};
36
37static const enum GBBus _oamBlockCGB[] = {
38 GB_BUS_MAIN, // 0x0000
39 GB_BUS_MAIN, // 0x2000
40 GB_BUS_MAIN, // 0x4000
41 GB_BUS_MAIN, // 0x6000
42 GB_BUS_VRAM, // 0x8000
43 GB_BUS_MAIN, // 0xA000
44 GB_BUS_RAM, // 0xC000
45 GB_BUS_CPU // 0xE000
46};
47
48static void _pristineCow(struct GB* gba);
49
50static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
51 if (UNLIKELY(address >= cpu->memory.activeRegionEnd)) {
52 cpu->memory.setActiveRegion(cpu, address);
53 return cpu->memory.cpuLoad8(cpu, address);
54 }
55 return cpu->memory.activeRegion[address & cpu->memory.activeMask];
56}
57
58static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
59 struct GB* gb = (struct GB*) cpu->master;
60 struct GBMemory* memory = &gb->memory;
61 switch (address >> 12) {
62 case GB_REGION_CART_BANK0:
63 case GB_REGION_CART_BANK0 + 1:
64 case GB_REGION_CART_BANK0 + 2:
65 case GB_REGION_CART_BANK0 + 3:
66 cpu->memory.cpuLoad8 = GBFastLoad8;
67 cpu->memory.activeRegion = memory->romBase;
68 cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
69 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
70 break;
71 case GB_REGION_CART_BANK1:
72 case GB_REGION_CART_BANK1 + 1:
73 case GB_REGION_CART_BANK1 + 2:
74 case GB_REGION_CART_BANK1 + 3:
75 cpu->memory.cpuLoad8 = GBFastLoad8;
76 cpu->memory.activeRegion = memory->romBank;
77 cpu->memory.activeRegionEnd = GB_BASE_VRAM;
78 cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
79 break;
80 default:
81 cpu->memory.cpuLoad8 = GBLoad8;
82 break;
83 }
84}
85
86static void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate);
87static void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate);
88
89void GBMemoryInit(struct GB* gb) {
90 struct LR35902Core* cpu = gb->cpu;
91 cpu->memory.cpuLoad8 = GBLoad8;
92 cpu->memory.load8 = GBLoad8;
93 cpu->memory.store8 = GBStore8;
94 cpu->memory.currentSegment = GBCurrentSegment;
95 cpu->memory.setActiveRegion = GBSetActiveRegion;
96
97 gb->memory.wram = 0;
98 gb->memory.wramBank = 0;
99 gb->memory.rom = 0;
100 gb->memory.romBank = 0;
101 gb->memory.romSize = 0;
102 gb->memory.sram = 0;
103 gb->memory.mbcType = GB_MBC_AUTODETECT;
104 gb->memory.mbcRead = NULL;
105 gb->memory.mbcWrite = NULL;
106
107 gb->memory.rtc = NULL;
108 gb->memory.rotation = NULL;
109 gb->memory.rumble = NULL;
110
111 GBIOInit(gb);
112}
113
114void GBMemoryDeinit(struct GB* gb) {
115 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
116 if (gb->memory.rom) {
117 mappedMemoryFree(gb->memory.rom, gb->memory.romSize);
118 }
119}
120
121void GBMemoryReset(struct GB* gb) {
122 if (gb->memory.wram) {
123 mappedMemoryFree(gb->memory.wram, GB_SIZE_WORKING_RAM);
124 }
125 gb->memory.wram = anonymousMemoryMap(GB_SIZE_WORKING_RAM);
126 if (gb->model >= GB_MODEL_CGB) {
127 uint32_t* base = (uint32_t*) gb->memory.wram;
128 size_t i;
129 uint32_t pattern = 0;
130 for (i = 0; i < GB_SIZE_WORKING_RAM / 4; i += 4) {
131 if ((i & 0x1FF) == 0) {
132 pattern = ~pattern;
133 }
134 base[i + 0] = pattern;
135 base[i + 1] = pattern;
136 base[i + 2] = ~pattern;
137 base[i + 3] = ~pattern;
138 }
139 }
140 GBMemorySwitchWramBank(&gb->memory, 1);
141 gb->memory.romBank = &gb->memory.rom[GB_SIZE_CART_BANK0];
142 gb->memory.currentBank = 1;
143 gb->memory.sramCurrentBank = 0;
144
145 gb->memory.ime = false;
146 gb->memory.ie = 0;
147
148 gb->memory.dmaRemaining = 0;
149 gb->memory.dmaSource = 0;
150 gb->memory.dmaDest = 0;
151 gb->memory.hdmaRemaining = 0;
152 gb->memory.hdmaSource = 0;
153 gb->memory.hdmaDest = 0;
154 gb->memory.isHdma = false;
155
156
157 gb->memory.dmaEvent.context = gb;
158 gb->memory.dmaEvent.name = "GB DMA";
159 gb->memory.dmaEvent.callback = _GBMemoryDMAService;
160 gb->memory.dmaEvent.priority = 0x40;
161 gb->memory.hdmaEvent.context = gb;
162 gb->memory.hdmaEvent.name = "GB HDMA";
163 gb->memory.hdmaEvent.callback = _GBMemoryHDMAService;
164 gb->memory.hdmaEvent.priority = 0x41;
165
166 memset(&gb->memory.hram, 0, sizeof(gb->memory.hram));
167 switch (gb->memory.mbcType) {
168 case GB_MBC1:
169 gb->memory.mbcState.mbc1.mode = 0;
170 break;
171 default:
172 memset(&gb->memory.mbcState, 0, sizeof(gb->memory.mbcState));
173 }
174
175 GBMBCInit(gb);
176 gb->memory.sramBank = gb->memory.sram;
177
178 if (!gb->memory.wram) {
179 GBMemoryDeinit(gb);
180 }
181}
182
183void GBMemorySwitchWramBank(struct GBMemory* memory, int bank) {
184 bank &= 7;
185 if (!bank) {
186 bank = 1;
187 }
188 memory->wramBank = &memory->wram[GB_SIZE_WORKING_RAM_BANK0 * bank];
189 memory->wramCurrentBank = bank;
190}
191
192uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) {
193 struct GB* gb = (struct GB*) cpu->master;
194 struct GBMemory* memory = &gb->memory;
195 if (gb->memory.dmaRemaining) {
196 const enum GBBus* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
197 enum GBBus dmaBus = block[memory->dmaSource >> 13];
198 enum GBBus accessBus = block[address >> 13];
199 if (dmaBus != GB_BUS_CPU && dmaBus == accessBus) {
200 return 0xFF;
201 }
202 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
203 return 0xFF;
204 }
205 }
206 switch (address >> 12) {
207 case GB_REGION_CART_BANK0:
208 case GB_REGION_CART_BANK0 + 1:
209 case GB_REGION_CART_BANK0 + 2:
210 case GB_REGION_CART_BANK0 + 3:
211 return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
212 case GB_REGION_CART_BANK1:
213 case GB_REGION_CART_BANK1 + 1:
214 case GB_REGION_CART_BANK1 + 2:
215 case GB_REGION_CART_BANK1 + 3:
216 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
217 case GB_REGION_VRAM:
218 case GB_REGION_VRAM + 1:
219 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
220 case GB_REGION_EXTERNAL_RAM:
221 case GB_REGION_EXTERNAL_RAM + 1:
222 if (memory->rtcAccess) {
223 return memory->rtcRegs[memory->activeRtcReg];
224 } else if (memory->mbcRead) {
225 return memory->mbcRead(memory, address);
226 } else if (memory->sramAccess && memory->sram) {
227 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
228 } else if (memory->mbcType == GB_HuC3) {
229 return 0x01; // TODO: Is this supposed to be the current SRAM bank?
230 }
231 return 0xFF;
232 case GB_REGION_WORKING_RAM_BANK0:
233 case GB_REGION_WORKING_RAM_BANK0 + 2:
234 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
235 case GB_REGION_WORKING_RAM_BANK1:
236 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
237 default:
238 if (address < GB_BASE_OAM) {
239 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
240 }
241 if (address < GB_BASE_UNUSABLE) {
242 if (gb->video.mode < 2) {
243 return gb->video.oam.raw[address & 0xFF];
244 }
245 return 0xFF;
246 }
247 if (address < GB_BASE_IO) {
248 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
249 return 0xFF;
250 }
251 if (address < GB_BASE_HRAM) {
252 return GBIORead(gb, address & (GB_SIZE_IO - 1));
253 }
254 if (address < GB_BASE_IE) {
255 return memory->hram[address & GB_SIZE_HRAM];
256 }
257 return GBIORead(gb, REG_IE);
258 }
259}
260
261void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
262 struct GB* gb = (struct GB*) cpu->master;
263 struct GBMemory* memory = &gb->memory;
264 if (gb->memory.dmaRemaining) {
265 const enum GBBus* block = gb->model < GB_MODEL_CGB ? _oamBlockDMG : _oamBlockCGB;
266 enum GBBus dmaBus = block[memory->dmaSource >> 13];
267 enum GBBus accessBus = block[address >> 13];
268 if (dmaBus != GB_BUS_CPU && dmaBus == accessBus) {
269 return;
270 }
271 if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) {
272 return;
273 }
274 }
275 switch (address >> 12) {
276 case GB_REGION_CART_BANK0:
277 case GB_REGION_CART_BANK0 + 1:
278 case GB_REGION_CART_BANK0 + 2:
279 case GB_REGION_CART_BANK0 + 3:
280 case GB_REGION_CART_BANK1:
281 case GB_REGION_CART_BANK1 + 1:
282 case GB_REGION_CART_BANK1 + 2:
283 case GB_REGION_CART_BANK1 + 3:
284 memory->mbcWrite(gb, address, value);
285 cpu->memory.setActiveRegion(cpu, cpu->pc);
286 return;
287 case GB_REGION_VRAM:
288 case GB_REGION_VRAM + 1:
289 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) | (GB_SIZE_VRAM_BANK0 * gb->video.vramCurrentBank));
290 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
291 return;
292 case GB_REGION_EXTERNAL_RAM:
293 case GB_REGION_EXTERNAL_RAM + 1:
294 if (memory->rtcAccess) {
295 memory->rtcRegs[memory->activeRtcReg] = value;
296 } else if (memory->sramAccess && memory->sram && memory->mbcType != GB_MBC2) {
297 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
298 } else if (memory->mbcType == GB_MBC7) {
299 GBMBC7Write(memory, address, value);
300 }
301 gb->sramDirty |= GB_SRAM_DIRT_NEW;
302 return;
303 case GB_REGION_WORKING_RAM_BANK0:
304 case GB_REGION_WORKING_RAM_BANK0 + 2:
305 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
306 return;
307 case GB_REGION_WORKING_RAM_BANK1:
308 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
309 return;
310 default:
311 if (address < GB_BASE_OAM) {
312 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
313 } else if (address < GB_BASE_UNUSABLE) {
314 if (gb->video.mode < 2) {
315 gb->video.oam.raw[address & 0xFF] = value;
316 gb->video.renderer->writeOAM(gb->video.renderer, address & 0xFF);
317 }
318 } else if (address < GB_BASE_IO) {
319 mLOG(GB_MEM, GAME_ERROR, "Attempt to write to unusable memory: %04X:%02X", address, value);
320 } else if (address < GB_BASE_HRAM) {
321 GBIOWrite(gb, address & (GB_SIZE_IO - 1), value);
322 } else if (address < GB_BASE_IE) {
323 memory->hram[address & GB_SIZE_HRAM] = value;
324 } else {
325 GBIOWrite(gb, REG_IE, value);
326 }
327 }
328}
329
330int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address) {
331 struct GB* gb = (struct GB*) cpu->master;
332 struct GBMemory* memory = &gb->memory;
333 switch (address >> 12) {
334 case GB_REGION_CART_BANK0:
335 case GB_REGION_CART_BANK0 + 1:
336 case GB_REGION_CART_BANK0 + 2:
337 case GB_REGION_CART_BANK0 + 3:
338 return 0;
339 case GB_REGION_CART_BANK1:
340 case GB_REGION_CART_BANK1 + 1:
341 case GB_REGION_CART_BANK1 + 2:
342 case GB_REGION_CART_BANK1 + 3:
343 return memory->currentBank;
344 case GB_REGION_VRAM:
345 case GB_REGION_VRAM + 1:
346 return gb->video.vramCurrentBank;
347 case GB_REGION_EXTERNAL_RAM:
348 case GB_REGION_EXTERNAL_RAM + 1:
349 return memory->sramCurrentBank;
350 case GB_REGION_WORKING_RAM_BANK0:
351 case GB_REGION_WORKING_RAM_BANK0 + 2:
352 return 0;
353 case GB_REGION_WORKING_RAM_BANK1:
354 return memory->wramCurrentBank;
355 default:
356 return 0;
357 }
358}
359
360uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment) {
361 struct GB* gb = (struct GB*) cpu->master;
362 struct GBMemory* memory = &gb->memory;
363 switch (address >> 12) {
364 case GB_REGION_CART_BANK0:
365 case GB_REGION_CART_BANK0 + 1:
366 case GB_REGION_CART_BANK0 + 2:
367 case GB_REGION_CART_BANK0 + 3:
368 return memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
369 case GB_REGION_CART_BANK1:
370 case GB_REGION_CART_BANK1 + 1:
371 case GB_REGION_CART_BANK1 + 2:
372 case GB_REGION_CART_BANK1 + 3:
373 if (segment < 0) {
374 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
375 } else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
376 return memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
377 } else {
378 return 0xFF;
379 }
380 case GB_REGION_VRAM:
381 case GB_REGION_VRAM + 1:
382 if (segment < 0) {
383 return gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
384 } else if (segment < 2) {
385 return gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment *GB_SIZE_VRAM_BANK0];
386 } else {
387 return 0xFF;
388 }
389 case GB_REGION_EXTERNAL_RAM:
390 case GB_REGION_EXTERNAL_RAM + 1:
391 if (memory->rtcAccess) {
392 return memory->rtcRegs[memory->activeRtcReg];
393 } else if (memory->sramAccess) {
394 if (segment < 0 && memory->sram) {
395 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
396 } else if ((size_t) segment * GB_SIZE_EXTERNAL_RAM < gb->sramSize) {
397 return memory->sram[(address & (GB_SIZE_EXTERNAL_RAM - 1)) + segment *GB_SIZE_EXTERNAL_RAM];
398 } else {
399 return 0xFF;
400 }
401 } else if (memory->mbcRead) {
402 return memory->mbcRead(memory, address);
403 } else if (memory->mbcType == GB_HuC3) {
404 return 0x01; // TODO: Is this supposed to be the current SRAM bank?
405 }
406 return 0xFF;
407 case GB_REGION_WORKING_RAM_BANK0:
408 case GB_REGION_WORKING_RAM_BANK0 + 2:
409 return memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
410 case GB_REGION_WORKING_RAM_BANK1:
411 if (segment < 0) {
412 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
413 } else if (segment < 8) {
414 return memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment *GB_SIZE_WORKING_RAM_BANK0];
415 } else {
416 return 0xFF;
417 }
418 default:
419 if (address < GB_BASE_OAM) {
420 return memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
421 }
422 if (address < GB_BASE_UNUSABLE) {
423 if (gb->video.mode < 2) {
424 return gb->video.oam.raw[address & 0xFF];
425 }
426 return 0xFF;
427 }
428 if (address < GB_BASE_IO) {
429 mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address);
430 return 0xFF;
431 }
432 if (address < GB_BASE_HRAM) {
433 return GBIORead(gb, address & (GB_SIZE_IO - 1));
434 }
435 if (address < GB_BASE_IE) {
436 return memory->hram[address & GB_SIZE_HRAM];
437 }
438 return GBIORead(gb, REG_IE);
439 }
440}
441
442void GBMemoryDMA(struct GB* gb, uint16_t base) {
443 if (base > 0xF100) {
444 return;
445 }
446 mTimingDeschedule(&gb->timing, &gb->memory.dmaEvent);
447 mTimingSchedule(&gb->timing, &gb->memory.dmaEvent, 8);
448 if (gb->cpu->cycles + 8 < gb->cpu->nextEvent) {
449 gb->cpu->nextEvent = gb->cpu->cycles + 8;
450 }
451 gb->memory.dmaSource = base;
452 gb->memory.dmaDest = 0;
453 gb->memory.dmaRemaining = 0xA0;
454}
455
456uint8_t GBMemoryWriteHDMA5(struct GB* gb, uint8_t value) {
457 gb->memory.hdmaSource = gb->memory.io[REG_HDMA1] << 8;
458 gb->memory.hdmaSource |= gb->memory.io[REG_HDMA2];
459 gb->memory.hdmaDest = gb->memory.io[REG_HDMA3] << 8;
460 gb->memory.hdmaDest |= gb->memory.io[REG_HDMA4];
461 gb->memory.hdmaSource &= 0xFFF0;
462 if (gb->memory.hdmaSource >= 0x8000 && gb->memory.hdmaSource < 0xA000) {
463 mLOG(GB_MEM, GAME_ERROR, "Invalid HDMA source: %04X", gb->memory.hdmaSource);
464 return value | 0x80;
465 }
466 gb->memory.hdmaDest &= 0x1FF0;
467 gb->memory.hdmaDest |= 0x8000;
468 bool wasHdma = gb->memory.isHdma;
469 gb->memory.isHdma = value & 0x80;
470 if ((!wasHdma && !gb->memory.isHdma) || gb->video.mode == 0) {
471 if (gb->memory.isHdma) {
472 gb->memory.hdmaRemaining = 0x10;
473 } else {
474 gb->memory.hdmaRemaining = ((value & 0x7F) + 1) * 0x10;
475 }
476 gb->cpuBlocked = true;
477 mTimingSchedule(&gb->timing, &gb->memory.hdmaEvent, 0);
478 } else if (gb->memory.isHdma && !GBRegisterLCDCIsEnable(gb->memory.io[REG_LCDC])) {
479 return 0x80 | ((value + 1) & 0x7F);
480 }
481 return value & 0x7F;
482}
483
484void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate) {
485 struct GB* gb = context;
486 int dmaRemaining = gb->memory.dmaRemaining;
487 gb->memory.dmaRemaining = 0;
488 uint8_t b = GBLoad8(gb->cpu, gb->memory.dmaSource);
489 // TODO: Can DMA write OAM during modes 2-3?
490 gb->video.oam.raw[gb->memory.dmaDest] = b;
491 gb->video.renderer->writeOAM(gb->video.renderer, gb->memory.dmaDest);
492 ++gb->memory.dmaSource;
493 ++gb->memory.dmaDest;
494 gb->memory.dmaRemaining = dmaRemaining - 1;
495 if (gb->memory.dmaRemaining) {
496 mTimingSchedule(timing, &gb->memory.dmaEvent, 4 - cyclesLate);
497 }
498}
499
500void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cyclesLate) {
501 struct GB* gb = context;
502 gb->cpuBlocked = true;
503 uint8_t b = gb->cpu->memory.load8(gb->cpu, gb->memory.hdmaSource);
504 gb->cpu->memory.store8(gb->cpu, gb->memory.hdmaDest, b);
505 ++gb->memory.hdmaSource;
506 ++gb->memory.hdmaDest;
507 --gb->memory.hdmaRemaining;
508 if (gb->memory.hdmaRemaining) {
509 mTimingDeschedule(timing, &gb->memory.hdmaEvent);
510 mTimingSchedule(timing, &gb->memory.hdmaEvent, 2 - cyclesLate);
511 } else {
512 gb->cpuBlocked = false;
513 gb->memory.io[REG_HDMA1] = gb->memory.hdmaSource >> 8;
514 gb->memory.io[REG_HDMA2] = gb->memory.hdmaSource;
515 gb->memory.io[REG_HDMA3] = gb->memory.hdmaDest >> 8;
516 gb->memory.io[REG_HDMA4] = gb->memory.hdmaDest;
517 if (gb->memory.isHdma) {
518 --gb->memory.io[REG_HDMA5];
519 if (gb->memory.io[REG_HDMA5] == 0xFF) {
520 gb->memory.isHdma = false;
521 }
522 } else {
523 gb->memory.io[REG_HDMA5] = 0xFF;
524 }
525 }
526}
527
528void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment) {
529 struct GB* gb = (struct GB*) cpu->master;
530 struct GBMemory* memory = &gb->memory;
531 int8_t oldValue = -1;
532
533 switch (address >> 12) {
534 case GB_REGION_CART_BANK0:
535 case GB_REGION_CART_BANK0 + 1:
536 case GB_REGION_CART_BANK0 + 2:
537 case GB_REGION_CART_BANK0 + 3:
538 _pristineCow(gb);
539 oldValue = memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)];
540 memory->romBase[address & (GB_SIZE_CART_BANK0 - 1)] = value;
541 break;
542 case GB_REGION_CART_BANK1:
543 case GB_REGION_CART_BANK1 + 1:
544 case GB_REGION_CART_BANK1 + 2:
545 case GB_REGION_CART_BANK1 + 3:
546 _pristineCow(gb);
547 if (segment < 0) {
548 oldValue = memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
549 memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)] = value;
550 } else if ((size_t) segment * GB_SIZE_CART_BANK0 < memory->romSize) {
551 oldValue = memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0];
552 memory->rom[(address & (GB_SIZE_CART_BANK0 - 1)) + segment * GB_SIZE_CART_BANK0] = value;
553 } else {
554 return;
555 }
556 break;
557 case GB_REGION_VRAM:
558 case GB_REGION_VRAM + 1:
559 if (segment < 0) {
560 oldValue = gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)];
561 gb->video.vramBank[address & (GB_SIZE_VRAM_BANK0 - 1)] = value;
562 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) + GB_SIZE_VRAM_BANK0 * gb->video.vramCurrentBank);
563 } else if (segment < 2) {
564 oldValue = gb->video.vram[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0];
565 gb->video.vramBank[(address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0] = value;
566 gb->video.renderer->writeVRAM(gb->video.renderer, (address & (GB_SIZE_VRAM_BANK0 - 1)) + segment * GB_SIZE_VRAM_BANK0);
567 } else {
568 return;
569 }
570 break;
571 case GB_REGION_EXTERNAL_RAM:
572 case GB_REGION_EXTERNAL_RAM + 1:
573 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
574 return;
575 case GB_REGION_WORKING_RAM_BANK0:
576 case GB_REGION_WORKING_RAM_BANK0 + 2:
577 oldValue = memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
578 memory->wram[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
579 break;
580 case GB_REGION_WORKING_RAM_BANK1:
581 if (segment < 0) {
582 oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
583 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
584 } else if (segment < 8) {
585 oldValue = memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0];
586 memory->wram[(address & (GB_SIZE_WORKING_RAM_BANK0 - 1)) + segment * GB_SIZE_WORKING_RAM_BANK0] = value;
587 } else {
588 return;
589 }
590 break;
591 default:
592 if (address < GB_BASE_OAM) {
593 oldValue = memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)];
594 memory->wramBank[address & (GB_SIZE_WORKING_RAM_BANK0 - 1)] = value;
595 } else if (address < GB_BASE_UNUSABLE) {
596 oldValue = gb->video.oam.raw[address & 0xFF];
597 gb->video.oam.raw[address & 0xFF] = value;
598 gb->video.renderer->writeOAM(gb->video.renderer, address & 0xFF);
599 } else if (address < GB_BASE_HRAM) {
600 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
601 return;
602 } else if (address < GB_BASE_IE) {
603 oldValue = memory->hram[address & GB_SIZE_HRAM];
604 memory->hram[address & GB_SIZE_HRAM] = value;
605 } else {
606 mLOG(GB_MEM, STUB, "Unimplemented memory Patch8: 0x%08X", address);
607 return;
608 }
609 }
610 if (old) {
611 *old = oldValue;
612 }
613}
614
615void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state) {
616 const struct GBMemory* memory = &gb->memory;
617 memcpy(state->wram, memory->wram, GB_SIZE_WORKING_RAM);
618 memcpy(state->hram, memory->hram, GB_SIZE_HRAM);
619 STORE_16LE(memory->currentBank, 0, &state->memory.currentBank);
620 state->memory.wramCurrentBank = memory->wramCurrentBank;
621 state->memory.sramCurrentBank = memory->sramCurrentBank;
622
623 STORE_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
624 STORE_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
625
626 STORE_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
627 STORE_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
628
629 STORE_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
630 state->memory.dmaRemaining = memory->dmaRemaining;
631 memcpy(state->memory.rtcRegs, memory->rtcRegs, sizeof(state->memory.rtcRegs));
632
633 STORE_32LE(memory->dmaEvent.when - mTimingCurrentTime(&gb->timing), 0, &state->memory.dmaNext);
634 STORE_32LE(memory->hdmaEvent.when - mTimingCurrentTime(&gb->timing), 0, &state->memory.hdmaNext);
635
636 GBSerializedMemoryFlags flags = 0;
637 flags = GBSerializedMemoryFlagsSetSramAccess(flags, memory->sramAccess);
638 flags = GBSerializedMemoryFlagsSetRtcAccess(flags, memory->rtcAccess);
639 flags = GBSerializedMemoryFlagsSetRtcLatched(flags, memory->rtcLatched);
640 flags = GBSerializedMemoryFlagsSetIme(flags, memory->ime);
641 flags = GBSerializedMemoryFlagsSetIsHdma(flags, memory->isHdma);
642 flags = GBSerializedMemoryFlagsSetActiveRtcReg(flags, memory->activeRtcReg);
643 STORE_16LE(flags, 0, &state->memory.flags);
644
645 switch (memory->mbcType) {
646 case GB_MBC1:
647 state->memory.mbc1.mode = memory->mbcState.mbc1.mode;
648 state->memory.mbc1.multicartStride = memory->mbcState.mbc1.multicartStride;
649 break;
650 case GB_MBC3_RTC:
651 STORE_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
652 break;
653 case GB_MBC7:
654 state->memory.mbc7.state = memory->mbcState.mbc7.state;
655 state->memory.mbc7.eeprom = memory->mbcState.mbc7.eeprom;
656 state->memory.mbc7.address = memory->mbcState.mbc7.address;
657 state->memory.mbc7.access = memory->mbcState.mbc7.access;
658 state->memory.mbc7.latch = memory->mbcState.mbc7.latch;
659 state->memory.mbc7.srBits = memory->mbcState.mbc7.srBits;
660 STORE_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
661 STORE_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
662 break;
663 default:
664 break;
665 }
666}
667
668void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state) {
669 struct GBMemory* memory = &gb->memory;
670 memcpy(memory->wram, state->wram, GB_SIZE_WORKING_RAM);
671 memcpy(memory->hram, state->hram, GB_SIZE_HRAM);
672 LOAD_16LE(memory->currentBank, 0, &state->memory.currentBank);
673 memory->wramCurrentBank = state->memory.wramCurrentBank;
674 memory->sramCurrentBank = state->memory.sramCurrentBank;
675
676 GBMBCSwitchBank(gb, memory->currentBank);
677 GBMemorySwitchWramBank(memory, memory->wramCurrentBank);
678 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
679
680 LOAD_16LE(memory->dmaSource, 0, &state->memory.dmaSource);
681 LOAD_16LE(memory->dmaDest, 0, &state->memory.dmaDest);
682
683 LOAD_16LE(memory->hdmaSource, 0, &state->memory.hdmaSource);
684 LOAD_16LE(memory->hdmaDest, 0, &state->memory.hdmaDest);
685
686 LOAD_16LE(memory->hdmaRemaining, 0, &state->memory.hdmaRemaining);
687 memory->dmaRemaining = state->memory.dmaRemaining;
688 memcpy(memory->rtcRegs, state->memory.rtcRegs, sizeof(state->memory.rtcRegs));
689
690 uint32_t when;
691 LOAD_32LE(when, 0, &state->memory.dmaNext);
692 if (memory->dmaRemaining) {
693 mTimingSchedule(&gb->timing, &memory->dmaEvent, when);
694 }
695 LOAD_32LE(when, 0, &state->memory.hdmaNext);
696 if (memory->hdmaRemaining) {
697 mTimingSchedule(&gb->timing, &memory->hdmaEvent, when);
698 }
699
700 GBSerializedMemoryFlags flags;
701 LOAD_16LE(flags, 0, &state->memory.flags);
702 memory->sramAccess = GBSerializedMemoryFlagsGetSramAccess(flags);
703 memory->rtcAccess = GBSerializedMemoryFlagsGetRtcAccess(flags);
704 memory->rtcLatched = GBSerializedMemoryFlagsGetRtcLatched(flags);
705 memory->ime = GBSerializedMemoryFlagsGetIme(flags);
706 memory->isHdma = GBSerializedMemoryFlagsGetIsHdma(flags);
707 memory->activeRtcReg = GBSerializedMemoryFlagsGetActiveRtcReg(flags);
708
709 switch (memory->mbcType) {
710 case GB_MBC1:
711 memory->mbcState.mbc1.mode = state->memory.mbc1.mode;
712 memory->mbcState.mbc1.multicartStride = state->memory.mbc1.multicartStride;
713 if (memory->mbcState.mbc1.mode) {
714 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
715 }
716 break;
717 case GB_MBC3_RTC:
718 LOAD_64LE(gb->memory.rtcLastLatch, 0, &state->memory.rtc.lastLatch);
719 break;
720 case GB_MBC7:
721 memory->mbcState.mbc7.state = state->memory.mbc7.state;
722 memory->mbcState.mbc7.eeprom = state->memory.mbc7.eeprom;
723 memory->mbcState.mbc7.address = state->memory.mbc7.address & 0x7F;
724 memory->mbcState.mbc7.access = state->memory.mbc7.access;
725 memory->mbcState.mbc7.latch = state->memory.mbc7.latch;
726 memory->mbcState.mbc7.srBits = state->memory.mbc7.srBits;
727 LOAD_16LE(memory->mbcState.mbc7.sr, 0, &state->memory.mbc7.sr);
728 LOAD_32LE(memory->mbcState.mbc7.writable, 0, &state->memory.mbc7.writable);
729 break;
730 default:
731 break;
732 }
733}
734
735void _pristineCow(struct GB* gb) {
736 if (!gb->isPristine) {
737 return;
738 }
739 void* newRom = anonymousMemoryMap(GB_SIZE_CART_MAX);
740 memcpy(newRom, gb->memory.rom, gb->memory.romSize);
741 memset(((uint8_t*) newRom) + gb->memory.romSize, 0xFF, GB_SIZE_CART_MAX - gb->memory.romSize);
742 if (gb->memory.rom == gb->memory.romBase) {
743 gb->memory.romBase = newRom;
744 }
745 gb->memory.rom = newRom;
746 GBMBCSwitchBank(gb, gb->memory.currentBank);
747 gb->isPristine = false;
748}