src/arm/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 cpu->currentPC = cpu->gprs[ARM_PC] - WORD_SIZE_THUMB;
9 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
10 uint16_t opcode;
11 LOAD_16(opcode, cpu->currentPC & cpu->memory->activeMask, cpu->memory->activeRegion);
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
24
25#define THUMB_SUBTRACTION_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D); \
28 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
29 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
30
31#define THUMB_NEUTRAL_S(M, N, D) \
32 cpu->cpsr.n = ARM_SIGN(D); \
33 cpu->cpsr.z = !(D);
34
35#define THUMB_ADDITION(D, M, N) \
36 int n = N; \
37 int m = M; \
38 D = M + N; \
39 THUMB_ADDITION_S(m, n, D)
40
41#define THUMB_SUBTRACTION(D, M, N) \
42 int n = N; \
43 int m = M; \
44 D = M - N; \
45 THUMB_SUBTRACTION_S(m, n, D)
46
47#define THUMB_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles16)
48
49#define THUMB_STORE_POST_BODY \
50 currentCycles += cpu->memory->activeNonseqCycles16 - cpu->memory->activePrefetchCycles16;
51
52#define APPLY(F, ...) F(__VA_ARGS__)
53
54#define COUNT_1(EMITTER, PREFIX, ...) \
55 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
56 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
57
58#define COUNT_2(EMITTER, PREFIX, ...) \
59 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
60 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
61 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
62
63#define COUNT_3(EMITTER, PREFIX, ...) \
64 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
65 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
66 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
67 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
68 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
69
70#define COUNT_4(EMITTER, PREFIX, ...) \
71 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
72 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
73 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
74 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
75 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
76 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
77 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
78 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
79 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
80
81#define COUNT_5(EMITTER, PREFIX, ...) \
82 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
83 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
84 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
85 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
86 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
87 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
88 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
89 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
90 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
91 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
92 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
93 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
94 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
95 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
96 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
97 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
98 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
99
100#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
101 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
102 int currentCycles = THUMB_PREFETCH_CYCLES; \
103 BODY; \
104 cpu->cycles += currentCycles; \
105 }
106
107#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
108 DEFINE_INSTRUCTION_THUMB(NAME, \
109 int immediate = IMMEDIATE; \
110 int rd = opcode & 0x0007; \
111 int rm = (opcode >> 3) & 0x0007; \
112 BODY;)
113
114#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
115 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
116
117DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
118 if (!immediate) {
119 cpu->gprs[rd] = cpu->gprs[rm];
120 } else {
121 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
122 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
123 }
124 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
125
126DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
127 if (!immediate) {
128 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
129 cpu->gprs[rd] = 0;
130 } else {
131 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
132 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
133 }
134 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
135
136DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
137 if (!immediate) {
138 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
139 if (cpu->cpsr.c) {
140 cpu->gprs[rd] = 0xFFFFFFFF;
141 } else {
142 cpu->gprs[rd] = 0;
143 }
144 } else {
145 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
146 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
147 }
148 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
149
150DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4, ¤tCycles))
151DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rm] + immediate, ¤tCycles))
152DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rm] + immediate * 2, ¤tCycles))
153DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
154DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
155DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
156
157#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
158 DEFINE_INSTRUCTION_THUMB(NAME, \
159 int rm = RM; \
160 int rd = opcode & 0x0007; \
161 int rn = (opcode >> 3) & 0x0007; \
162 BODY;)
163
164#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
165 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
166
167DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
168DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
169
170#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
171 DEFINE_INSTRUCTION_THUMB(NAME, \
172 int immediate = IMMEDIATE; \
173 int rd = opcode & 0x0007; \
174 int rn = (opcode >> 3) & 0x0007; \
175 BODY;)
176
177#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
178 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
179
180DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
181DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
182
183#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
184 DEFINE_INSTRUCTION_THUMB(NAME, \
185 int rd = RD; \
186 int immediate = opcode & 0x00FF; \
187 BODY;)
188
189#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
190 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
191
192DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
193DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
194DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
195DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
196
197#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
198 DEFINE_INSTRUCTION_THUMB(NAME, \
199 int rd = opcode & 0x0007; \
200 int rn = (opcode >> 3) & 0x0007; \
201 BODY;)
202
203DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
204DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
205DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
206 int rs = cpu->gprs[rn] & 0xFF;
207 if (rs) {
208 if (rs < 32) {
209 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
210 cpu->gprs[rd] <<= rs;
211 } else {
212 if (rs > 32) {
213 cpu->cpsr.c = 0;
214 } else {
215 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
216 }
217 cpu->gprs[rd] = 0;
218 }
219 }
220 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
221
222DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
223 int rs = cpu->gprs[rn] & 0xFF;
224 if (rs) {
225 if (rs < 32) {
226 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
227 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
228 } else {
229 if (rs > 32) {
230 cpu->cpsr.c = 0;
231 } else {
232 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
233 }
234 cpu->gprs[rd] = 0;
235 }
236 }
237 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
238
239DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
240 int rs = cpu->gprs[rn] & 0xFF;
241 if (rs) {
242 if (rs < 32) {
243 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
244 cpu->gprs[rd] >>= rs;
245 } else {
246 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
247 if (cpu->cpsr.c) {
248 cpu->gprs[rd] = 0xFFFFFFFF;
249 } else {
250 cpu->gprs[rd] = 0;
251 }
252 }
253 }
254 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
255
256DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
257 int n = cpu->gprs[rn];
258 int d = cpu->gprs[rd];
259 cpu->gprs[rd] = d + n + cpu->cpsr.c;
260 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
261
262DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
263 int n = cpu->gprs[rn] + !cpu->cpsr.c;
264 int d = cpu->gprs[rd];
265 cpu->gprs[rd] = d - n;
266 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
267DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
268 int rs = cpu->gprs[rn] & 0xFF;
269 if (rs) {
270 int r4 = rs & 0x1F;
271 if (r4 > 0) {
272 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
273 cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4);
274 } else {
275 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
276 }
277 }
278 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
279DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
280DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
281DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
282DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
283DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
284DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rn]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
285DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
286DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
287
288#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
289 DEFINE_INSTRUCTION_THUMB(NAME, \
290 int rd = (opcode & 0x0007) | H1; \
291 int rm = ((opcode >> 3) & 0x0007) | H2; \
292 BODY;)
293
294#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
295 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
296 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
297 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
298 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
299
300DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
301 cpu->gprs[rd] += cpu->gprs[rm];
302 if (rd == ARM_PC) {
303 THUMB_WRITE_PC;
304 })
305
306DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
307DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
308 cpu->gprs[rd] = cpu->gprs[rm];
309 if (rd == ARM_PC) {
310 THUMB_WRITE_PC;
311 })
312
313#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
314 DEFINE_INSTRUCTION_THUMB(NAME, \
315 int rd = RD; \
316 int immediate = (opcode & 0x00FF) << 2; \
317 BODY;)
318
319#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
320 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
321
322DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles))
323DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate, ¤tCycles))
324DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
325
326DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
327DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
328
329#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
330 DEFINE_INSTRUCTION_THUMB(NAME, \
331 int rm = RM; \
332 int rd = opcode & 0x0007; \
333 int rn = (opcode >> 3) & 0x0007; \
334 BODY;)
335
336#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
337 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
338
339DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
340DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
341DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
342DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
343DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
344DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory->store32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
345DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory->store8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
346DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory->store16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
347
348#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
349 DEFINE_INSTRUCTION_THUMB(NAME, \
350 int rn = RN; \
351 UNUSED(rn); \
352 int rs = opcode & 0xFF; \
353 int32_t address = ADDRESS; \
354 int m; \
355 int i; \
356 int total = 0; \
357 PRE_BODY; \
358 for LOOP { \
359 if (rs & m) { \
360 BODY; \
361 address OP 4; \
362 ++total; \
363 } \
364 } \
365 POST_BODY; \
366 currentCycles += cpu->memory->waitMultiple(cpu->memory, address, total); \
367 WRITEBACK;)
368
369#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
370 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
371
372DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
373 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
374 if (!((1 << rn) & rs)) {
375 cpu->gprs[rn] = address;
376 })
377
378DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
379 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
380 THUMB_STORE_POST_BODY;
381 cpu->gprs[rn] = address;)
382
383#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
384 DEFINE_INSTRUCTION_THUMB(B ## COND, \
385 if (ARM_COND_ ## COND) { \
386 int8_t immediate = opcode; \
387 cpu->gprs[ARM_PC] += immediate << 1; \
388 THUMB_WRITE_PC; \
389 })
390
391DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
392DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
393DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
394DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
395DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
396DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
397DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
398DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
399DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
400DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
401DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
402DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
403DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
404DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
405
406DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
407DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
408
409DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
410 opcode & 0x00FF,
411 cpu->gprs[ARM_SP],
412 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
413 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
414 +=,
415 , ,
416 cpu->gprs[ARM_SP] = address)
417
418DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
419 opcode & 0x00FF,
420 cpu->gprs[ARM_SP],
421 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
422 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
423 +=,
424 ,
425 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address, 0) & 0xFFFFFFFE;
426 address += 4;,
427 cpu->gprs[ARM_SP] = address;
428 THUMB_WRITE_PC;)
429
430DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
431 opcode & 0x00FF,
432 cpu->gprs[ARM_SP] - 4,
433 (m = 0x80, i = 7; m; m >>= 1, --i),
434 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
435 -=,
436 ,
437 THUMB_STORE_POST_BODY,
438 cpu->gprs[ARM_SP] = address + 4)
439
440DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
441 opcode & 0x00FF,
442 cpu->gprs[ARM_SP] - 4,
443 (m = 0x80, i = 7; m; m >>= 1, --i),
444 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
445 -=,
446 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR], 0);
447 address -= 4;,
448 THUMB_STORE_POST_BODY,
449 cpu->gprs[ARM_SP] = address + 4)
450
451DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
452DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
453DEFINE_INSTRUCTION_THUMB(B,
454 int16_t immediate = (opcode & 0x07FF) << 5;
455 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
456 THUMB_WRITE_PC;)
457
458DEFINE_INSTRUCTION_THUMB(BL1,
459 int16_t immediate = (opcode & 0x07FF) << 5;
460 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
461
462DEFINE_INSTRUCTION_THUMB(BL2,
463 uint16_t immediate = (opcode & 0x07FF) << 1;
464 uint32_t pc = cpu->gprs[ARM_PC];
465 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
466 cpu->gprs[ARM_LR] = pc - 1;
467 THUMB_WRITE_PC;)
468
469DEFINE_INSTRUCTION_THUMB(BX,
470 int rm = (opcode >> 3) & 0xF;
471 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
472 int misalign = 0;
473 if (rm == ARM_PC) {
474 misalign = cpu->gprs[rm] & 0x00000002;
475 }
476 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
477 if (cpu->executionMode == MODE_THUMB) {
478 THUMB_WRITE_PC;
479 } else {
480 ARM_WRITE_PC;
481 })
482
483DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF))
484
485#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
486 EMITTER ## NAME
487
488#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
489 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
490 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
491 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
492 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
493
494#define DUMMY(X, ...) X,
495#define DUMMY_4(...) \
496 DUMMY(__VA_ARGS__) \
497 DUMMY(__VA_ARGS__) \
498 DUMMY(__VA_ARGS__) \
499 DUMMY(__VA_ARGS__)
500
501#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
502 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
503 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
504 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
505 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
506 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
507 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
508 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
509 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
510 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
511 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
512 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
513 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
514 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
515 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
516 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
517 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
518 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
519 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
520 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
521 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
522 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
523 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
524 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
525 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
526 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
527 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
528 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
529 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
530 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
531 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
532 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
533 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
534 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
535 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
536 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
537 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
538 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
539 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
540 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
541 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
542 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
543 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
544 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
545 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
546 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
547 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
548 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
549 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
550 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
551 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
552 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
553 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
554 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
555 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
556 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
557 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
558 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
559 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
560 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
561 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
562 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
563 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
564 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
565 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
566 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
567 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
568 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
569 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
570 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
571 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
572 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
573 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
574 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
575 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
576 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
577 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
578 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
579 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
580 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
581 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
582 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
583 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
584 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
585 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
586 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
587 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
588 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
589 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
590 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
591 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
592 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
593
594static const ThumbInstruction _thumbTable[0x400] = {
595 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
596};