src/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
24
25#define THUMB_SUBTRACTION_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D); \
28 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
29 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
30
31#define THUMB_NEUTRAL_S(M, N, D) \
32 cpu->cpsr.n = ARM_SIGN(D); \
33 cpu->cpsr.z = !(D);
34
35#define THUMB_ADDITION(D, M, N) \
36 int n = N; \
37 int m = M; \
38 D = M + N; \
39 THUMB_ADDITION_S(m, n, D)
40
41#define APPLY(F, ...) F(__VA_ARGS__)
42
43#define COUNT_1(EMITTER, PREFIX, ...) \
44 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
45 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
46
47#define COUNT_2(EMITTER, PREFIX, ...) \
48 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
49 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
50 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
51
52#define COUNT_3(EMITTER, PREFIX, ...) \
53 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
54 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
55 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
56 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
57 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
58
59#define COUNT_4(EMITTER, PREFIX, ...) \
60 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
61 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
62 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
63 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
64 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
65 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
66 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
67 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
68 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
69
70#define COUNT_5(EMITTER, PREFIX, ...) \
71 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
72 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
73 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
74 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
75 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
76 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
77 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
78 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
79 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
80 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
81 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
82 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
83 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
84 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
85 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
86 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
87 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
88
89#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
90 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
91 BODY; \
92 }
93
94#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
95 DEFINE_INSTRUCTION_THUMB(NAME, \
96 int immediate = IMMEDIATE; \
97 int rd = opcode & 0x0007; \
98 int rm = (opcode >> 3) & 0x0007; \
99 BODY;)
100
101#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
102 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
103
104DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
105 if (!immediate) { \
106 cpu->gprs[rd] = cpu->gprs[rm]; \
107 } else { \
108 cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \
109 cpu->gprs[rd] = cpu->gprs[rm] << immediate; \
110 } \
111 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
112
113DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
114 if (!immediate) { \
115 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]); \
116 cpu->gprs[rd] = 0; \
117 } else { \
118 cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); \
119 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate; \
120 } \
121 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
122
123DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
124
125DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
126DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
127DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
128DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
129DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd]))
130DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd]))
131
132#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
133 DEFINE_INSTRUCTION_THUMB(NAME, \
134 int rm = RM; \
135 int rd = opcode & 0x0007; \
136 int rn = (opcode >> 3) & 0x0007; \
137 BODY;)
138
139#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
140 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
141
142DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
143DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
144
145#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
146 DEFINE_INSTRUCTION_THUMB(NAME, \
147 int immediate = IMMEDIATE; \
148 int rd = opcode & 0x0007; \
149 int rn = (opcode >> 3) & 0x0007; \
150 BODY;)
151
152#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
153 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
154
155DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
156
157DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
158
159#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
160 DEFINE_INSTRUCTION_THUMB(NAME, \
161 int rd = RD; \
162 int immediate = opcode & 0x00FF; \
163 BODY;)
164
165#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
166 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
167
168DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
169
170
171DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
172DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
173DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
174
175#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
176 DEFINE_INSTRUCTION_THUMB(NAME, \
177 int rd = opcode & 0x0007; \
178 int rn = (opcode >> 3) & 0x0007; \
179 BODY;)
180
181DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
182DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
183DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
184DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, \
185 int rs = cpu->gprs[rn] & 0xFF; \
186 if (rs) { \
187 if (rs < 32) { \
188 cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \
189 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs; \
190 } else { \
191 if (rs > 32) { \
192 cpu->cpsr.c = 0; \
193 } else { \
194 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \
195 } \
196 cpu->gprs[rd] = 0; \
197 } \
198 } \
199 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
200
201DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, \
202 int rs = cpu->gprs[rn] & 0xFF; \
203 if (rs) { \
204 if (rs < 32) { \
205 cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \
206 cpu->gprs[rd] >>= rs; \
207 } else { \
208 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \
209 if (cpu->cpsr.c) { \
210 cpu->gprs[rd] = 0xFFFFFFFF; \
211 } else { \
212 cpu->gprs[rd] = 0; \
213 } \
214 } \
215 } \
216 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
217
218DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
219DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
220DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
221DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
222DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
223DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
224DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
225DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
226DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
227DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
228DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
229
230#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
231 DEFINE_INSTRUCTION_THUMB(NAME, \
232 int rd = opcode & 0x0007 | H1; \
233 int rm = (opcode >> 3) & 0x0007 | H2; \
234 BODY;)
235
236#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
237 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
238 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
239 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
240 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
241
242DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, cpu->gprs[rd] += cpu->gprs[rm])
243DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
244DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
245
246#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
247 DEFINE_INSTRUCTION_THUMB(NAME, \
248 int rd = RD; \
249 int immediate = (opcode & 0x00FF) << 2; \
250 BODY;)
251
252#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
253 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
254
255DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_PC] + immediate))
256DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate))
257DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd]))
258
259DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
260DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
261
262#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
263 DEFINE_INSTRUCTION_THUMB(NAME, \
264 int rm = RM; \
265 BODY;)
266
267#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
268 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
269
270DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
271DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
272DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
273DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
274DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
275DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
276DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
277DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
278
279#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
280 DEFINE_INSTRUCTION_THUMB(NAME, \
281 int rn = (opcode >> 8) & 0x000F; \
282 int rs = RS; \
283 int32_t address = ADDRESS; \
284 int m; \
285 int i; \
286 PRE_BODY; \
287 for LOOP { \
288 if (rs & m) { \
289 BODY; \
290 address OP 4; \
291 } \
292 } \
293 POST_BODY; \
294 WRITEBACK;)
295
296#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
297 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
298
299DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
300 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
301 if (!((1 << rn) & rs)) { \
302 cpu->gprs[rn] = address; \
303 })
304
305DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
306 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
307 cpu->gprs[rn] = address)
308
309#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
310 DEFINE_INSTRUCTION_THUMB(B ## COND, \
311 if (ARM_COND_ ## COND) { \
312 int8_t immediate = opcode; \
313 cpu->gprs[ARM_PC] += immediate << 1; \
314 THUMB_WRITE_PC; \
315 })
316
317DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
318DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
319DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
320DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
321DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
322DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
323DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
324DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
325DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
326DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
327DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
328DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
329DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
330DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
331
332DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
333DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
334
335DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
336 opcode & 0x00FF, \
337 cpu->gprs[ARM_SP], \
338 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
339 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
340 +=, \
341 , , \
342 cpu->gprs[ARM_SP] = address)
343
344DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
345 opcode & 0x00FF, \
346 cpu->gprs[ARM_SP], \
347 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
348 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
349 +=, \
350 , \
351 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
352 address += 4;, \
353 cpu->gprs[ARM_SP] = address)
354
355DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
356 opcode & 0x00FF, \
357 cpu->gprs[ARM_SP] - 4, \
358 (m = 0x80, i = 7; m; m >>= 1, --i), \
359 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
360 -=, \
361 , , \
362 cpu->gprs[ARM_SP] = address + 4)
363
364DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
365 opcode & 0x00FF, \
366 cpu->gprs[ARM_SP] - 4, \
367 (m = 0x80, i = 7; m; m >>= 1, --i), \
368 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
369 -=, \
370 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
371 address -= 4;, \
372 , \
373 cpu->gprs[ARM_SP] = address + 4)
374
375DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
376DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
377DEFINE_INSTRUCTION_THUMB(B, \
378 int16_t immediate = (opcode & 0x07FF) << 5; \
379 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4); \
380 THUMB_WRITE_PC;)
381
382DEFINE_INSTRUCTION_THUMB(BL1, \
383 int16_t immediate = (opcode & 0x07FF) << 5; \
384 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
385
386DEFINE_INSTRUCTION_THUMB(BL2, \
387 uint16_t immediate = (opcode & 0x07FF) << 1; \
388 uint32_t pc = cpu->gprs[ARM_PC]; \
389 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
390 cpu->gprs[ARM_LR] = pc - 1; \
391 THUMB_WRITE_PC;)
392
393DEFINE_INSTRUCTION_THUMB(BX, \
394 int rm = opcode & 0x0000000F; \
395 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
396 int misalign = 0;
397 if (rm == ARM_PC) {
398 misalign = cpu->gprs[rm] & 0x00000002;
399 }
400 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE - misalign; \
401 if (cpu->executionMode == MODE_THUMB) { \
402 THUMB_WRITE_PC; \
403 } else { \
404 ARM_WRITE_PC; \
405 })
406
407DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
408
409#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
410 EMITTER ## NAME
411
412#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
413 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
414 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
415 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
416 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
417
418#define DUMMY(X, ...) X,
419#define DUMMY_4(...) \
420 DUMMY(__VA_ARGS__) \
421 DUMMY(__VA_ARGS__) \
422 DUMMY(__VA_ARGS__) \
423 DUMMY(__VA_ARGS__)
424
425#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
426 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
427 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
428 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
429 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
430 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
431 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
432 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
433 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
434 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
435 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
436 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
437 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
438 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
439 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
440 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
441 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
442 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
443 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
444 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
445 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
446 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
447 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
448 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
449 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
450 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
451 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
452 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
453 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
454 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
455 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
456 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
457 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
458 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
459 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
460 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
461 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
462 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
463 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
464 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
465 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
466 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
467 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
468 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
469 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
470 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
471 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
472 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
473 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
474 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
475 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
476 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
477 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
478 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
479 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
480 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
481 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
482 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
483 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
484 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
485 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
486 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
487 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
488 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
489 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
490 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
491 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
492 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
493 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
494 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
495 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
496 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
497 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
498 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
499 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
500 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
501 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
502 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
503 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
504 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
505 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
506 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
507 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
508 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
509 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
510 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
511 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
512 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
513 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
514 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
515 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
516 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
517
518static const ThumbInstruction _thumbTable[0x400] = {
519 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
520};