src/gba/dma.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gba/dma.h>
7
8#include <mgba/internal/gba/gba.h>
9#include <mgba/internal/gba/io.h>
10
11static void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate);
12
13static void GBADMAService(struct GBA* gba, int number, struct GBADMA* info);
14
15static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
16
17void GBADMAInit(struct GBA* gba) {
18 gba->memory.dmaEvent.name = "GBA DMA";
19 gba->memory.dmaEvent.callback = _dmaEvent;
20 gba->memory.dmaEvent.context = gba;
21 gba->memory.dmaEvent.priority = 0x40;
22}
23
24void GBADMAReset(struct GBA* gba) {
25 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
26 int i;
27 for (i = 0; i < 4; ++i) {
28 gba->memory.dma[i].count = 0x4000;
29 }
30 gba->memory.dma[3].count = 0x10000;
31 gba->memory.activeDMA = -1;
32}
33static bool _isValidDMASAD(int dma, uint32_t address) {
34 if (dma == 0 && address >= BASE_CART0 && address < BASE_CART_SRAM) {
35 return false;
36 }
37 return address >= BASE_WORKING_RAM;
38}
39
40static bool _isValidDMADAD(int dma, uint32_t address) {
41 return dma == 3 || address < BASE_CART0;
42}
43
44uint32_t GBADMAWriteSAD(struct GBA* gba, int dma, uint32_t address) {
45 struct GBAMemory* memory = &gba->memory;
46 address &= 0x0FFFFFFE;
47 if (_isValidDMASAD(dma, address)) {
48 memory->dma[dma].source = address;
49 } else {
50 memory->dma[dma].source = 0;
51 }
52 return memory->dma[dma].source;
53}
54
55uint32_t GBADMAWriteDAD(struct GBA* gba, int dma, uint32_t address) {
56 struct GBAMemory* memory = &gba->memory;
57 address &= 0x0FFFFFFE;
58 if (_isValidDMADAD(dma, address)) {
59 memory->dma[dma].dest = address;
60 }
61 return memory->dma[dma].dest;
62}
63
64void GBADMAWriteCNT_LO(struct GBA* gba, int dma, uint16_t count) {
65 struct GBAMemory* memory = &gba->memory;
66 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
67}
68
69uint16_t GBADMAWriteCNT_HI(struct GBA* gba, int dma, uint16_t control) {
70 struct GBAMemory* memory = &gba->memory;
71 struct GBADMA* currentDma = &memory->dma[dma];
72 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
73 if (dma < 3) {
74 control &= 0xF7E0;
75 } else {
76 control &= 0xFFE0;
77 }
78 currentDma->reg = control;
79
80 if (GBADMARegisterIsDRQ(currentDma->reg)) {
81 mLOG(GBA_MEM, STUB, "DRQ not implemented");
82 }
83
84 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
85 currentDma->nextSource = currentDma->source;
86 if (currentDma->nextSource >= BASE_CART0 && currentDma->nextSource < BASE_CART_SRAM && GBADMARegisterGetSrcControl(currentDma->reg) < 3) {
87 currentDma->reg = GBADMARegisterClearSrcControl(currentDma->reg);
88 }
89 currentDma->nextDest = currentDma->dest;
90 GBADMASchedule(gba, dma, currentDma);
91 }
92 // If the DMA has already occurred, this value might have changed since the function started
93 return currentDma->reg;
94};
95
96void GBADMASchedule(struct GBA* gba, int number, struct GBADMA* info) {
97 switch (GBADMARegisterGetTiming(info->reg)) {
98 case GBA_DMA_TIMING_NOW:
99 info->when = mTimingCurrentTime(&gba->timing) + 3; // DMAs take 3 cycles to start
100 info->nextCount = info->count;
101 break;
102 case GBA_DMA_TIMING_HBLANK:
103 case GBA_DMA_TIMING_VBLANK:
104 // Handled implicitly
105 return;
106 case GBA_DMA_TIMING_CUSTOM:
107 switch (number) {
108 case 0:
109 mLOG(GBA_MEM, WARN, "Discarding invalid DMA0 scheduling");
110 return;
111 case 1:
112 case 2:
113 GBAAudioScheduleFifoDma(&gba->audio, number, info);
114 break;
115 case 3:
116 // Handled implicitly
117 break;
118 }
119 }
120 GBADMAUpdate(gba);
121}
122
123void GBADMARunHblank(struct GBA* gba, int32_t cycles) {
124 struct GBAMemory* memory = &gba->memory;
125 struct GBADMA* dma;
126 int i;
127 for (i = 0; i < 4; ++i) {
128 dma = &memory->dma[i];
129 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_HBLANK && !dma->nextCount) {
130 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
131 dma->nextCount = dma->count;
132 }
133 }
134 GBADMAUpdate(gba);
135}
136
137void GBADMARunVblank(struct GBA* gba, int32_t cycles) {
138 struct GBAMemory* memory = &gba->memory;
139 struct GBADMA* dma;
140 int i;
141 for (i = 0; i < 4; ++i) {
142 dma = &memory->dma[i];
143 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_VBLANK && !dma->nextCount) {
144 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
145 dma->nextCount = dma->count;
146 }
147 }
148 GBADMAUpdate(gba);
149}
150
151void GBADMARunDisplayStart(struct GBA* gba, int32_t cycles) {
152 struct GBAMemory* memory = &gba->memory;
153 struct GBADMA* dma = &memory->dma[3];
154 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_CUSTOM && !dma->nextCount) {
155 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
156 dma->nextCount = dma->count;
157 GBADMAUpdate(gba);
158 }
159}
160
161void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate) {
162 UNUSED(timing);
163 UNUSED(cyclesLate);
164 struct GBA* gba = context;
165 struct GBAMemory* memory = &gba->memory;
166 struct GBADMA* dma = &memory->dma[memory->activeDMA];
167 if (dma->nextCount == dma->count) {
168 dma->when = mTimingCurrentTime(&gba->timing);
169 }
170 if (dma->nextCount & 0xFFFFF) {
171 GBADMAService(gba, memory->activeDMA, dma);
172 } else {
173 dma->nextCount = 0;
174 bool noRepeat = !GBADMARegisterIsRepeat(dma->reg);
175 noRepeat |= GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_NOW;
176 noRepeat |= memory->activeDMA == 3 && GBADMARegisterGetTiming(dma->reg) == GBA_DMA_TIMING_CUSTOM;
177 if (noRepeat) {
178 dma->reg = GBADMARegisterClearEnable(dma->reg);
179
180 // Clear the enable bit in memory
181 memory->io[(REG_DMA0CNT_HI + memory->activeDMA * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
182 }
183 if (GBADMARegisterGetDestControl(dma->reg) == GBA_DMA_INCREMENT_RELOAD) {
184 dma->nextDest = dma->dest;
185 }
186 if (GBADMARegisterIsDoIRQ(dma->reg)) {
187 GBARaiseIRQ(gba, IRQ_DMA0 + memory->activeDMA);
188 }
189 GBADMAUpdate(gba);
190 }
191}
192
193void GBADMAUpdate(struct GBA* gba) {
194 int i;
195 struct GBAMemory* memory = &gba->memory;
196 memory->activeDMA = -1;
197 uint32_t currentTime = mTimingCurrentTime(&gba->timing);
198 for (i = 0; i < 4; ++i) {
199 struct GBADMA* dma = &memory->dma[i];
200 if (GBADMARegisterIsEnable(dma->reg) && dma->nextCount) {
201 memory->activeDMA = i;
202 break;
203 }
204 }
205
206 if (memory->activeDMA >= 0) {
207 mTimingDeschedule(&gba->timing, &memory->dmaEvent);
208 mTimingSchedule(&gba->timing, &memory->dmaEvent, memory->dma[memory->activeDMA].when - currentTime);
209 } else {
210 gba->cpuBlocked = false;
211 }
212}
213
214void GBADMAService(struct GBA* gba, int number, struct GBADMA* info) {
215 struct GBAMemory* memory = &gba->memory;
216 struct ARMCore* cpu = gba->cpu;
217 uint32_t width = 2 << GBADMARegisterGetWidth(info->reg);
218 int32_t wordsRemaining = info->nextCount;
219 uint32_t source = info->nextSource;
220 uint32_t dest = info->nextDest;
221 uint32_t sourceRegion = source >> BASE_OFFSET;
222 uint32_t destRegion = dest >> BASE_OFFSET;
223 int32_t cycles = 2;
224
225 gba->cpuBlocked = true;
226 if (info->count == info->nextCount) {
227 if (sourceRegion < REGION_CART0 || destRegion < REGION_CART0) {
228 cycles += 2;
229 }
230 if (width == 4) {
231 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
232 } else {
233 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
234 }
235 source &= -width;
236 dest &= -width;
237 } else {
238 if (width == 4) {
239 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
240 } else {
241 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
242 }
243 }
244 info->when += cycles;
245
246 gba->performingDMA = 1 | (number << 1);
247 if (width == 4) {
248 if (source) {
249 memory->dmaTransferRegister = cpu->memory.load32(cpu, source, 0);
250 }
251 gba->bus = memory->dmaTransferRegister;
252 cpu->memory.store32(cpu, dest, memory->dmaTransferRegister, 0);
253 memory->dmaTransferRegister &= 0xFFFF0000;
254 memory->dmaTransferRegister |= memory->dmaTransferRegister >> 16;
255 } else {
256 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
257 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
258 mLOG(GBA_MEM, INFO, "Detected EEPROM savegame");
259 GBASavedataInitEEPROM(&memory->savedata, gba->realisticTiming);
260 }
261 memory->dmaTransferRegister = GBASavedataReadEEPROM(&memory->savedata);
262 } else {
263 if (source) {
264 memory->dmaTransferRegister = cpu->memory.load16(cpu, source, 0);
265 }
266 }
267 if (destRegion == REGION_CART2_EX) {
268 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
269 mLOG(GBA_MEM, INFO, "Detected EEPROM savegame");
270 GBASavedataInitEEPROM(&memory->savedata, gba->realisticTiming);
271 }
272 GBASavedataWriteEEPROM(&memory->savedata, memory->dmaTransferRegister, wordsRemaining);
273 } else {
274 cpu->memory.store16(cpu, dest, memory->dmaTransferRegister, 0);
275
276 }
277 memory->dmaTransferRegister |= memory->dmaTransferRegister << 16;
278 gba->bus = memory->dmaTransferRegister;
279 }
280 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
281 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
282 if (source) {
283 source += sourceOffset;
284 }
285 dest += destOffset;
286 --wordsRemaining;
287 gba->performingDMA = 0;
288
289 info->nextCount = wordsRemaining;
290 info->nextSource = source;
291 info->nextDest = dest;
292 if (!wordsRemaining) {
293 info->nextCount |= 0x80000000;
294 }
295 GBADMAUpdate(gba);
296}