1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef DS_MEMORY_H
  7#define DS_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/internal/arm/arm.h>
 16#include <mgba/internal/ds/dma.h>
 17#include <mgba/internal/ds/io.h>
 18#include <mgba/internal/ds/slot1.h>
 19#include <mgba/internal/ds/spi.h>
 20
 21const uint32_t redzoneInstruction;
 22
 23enum DSMemoryRegion {
 24	DS7_REGION_BIOS = 0x0,
 25	DS9_REGION_ITCM = 0x0,
 26	DS9_REGION_ITCM_MIRROR = 0x1,
 27	DS_REGION_RAM = 0x2,
 28	DS_REGION_WORKING_RAM = 0x3,
 29	DS_REGION_IO = 0x4,
 30	DS9_REGION_PALETTE_RAM = 0x5,
 31	DS_REGION_VRAM = 0x6,
 32	DS9_REGION_OAM = 0x7,
 33	DS_REGION_SLOT2 = 0x8,
 34	DS_REGION_SLOT2_EX = 0x9,
 35	DS_REGION_SLOT2_SRAM = 0xA,
 36	DS9_REGION_BIOS = 0xFF,
 37};
 38
 39enum DSMemoryBase {
 40	DS7_BASE_BIOS = 0x00000000,
 41	DS9_BASE_ITCM = 0x00000000,
 42	DS_BASE_RAM = 0x02000000,
 43	DS9_BASE_DTCM = 0x027C0000,
 44	DS_BASE_WORKING_RAM = 0x03000000,
 45	DS7_BASE_WORKING_RAM = 0x03800000,
 46	DS_BASE_IO = 0x04000000,
 47	DS9_BASE_PALETTE_RAM = 0x05000000,
 48	DS_BASE_VRAM = 0x06000000,
 49	DS9_BASE_OAM = 0x07000000,
 50	DS_BASE_SLOT2 = 0x08000000,
 51	DS_BASE_SLOT2_EX = 0x09000000,
 52	DS9_BASE_BIOS = 0xFFFF0000,
 53};
 54
 55enum {
 56	DS9_SIZE_ITCM = 0x00008000,
 57	DS9_SIZE_DTCM = 0x00004000,
 58	DS7_SIZE_BIOS = 0x00004000,
 59	DS9_SIZE_BIOS = 0x00008000,
 60	DS_SIZE_RAM = 0x00400000,
 61	DS_SIZE_VRAM = 0x000A4000,
 62	DS_SIZE_WORKING_RAM = 0x00008000,
 63	DS7_SIZE_WORKING_RAM = 0x00010000,
 64	DS9_SIZE_PALETTE_RAM = 0x00000800,
 65	DS9_SIZE_OAM = 0x00000800,
 66	DS_SIZE_SLOT2 = 0x02000000,
 67	DS_SIZE_SLOT2_SRAM = 0x00010000,
 68};
 69
 70enum {
 71	DS_OFFSET_MASK = 0x00FFFFFF,
 72	DS_BASE_OFFSET = 24,
 73	DS_VRAM_OFFSET = 14
 74};
 75
 76mLOG_DECLARE_CATEGORY(DS_MEM);
 77
 78struct DSMemory {
 79	uint32_t* bios7;
 80	uint32_t* bios9;
 81	uint32_t* itcm;
 82	uint32_t* dtcm;
 83	uint32_t* ram;
 84	uint32_t* wram;
 85	uint32_t* wramBase;
 86	uint32_t* wramBase7;
 87	uint32_t* wramBase9;
 88	uint32_t* wram7;
 89	uint32_t* rom;
 90	uint16_t io7[DS7_REG_MAX >> 1];
 91	uint16_t io9[DS9_REG_MAX >> 1];
 92	struct DSSlot1 slot1;
 93	struct DSSPIBus spiBus;
 94
 95	uint16_t vramMirror[9][0x40];
 96	uint16_t vramMode[9][6];
 97	uint16_t* vramBank[9];
 98	uint16_t* vram7[2];
 99
100
101	size_t romSize;
102	size_t wramSize7;
103	size_t wramSize9;
104
105	uint32_t dtcmBase;
106	uint32_t dtcmSize;
107	uint32_t itcmSize;
108
109	bool slot1Owner;
110	bool slot2Owner;
111};
112
113struct DSCoreMemory {
114	uint16_t* io;
115	int activeRegion;
116
117	char waitstatesSeq32[256];
118	char waitstatesSeq16[256];
119	char waitstatesNonseq32[256];
120	char waitstatesNonseq16[256];
121	char waitstatesPrefetchSeq32[16];
122	char waitstatesPrefetchSeq16[16];
123	char waitstatesPrefetchNonseq32[16];
124	char waitstatesPrefetchNonseq16[16];
125
126	struct GBADMA dma[4];
127	struct mTimingEvent dmaEvent;
128	int activeDMA;
129	bool slot1Access;
130	bool slot2Access;
131};
132
133struct DS;
134void DSMemoryInit(struct DS* ds);
135void DSMemoryDeinit(struct DS* ds);
136
137void DSMemoryReset(struct DS* ds);
138
139uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
140uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
141uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
142
143void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
144void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
145void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
146
147uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
148                         int* cycleCounter);
149uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
150                          int* cycleCounter);
151
152uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
153uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
154uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
155
156void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
157void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
158void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
159
160uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
161                         int* cycleCounter);
162uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
163                          int* cycleCounter);
164
165void DSConfigureWRAM(struct DSMemory*, uint8_t config);
166void DSConfigureExternalMemory(struct DS*, uint16_t config);
167
168#endif