src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26const uint8_t DS_CHIP_ID[4] = { 0xC2, 0x0F, 0x00, 0x00 };
27
28static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
29static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
30static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
31
32enum {
33 DS7_SP_BASE = 0x380FD80,
34 DS7_SP_BASE_IRQ = 0x380FF80,
35 DS7_SP_BASE_SVC = 0x380FFC0,
36
37 DS9_SP_BASE = 0x3002F7C,
38 DS9_SP_BASE_IRQ = 0x3003F80,
39 DS9_SP_BASE_SVC = 0x3003FC0,
40};
41
42static void DSInit(void* cpu, struct mCPUComponent* component);
43
44static void DS7Reset(struct ARMCore* cpu);
45static void DS7TestIRQ(struct ARMCore* cpu);
46static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
47static void DS7ProcessEvents(struct ARMCore* cpu);
48
49static void DS9Reset(struct ARMCore* cpu);
50static void DS9TestIRQ(struct ARMCore* cpu);
51static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
52static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
53static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
54static void DS9ProcessEvents(struct ARMCore* cpu);
55
56static void DSProcessEvents(struct DSCommon* dscore);
57static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
58static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
59static void DSBreakpoint(struct ARMCore* cpu, int immediate);
60
61static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
62 UNUSED(cyclesLate);
63 struct DS* ds = context;
64 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
65 if (ds->activeCpu == ds->ds9.cpu) {
66 ds->activeCpu = ds->ds7.cpu;
67 ds->cycleDrift += cycles;
68 cycles = ds->cycleDrift >> 1;
69 timing = &ds->ds7.timing;
70 } else {
71 ds->activeCpu = ds->ds9.cpu;
72 ds->cycleDrift -= cycles << 1;
73 cycles = ds->cycleDrift + SLICE_CYCLES;
74 timing = &ds->ds9.timing;
75 }
76 mTimingSchedule(timing, &ds->slice, cycles);
77 ds->sliceStart = mTimingCurrentTime(timing);
78 ds->earlyExit = true;
79}
80
81static void _divide(struct mTiming* timing, void* context, uint32_t cyclesLate) {
82 UNUSED(timing);
83 UNUSED(cyclesLate);
84 struct DS* ds = context;
85 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x8000;
86 int64_t numerator;
87 int64_t denominator;
88 LOAD_64LE(numerator, DS9_REG_DIV_NUMER_0, ds->memory.io9);
89 LOAD_64LE(denominator, DS9_REG_DIV_DENOM_0, ds->memory.io9);
90 bool max = false;
91 switch (ds->memory.io9[DS9_REG_DIVCNT >> 1] & 0x3) {
92 case 0:
93 numerator = (int64_t)(int32_t) numerator;
94 case 1:
95 case 3:
96 denominator = (int64_t)(int32_t) denominator;
97 break;
98 }
99 if (numerator == INT64_MIN) {
100 max = true;
101 }
102 if (!denominator) {
103 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
104 STORE_64LE(numerator, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
105 numerator >>= 63LL;
106 numerator = -numerator;
107 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
108 return;
109 }
110 if (denominator == -1LL && max) {
111 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
112 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
113 return;
114 }
115 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x4000;
116 int64_t result = numerator / denominator;
117 int64_t remainder = numerator % denominator; // TODO: defined behavior for negative denominator?
118 STORE_64LE(result, DS9_REG_DIV_RESULT_0, ds->memory.io9);
119 STORE_64LE(remainder, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
120}
121
122 static void _sqrt(struct mTiming* timing, void* context, uint32_t cyclesLate) {
123 UNUSED(timing);
124 UNUSED(cyclesLate);
125 struct DS* ds = context;
126 ds->memory.io9[DS9_REG_SQRTCNT >> 1] &= ~0x8000;
127 uint64_t param;
128 LOAD_64LE(param, DS9_REG_SQRT_PARAM_0, ds->memory.io9);
129 if (!(ds->memory.io9[DS9_REG_SQRTCNT >> 1] & 1)) {
130 param &= 0xFFFFFFFFULL;
131 }
132
133 uint64_t result = 0;
134 uint64_t bit = 0x4000000000000000ULL; // The second-to-top bit is set: 1 << 30 for 32 bits
135
136 // "bit" starts at the highest power of four <= the argument.
137 while (bit > param) {
138 bit >>= 2;
139 }
140
141 while (bit != 0) {
142 if (param >= param + bit) {
143 param -= param + bit;
144 param = (result >> 1) + bit;
145 } else {
146 param >>= 1;
147 }
148 bit >>= 2;
149 }
150 STORE_32LE(result, DS9_REG_SQRT_RESULT_LO, ds->memory.io9);
151}
152
153void DSCreate(struct DS* ds) {
154 ds->d.id = DS_COMPONENT_MAGIC;
155 ds->d.init = DSInit;
156 ds->d.deinit = NULL;
157 ds->ds7.p = ds;
158 ds->ds9.p = ds;
159 ds->ds7.cpu = NULL;
160 ds->ds9.cpu = NULL;
161 ds->ds7.ipc = &ds->ds9;
162 ds->ds9.ipc = &ds->ds7;
163}
164
165static void DSInit(void* cpu, struct mCPUComponent* component) {
166 struct DS* ds = (struct DS*) component;
167 struct ARMCore* core = cpu;
168 if (!ds->ds7.cpu) {
169 // The ARM7 must get initialized first
170 ds->ds7.cpu = core;
171 ds->debugger = 0;
172 ds->sync = 0;
173 return;
174 }
175 ds->ds9.cpu = cpu;
176 ds->activeCpu = NULL;
177
178 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
179
180 ds->slice.name = "DS CPU Time Slicing";
181 ds->slice.callback = _slice;
182 ds->slice.context = ds;
183 ds->slice.priority = UINT_MAX;
184
185 CircleBufferInit(&ds->ds7.fifo, 64);
186 CircleBufferInit(&ds->ds9.fifo, 64);
187
188 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
189 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
190 DSMemoryInit(ds);
191 DSDMAInit(ds);
192
193 DSVideoInit(&ds->video);
194 ds->video.p = ds;
195
196 ds->ds7.springIRQ = 0;
197 ds->ds9.springIRQ = 0;
198 DSTimerInit(ds);
199 ds->keySource = NULL;
200 ds->rtcSource = NULL;
201 ds->rumble = NULL;
202
203 ds->romVf = NULL;
204 DSSlot1SPIInit(ds, NULL);
205
206 ds->keyCallback = NULL;
207
208 ds->divEvent.name = "DS Hardware Divide";
209 ds->divEvent.callback = _divide;
210 ds->divEvent.context = ds;
211 ds->divEvent.priority = 0x50;
212
213 ds->sqrtEvent.name = "DS Hardware Sqrt";
214 ds->sqrtEvent.callback = _sqrt;
215 ds->sqrtEvent.context = ds;
216 ds->sqrtEvent.priority = 0x51;
217
218 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
219 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
220}
221
222void DSUnloadROM(struct DS* ds) {
223 if (ds->romVf) {
224 ds->romVf->close(ds->romVf);
225 ds->romVf = NULL;
226 }
227}
228
229void DSDestroy(struct DS* ds) {
230 CircleBufferDeinit(&ds->ds7.fifo);
231 CircleBufferDeinit(&ds->ds9.fifo);
232 DSUnloadROM(ds);
233 DSMemoryDeinit(ds);
234 mTimingDeinit(&ds->ds7.timing);
235 mTimingDeinit(&ds->ds9.timing);
236}
237
238void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
239 irqh->reset = DS7Reset;
240 irqh->processEvents = DS7ProcessEvents;
241 irqh->swi16 = DS7Swi16;
242 irqh->swi32 = DS7Swi32;
243 irqh->hitIllegal = DSIllegal;
244 irqh->readCPSR = DS7TestIRQ;
245 irqh->writeCP15 = NULL;
246 irqh->readCP15 = NULL;
247 irqh->hitStub = DSHitStub;
248 irqh->bkpt16 = DSBreakpoint;
249 irqh->bkpt32 = DSBreakpoint;
250}
251
252void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
253 irqh->reset = DS9Reset;
254 irqh->processEvents = DS9ProcessEvents;
255 irqh->swi16 = DS9Swi16;
256 irqh->swi32 = DS9Swi32;
257 irqh->hitIllegal = DSIllegal;
258 irqh->readCPSR = DS9TestIRQ;
259 irqh->writeCP15 = DS9WriteCP15;
260 irqh->readCP15 = DS9ReadCP15;
261 irqh->hitStub = DSHitStub;
262 irqh->bkpt16 = DSBreakpoint;
263 irqh->bkpt32 = DSBreakpoint;
264}
265
266void DS7Reset(struct ARMCore* cpu) {
267 ARMSetPrivilegeMode(cpu, MODE_IRQ);
268 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
269 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
270 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
271 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
272 cpu->gprs[ARM_SP] = DS7_SP_BASE;
273
274 struct DS* ds = (struct DS*) cpu->master;
275 mTimingClear(&ds->ds7.timing);
276 CircleBufferInit(&ds->ds7.fifo, 64);
277 DSMemoryReset(ds);
278 DSDMAReset(&ds->ds7);
279 DS7IOInit(ds);
280
281 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
282 if (header) {
283 memcpy(&ds->memory.ram[0x3FF800 >> 2], DS_CHIP_ID, 4);
284 memcpy(&ds->memory.ram[0x3FF804 >> 2], DS_CHIP_ID, 4);
285 memcpy(&ds->memory.ram[0x3FFC00 >> 2], DS_CHIP_ID, 4);
286 memcpy(&ds->memory.ram[0x3FFC04 >> 2], DS_CHIP_ID, 4);
287 memcpy(&ds->memory.ram[0x3FFE00 >> 2], header, 0x170);
288 DS7IOWrite32(ds, DS_REG_ROMCNT_LO, header->busTiming | 0x2700000);
289 // TODO: Error check
290 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
291 uint32_t base = header->arm7Base - DS_BASE_RAM;
292 uint32_t* basePointer = &ds->memory.ram[base >> 2];
293 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
294 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
295 }
296 cpu->gprs[12] = header->arm7Entry;
297 cpu->gprs[ARM_LR] = header->arm7Entry;
298 cpu->gprs[ARM_PC] = header->arm7Entry;
299 int currentCycles = 0;
300 ARM_WRITE_PC;
301
302 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
303 }
304}
305
306void DS9Reset(struct ARMCore* cpu) {
307 ARMSetPrivilegeMode(cpu, MODE_IRQ);
308 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
309 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
310 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
311 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
312 cpu->gprs[ARM_SP] = DS9_SP_BASE;
313
314 struct DS* ds = (struct DS*) cpu->master;
315 mTimingClear(&ds->ds9.timing);
316 CircleBufferInit(&ds->ds9.fifo, 64);
317 DSVideoReset(&ds->video);
318 DSDMAReset(&ds->ds9);
319 DS9IOInit(ds);
320
321 ds->activeCpu = cpu;
322 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
323 ds->cycleDrift = 0;
324 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
325
326 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
327 if (header) {
328 // TODO: Error check
329 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
330 uint32_t base = header->arm9Base - DS_BASE_RAM;
331 uint32_t* basePointer = &ds->memory.ram[base >> 2];
332 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
333 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
334 }
335 cpu->gprs[12] = header->arm9Entry;
336 cpu->gprs[ARM_LR] = header->arm9Entry;
337 cpu->gprs[ARM_PC] = header->arm9Entry;
338 int currentCycles = 0;
339 ARM_WRITE_PC;
340
341 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
342 }
343}
344
345static void DS7ProcessEvents(struct ARMCore* cpu) {
346 struct DS* ds = (struct DS*) cpu->master;
347 DSProcessEvents(&ds->ds7);
348}
349
350static void DS9ProcessEvents(struct ARMCore* cpu) {
351 struct DS* ds = (struct DS*) cpu->master;
352 DSProcessEvents(&ds->ds9);
353}
354
355static void DSProcessEvents(struct DSCommon* dscore) {
356 struct ARMCore* cpu = dscore->cpu;
357 struct DS* ds = dscore->p;
358 if (dscore->springIRQ && !cpu->cpsr.i) {
359 ARMRaiseIRQ(cpu);
360 dscore->springIRQ = 0;
361 }
362
363 int32_t nextEvent = cpu->nextEvent;
364 while (cpu->cycles >= nextEvent) {
365 int32_t cycles = cpu->cycles;
366
367 cpu->cycles = 0;
368 cpu->nextEvent = 0;
369
370#ifndef NDEBUG
371 if (cycles < 0) {
372 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
373 }
374#endif
375 nextEvent = cycles;
376 do {
377 nextEvent = mTimingTick(&dscore->timing, nextEvent);
378 } while (ds->cpuBlocked);
379
380 if (ds->earlyExit) {
381 ds->earlyExit = false;
382 break;
383 }
384
385 cpu->nextEvent = nextEvent;
386 if (cpu->halted) {
387 cpu->cycles = nextEvent;
388 }
389#ifndef NDEBUG
390 else if (nextEvent < 0) {
391 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
392 }
393#endif
394 }
395}
396
397void DSRunLoop(struct DS* ds) {
398 if (ds->activeCpu == ds->ds9.cpu) {
399 ARMv5RunLoop(ds->ds9.cpu);
400 } else {
401 ARMv4RunLoop(ds->ds7.cpu);
402 }
403}
404
405void DS7Step(struct DS* ds) {
406 int32_t pc = ds->ds7.cpu->gprs[ARM_PC];
407 do {
408 while (ds->activeCpu == ds->ds9.cpu) {
409 ARMv5RunLoop(ds->ds9.cpu);
410 }
411 ARMv4Run(ds->ds7.cpu);
412 } while (ds->ds7.cpu->halted || ds->ds7.cpu->gprs[ARM_PC] == pc);
413}
414
415void DS9Step(struct DS* ds) {
416 int32_t pc = ds->ds9.cpu->gprs[ARM_PC];
417 do {
418 while (ds->activeCpu == ds->ds7.cpu) {
419 ARMv4RunLoop(ds->ds7.cpu);
420 }
421 ARMv5Run(ds->ds9.cpu);
422 } while (ds->ds9.cpu->halted || ds->ds9.cpu->gprs[ARM_PC] == pc);
423}
424
425void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
426 ds->debugger = (struct ARMDebugger*) debugger->platform;
427 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
428 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
429 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
430 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
431}
432
433void DSDetachDebugger(struct DS* ds) {
434 ds->debugger = NULL;
435 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
436 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
437 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
438 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
439}
440
441bool DSLoadROM(struct DS* ds, struct VFile* vf) {
442 DSUnloadROM(ds);
443 ds->romVf = vf;
444 // TODO: error check
445 return true;
446}
447
448bool DSLoadSave(struct DS* ds, struct VFile* sav) {
449 DSSlot1SPIInit(ds, sav);
450 return true;
451}
452
453bool DSIsROM(struct VFile* vf) {
454 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
455 return false;
456 }
457 uint8_t signature[sizeof(DS_ROM_MAGIC)];
458 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
459 return false;
460 }
461 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
462}
463
464bool DSIsBIOS7(struct VFile* vf) {
465 size_t size = vf->size(vf);
466 void* data = NULL;
467 uint32_t crc;
468 if (size == DS7_SIZE_BIOS) {
469 data = vf->map(vf, size, MAP_READ);
470 }
471 if (!data) {
472 return false;
473 }
474 crc = doCrc32(data, size);
475 vf->unmap(vf, data, size);
476 return crc == DS7_BIOS_CHECKSUM;
477}
478
479bool DSIsBIOS9(struct VFile* vf) {
480 size_t size = vf->size(vf);
481 void* data = NULL;
482 uint32_t crc;
483 if (size == DS9_SIZE_BIOS) {
484 data = vf->map(vf, 0x1000, MAP_READ);
485 } else if (size == 0x1000) {
486 data = vf->map(vf, 0x1000, MAP_READ);
487 }
488 if (!data) {
489 return false;
490 }
491 crc = doCrc32(data, 0x1000);
492 vf->unmap(vf, data, 0x1000);
493 return crc == DS9_BIOS_CHECKSUM;
494}
495
496bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
497 size_t size = vf->size(vf);
498 void* data = NULL;
499 uint32_t crc;
500 if (size == DS7_SIZE_BIOS) {
501 data = vf->map(vf, size, MAP_READ);
502 } else if (size == 0x1000) {
503 data = calloc(DS9_SIZE_BIOS, 1);
504 vf->read(vf, data, size);
505 } else if (size == DS9_SIZE_BIOS) {
506 data = vf->map(vf, size, MAP_READ);
507 }
508 if (!data) {
509 return false;
510 }
511 crc = doCrc32(data, size);
512 if (crc == DS7_BIOS_CHECKSUM) {
513 ds->bios7Vf = vf;
514 ds->memory.bios7 = data;
515 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
516 } else if (crc == DS9_BIOS_CHECKSUM) {
517 ds->bios9Vf = vf;
518 ds->memory.bios9 = data;
519 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
520 } else {
521 mLOG(DS, WARN, "BIOS checksum incorrect");
522 vf->unmap(vf, data, size);
523 return false;
524 }
525 return true;
526}
527
528void DSGetGameCode(struct DS* ds, char* out) {
529 memset(out, 0, 8);
530 if (!ds->romVf) {
531 return;
532 }
533
534 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
535 // TODO: TWL-?
536 memcpy(out, "NTR-", 4);
537 memcpy(&out[4], &cart->id, 4);
538 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
539}
540
541void DSGetGameTitle(struct DS* ds, char* out) {
542 memset(out, 0, 12);
543 if (!ds->romVf) {
544 return;
545 }
546
547 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
548 memcpy(out, &cart->title, 12);
549 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
550}
551
552void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
553 struct DS* ds = (struct DS*) cpu->master;
554 if (ds->debugger) {
555 struct mDebuggerEntryInfo info = {
556 .address = _ARMPCAddress(cpu),
557 .opcode = opcode
558 };
559 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
560 }
561 // TODO: More sensible category?
562 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
563}
564
565void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
566 struct DS* ds = (struct DS*) cpu->master;
567 if ((opcode & 0xFFFF) == (redzoneInstruction & 0xFFFF)) {
568 int currentCycles = 0;
569 if (cpu->executionMode == MODE_THUMB) {
570 cpu->gprs[ARM_PC] -= WORD_SIZE_THUMB * 2;
571 THUMB_WRITE_PC;
572 } else {
573 cpu->gprs[ARM_PC] -= WORD_SIZE_ARM * 2;
574 ARM_WRITE_PC;
575 }
576 } else if (ds->debugger) {
577 struct mDebuggerEntryInfo info = {
578 .address = _ARMPCAddress(cpu),
579 .opcode = opcode
580 };
581 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
582 } else {
583 ARMRaiseUndefined(cpu);
584 }
585}
586
587void DSBreakpoint(struct ARMCore* cpu, int immediate) {
588 struct DS* ds = (struct DS*) cpu->master;
589 if (immediate >= CPU_COMPONENT_MAX) {
590 return;
591 }
592 switch (immediate) {
593 case CPU_COMPONENT_DEBUGGER:
594 if (ds->debugger) {
595 struct mDebuggerEntryInfo info = {
596 .address = _ARMPCAddress(cpu)
597 };
598 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
599 }
600 break;
601 default:
602 break;
603 }
604}
605
606void DS7TestIRQ(struct ARMCore* cpu) {
607 struct DS* ds = (struct DS*) cpu->master;
608 if (!ds->memory.io7[DS_REG_IME >> 1]) {
609 return;
610 }
611 uint32_t test = (ds->memory.io7[DS_REG_IE_LO >> 1] & ds->memory.io7[DS_REG_IF_LO >> 1]);
612 test |= (ds->memory.io7[DS_REG_IE_HI >> 1] & ds->memory.io7[DS_REG_IF_HI >> 1]) << 16;
613 if (test) {
614 ds->ds7.springIRQ = test;
615 cpu->nextEvent = cpu->cycles;
616 }
617}
618
619void DS9TestIRQ(struct ARMCore* cpu) {
620 struct DS* ds = (struct DS*) cpu->master;
621 if (!ds->memory.io9[DS_REG_IME >> 1]) {
622 return;
623 }
624 uint32_t test = (ds->memory.io9[DS_REG_IE_LO >> 1] & ds->memory.io9[DS_REG_IF_LO >> 1]);
625 test |= (ds->memory.io9[DS_REG_IE_HI >> 1] & ds->memory.io9[DS_REG_IF_HI >> 1]) << 16;
626 if (test) {
627 ds->ds9.springIRQ = test;
628 cpu->nextEvent = cpu->cycles;
629 }
630}
631
632static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
633 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
634}
635
636static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
637 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
638 switch (opcode2) {
639 case 0:
640 cpu->cp15.r2.d = value;
641 break;
642 case 1:
643 cpu->cp15.r2.i = value;
644 break;
645 default:
646 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
647 break;
648 }
649}
650
651static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
652 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
653 switch (opcode2) {
654 case 0:
655 cpu->cp15.r3.d = value;
656 break;
657 default:
658 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
659 break;
660 }
661}
662
663static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
664 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
665}
666
667static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
668 cpu->cp15.r6.region[crm] = value;
669 uint32_t base = ARMProtectionGetBase(value) << 12;
670 uint32_t size = 2 << ARMProtectionGetSize(value);
671 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
672}
673
674static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
675 switch (crm) {
676 case 0:
677 if (opcode2 == 4) {
678 ARMHalt(cpu);
679 return;
680 }
681 break;
682 }
683 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
684}
685
686static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
687 uint32_t base = ARMTCMControlGetBase(value) << 12;
688 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
689 struct DS* ds = (struct DS*) cpu->master;
690 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
691 switch (opcode2) {
692 case 0:
693 cpu->cp15.r9.d = value;
694 ds->memory.dtcmBase = base;
695 ds->memory.dtcmSize = size;
696 break;
697 case 1:
698 cpu->cp15.r9.i = value;
699 ds->memory.itcmSize = size;
700 break;
701 default:
702 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
703 break;
704 }
705}
706
707void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
708 switch (crn) {
709 default:
710 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
711 break;
712 case 0:
713 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
714 ARMRaiseUndefined(cpu);
715 break;
716 case 1:
717 _writeSysControl(cpu, crm, opcode2, value);
718 break;
719 case 2:
720 _writeCacheControl(cpu, crm, opcode2, value);
721 break;
722 case 3:
723 _writeWriteBufferControl(cpu, crm, opcode2, value);
724 break;
725 case 5:
726 _writeAccessControl(cpu, crm, opcode2, value);
727 break;
728 case 6:
729 _writeRegionConfiguration(cpu, crm, opcode2, value);
730 break;
731 case 7:
732 _writeCache(cpu, crm, opcode2, value);
733 break;
734 case 9:
735 _writeTCMControl(cpu, crm, opcode2, value);
736 break;
737 }
738}
739
740static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
741 switch (opcode2) {
742 case 0:
743 return cpu->cp15.r9.d;
744 case 1:
745 return cpu->cp15.r9.i;
746 default:
747 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
748 return 0;
749 }
750}
751
752uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
753 switch (crn) {
754 default:
755 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
756 return 0;
757 case 9:
758 return _readTCMControl(cpu, crm, opcode2);
759 }
760}
761
762void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
763 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
764 ARMRaiseIRQ(cpu);
765 }
766}
767void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
768 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
769 ARMRaiseIRQ(cpu);
770 }
771}
772
773void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
774 if (irq < 16) {
775 io[DS_REG_IF_LO >> 1] |= 1 << irq;
776 } else {
777 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
778 }
779
780 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
781 cpu->halted = 0;
782 if (io[DS_REG_IME >> 1]) {
783 ARMRaiseIRQ(cpu);
784 }
785 }
786}
787
788void DSFrameStarted(struct DS* ds) {
789 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
790 if (callbacks && callbacks->videoFrameStarted) {
791 callbacks->videoFrameStarted(callbacks->context);
792 }
793}
794
795void DSFrameEnded(struct DS* ds) {
796 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
797 if (callbacks && callbacks->videoFrameEnded) {
798 callbacks->videoFrameEnded(callbacks->context);
799 }
800}