src/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define APPLY(F, ...) F(__VA_ARGS__)
20
21#define COUNT_1(EMITTER, PREFIX, ...) \
22 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
23 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
24
25#define COUNT_2(EMITTER, PREFIX, ...) \
26 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
27 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
28 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
29
30#define COUNT_3(EMITTER, PREFIX, ...) \
31 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
32 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
33 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
34 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
35 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
36
37#define COUNT_4(EMITTER, PREFIX, ...) \
38 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
39 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
40 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
41 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
42 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
43 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
44 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
45 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
46 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
47
48#define COUNT_5(EMITTER, PREFIX, ...) \
49 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
50 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
51 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
52 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
53 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
54 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
55 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
56 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
57 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
58 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
59 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
60 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
61 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
62 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
63 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
64 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
65 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
66
67#define THUMB_WRITE_PC \
68 cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB) + WORD_SIZE_THUMB
69
70#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
71 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
72 BODY; \
73 }
74
75#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
76 DEFINE_INSTRUCTION_THUMB(NAME, \
77 int immediate = IMMEDIATE; \
78 BODY;)
79
80#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
81 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
82
83DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, ARM_STUB)
84DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, ARM_STUB)
85DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
86
87DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, ARM_STUB)
88DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
89DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
90DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, ARM_STUB)
91DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, ARM_STUB)
92DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, ARM_STUB)
93
94#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
95 DEFINE_INSTRUCTION_THUMB(NAME, \
96 int rm = RM; \
97 BODY;)
98
99#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
100 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
101
102DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, ARM_STUB)
103DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
104
105#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
106 DEFINE_INSTRUCTION_THUMB(NAME, \
107 int immediate = IMMEDIATE; \
108 BODY;)
109
110#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
111 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
112
113DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, ARM_STUB)
114DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
115
116#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
117 DEFINE_INSTRUCTION_THUMB(NAME, \
118 int rd = RD; \
119 BODY;)
120
121#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
122 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
123
124DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, ARM_STUB)
125DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, ARM_STUB)
126DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, ARM_STUB)
127DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
128
129#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
130 DEFINE_INSTRUCTION_THUMB(NAME, \
131 int rd = opcode & 0x0007; \
132 int rn = (opcode >> 3) & 0x0007; \
133 BODY;)
134
135DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, ARM_STUB)
136DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, ARM_STUB)
137DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
138DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, ARM_STUB)
139DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, ARM_STUB)
140DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
141DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
142DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
143DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
144DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
145DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
146DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
147DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, ARM_STUB)
148DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
149DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
150DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
151
152#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
153 DEFINE_INSTRUCTION_THUMB(NAME, \
154 int rd = opcode & 0x0007 | H1; \
155 int rm = (opcode >> 3) & 0x0007 | H2; \
156 BODY;)
157
158#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
159 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
160 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
161 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
162 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
163
164DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, ARM_STUB)
165DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, ARM_STUB)
166DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, ARM_STUB)
167
168#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
169 DEFINE_INSTRUCTION_THUMB(NAME, \
170 int rd = RD; \
171 BODY;)
172
173#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
174 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
175
176DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, ARM_STUB)
177DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, ARM_STUB)
178DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, ARM_STUB)
179
180DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
181DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ARM_STUB)
182
183#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
184 DEFINE_INSTRUCTION_THUMB(NAME, \
185 int rm = RM; \
186 BODY;)
187
188#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
189 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
190
191DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
192DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
193DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
194DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
195DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
196DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
197DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
198DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
199
200#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, BODY) \
201 DEFINE_INSTRUCTION_THUMB(NAME, \
202 int rs = RS; \
203 BODY;)
204
205#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY) \
206 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, BODY)
207
208DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA, ARM_STUB)
209DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, ARM_STUB)
210
211#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
212 DEFINE_INSTRUCTION_THUMB(B ## COND, \
213 if (ARM_COND_ ## COND) { \
214 ARM_STUB; \
215 })
216
217DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
218DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
219DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
220DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
221DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
222DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
223DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
224DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
225DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
226DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
227DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
228DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
229DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
230DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
231
232DEFINE_INSTRUCTION_THUMB(ADD7, ARM_STUB)
233DEFINE_INSTRUCTION_THUMB(SUB4, ARM_STUB)
234
235DEFINE_INSTRUCTION_THUMB(POP, ARM_STUB)
236DEFINE_INSTRUCTION_THUMB(POPR, ARM_STUB)
237DEFINE_INSTRUCTION_THUMB(PUSH, ARM_STUB)
238DEFINE_INSTRUCTION_THUMB(PUSHR, ARM_STUB)
239
240DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
241DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
242DEFINE_INSTRUCTION_THUMB(B, ARM_STUB)
243DEFINE_INSTRUCTION_THUMB(BL1, ARM_STUB)
244DEFINE_INSTRUCTION_THUMB(BL2, ARM_STUB)
245DEFINE_INSTRUCTION_THUMB(BX, ARM_STUB)
246DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
247
248#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
249 EMITTER ## NAME
250
251#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
252 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
253 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
254 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
255 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
256
257#define DUMMY(X, ...) X,
258#define DUMMY_4(...) \
259 DUMMY(__VA_ARGS__) \
260 DUMMY(__VA_ARGS__) \
261 DUMMY(__VA_ARGS__) \
262 DUMMY(__VA_ARGS__)
263
264#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
265 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
266 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
267 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
268 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
269 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
270 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
271 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
272 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
273 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
274 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
275 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
276 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
277 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
278 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
279 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
280 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
281 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
282 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
283 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
284 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
285 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
286 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
287 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
288 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
289 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
290 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
291 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
292 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
293 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
294 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
295 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
296 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
297 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
298 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
299 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
300 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
301 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
302 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
303 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
304 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
305 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
306 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
307 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
308 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
309 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
310 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
311 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
312 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
313 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
314 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
315 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
316 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
317 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
318 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
319 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
320 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
321 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
322 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
323 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
324 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
325 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
326 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
327 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
328 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
329 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
330 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
331 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
332 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
333 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
334 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
335 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
336 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
337 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
338 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
339 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
340 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
341 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
342 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
343 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
344 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
345 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
346 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
347 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
348 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
349 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
350 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
351 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
352 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
353 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
354 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
355 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
356
357static const ThumbInstruction _thumbTable[0x400] = {
358 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
359};