src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/internal/arm/decoder.h>
9#include <mgba/internal/arm/debugger/debugger.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba/internal/ds/bios.h>
12
13#include <mgba-util/crc32.h>
14#include <mgba-util/memory.h>
15#include <mgba-util/math.h>
16#include <mgba-util/vfs.h>
17
18mLOG_DEFINE_CATEGORY(DS, "DS");
19
20const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
21const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
22const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
23
24static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
25static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
26
27enum {
28 DS7_SP_BASE = 0x380FD80,
29 DS7_SP_BASE_IRQ = 0x380FF80,
30 DS7_SP_BASE_SVC = 0x380FFC0,
31
32 DS9_SP_BASE = 0x3002F7C,
33 DS9_SP_BASE_IRQ = 0x3003F80,
34 DS9_SP_BASE_SVC = 0x3003FC0,
35};
36
37static void DSInit(void* cpu, struct mCPUComponent* component);
38
39static void DS7Reset(struct ARMCore* cpu);
40static void DS7TestIRQ(struct ARMCore* cpu);
41static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
42
43static void DS9Reset(struct ARMCore* cpu);
44static void DS9TestIRQ(struct ARMCore* cpu);
45static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
46static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
47
48static void DSProcessEvents(struct ARMCore* cpu);
49static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
50static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
51static void DSBreakpoint(struct ARMCore* cpu, int immediate);
52
53void DSCreate(struct DS* ds) {
54 ds->d.id = DS_COMPONENT_MAGIC;
55 ds->d.init = DSInit;
56 ds->d.deinit = NULL;
57 ds->arm7 = NULL;
58 ds->arm9 = NULL;
59}
60
61static void DSInit(void* cpu, struct mCPUComponent* component) {
62 struct DS* ds = (struct DS*) component;
63 struct ARMCore* core = cpu;
64 if (!ds->arm7) {
65 // The ARM7 must get initialized first
66 ds->arm7 = core;
67 ds->debugger = 0;
68 ds->sync = 0;
69 return;
70 }
71 ds->arm9 = cpu;
72
73 ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
74
75 DS7InterruptHandlerInit(&ds->arm7->irqh);
76 DS9InterruptHandlerInit(&ds->arm9->irqh);
77 DSMemoryInit(ds);
78
79 ds->video.p = ds;
80
81 ds->springIRQ7 = 0;
82 ds->springIRQ9 = 0;
83 DSTimerInit(ds);
84 ds->keySource = NULL;
85 ds->rtcSource = NULL;
86 ds->rumble = NULL;
87
88 ds->romVf = NULL;
89
90 ds->keyCallback = NULL;
91
92 mTimingInit(&ds->timing7, &ds->arm7->cycles, &ds->arm7->nextEvent);
93 mTimingInit(&ds->timing9, &ds->arm9->cycles, &ds->arm9->nextEvent);
94}
95
96void DSUnloadROM(struct DS* ds) {
97 if (ds->romVf) {
98 ds->romVf->close(ds->romVf);
99 ds->romVf = NULL;
100 }
101}
102
103void DSDestroy(struct DS* ds) {
104 DSUnloadROM(ds);
105 DSMemoryDeinit(ds);
106 mTimingDeinit(&ds->timing7);
107 mTimingDeinit(&ds->timing9);
108}
109
110void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
111 irqh->reset = DS7Reset;
112 irqh->processEvents = DSProcessEvents;
113 irqh->swi16 = DS7Swi16;
114 irqh->swi32 = DS7Swi32;
115 irqh->hitIllegal = DSIllegal;
116 irqh->readCPSR = DS7TestIRQ;
117 irqh->writeCP15 = NULL;
118 irqh->hitStub = DSHitStub;
119 irqh->bkpt16 = DSBreakpoint;
120 irqh->bkpt32 = DSBreakpoint;
121}
122
123void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
124 irqh->reset = DS9Reset;
125 irqh->processEvents = DSProcessEvents;
126 irqh->swi16 = NULL;
127 irqh->swi32 = NULL;
128 irqh->hitIllegal = DSIllegal;
129 irqh->readCPSR = DS9TestIRQ;
130 irqh->writeCP15 = DS9WriteCP15;
131 irqh->hitStub = DSHitStub;
132 irqh->bkpt16 = DSBreakpoint;
133 irqh->bkpt32 = DSBreakpoint;
134}
135
136void DS7Reset(struct ARMCore* cpu) {
137 ARMSetPrivilegeMode(cpu, MODE_IRQ);
138 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
139 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
140 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
141 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
142 cpu->gprs[ARM_SP] = DS7_SP_BASE;
143
144 struct DS* ds = (struct DS*) cpu->master;
145 mTimingClear(&ds->timing7);
146 DSMemoryReset(ds);
147 DS7IOInit(ds);
148
149 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
150 if (header) {
151 // TODO: Error check
152 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
153 uint32_t base = header->arm7Base - DS_BASE_RAM;
154 uint32_t* basePointer = &ds->memory.ram[base >> 2];
155 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
156 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
157 }
158 cpu->gprs[12] = header->arm7Entry;
159 cpu->gprs[ARM_LR] = header->arm7Entry;
160 cpu->gprs[ARM_PC] = header->arm7Entry;
161 int currentCycles = 0;
162 ARM_WRITE_PC;
163
164 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
165 }
166}
167
168void DS9Reset(struct ARMCore* cpu) {
169 ARMSetPrivilegeMode(cpu, MODE_IRQ);
170 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
171 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
172 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
173 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
174 cpu->gprs[ARM_SP] = DS9_SP_BASE;
175
176 struct DS* ds = (struct DS*) cpu->master;
177 mTimingClear(&ds->timing9);
178 DS9IOInit(ds);
179
180 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
181 if (header) {
182 // TODO: Error check
183 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
184 uint32_t base = header->arm9Base - DS_BASE_RAM;
185 uint32_t* basePointer = &ds->memory.ram[base >> 2];
186 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
187 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
188 }
189 cpu->gprs[12] = header->arm9Entry;
190 cpu->gprs[ARM_LR] = header->arm9Entry;
191 cpu->gprs[ARM_PC] = header->arm9Entry;
192 int currentCycles = 0;
193 ARM_WRITE_PC;
194
195 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
196 }
197}
198
199static void DSProcessEvents(struct ARMCore* cpu) {
200 struct DS* ds = (struct DS*) cpu->master;
201
202 if (ds->springIRQ7 && !cpu->cpsr.i) {
203 ARMRaiseIRQ(cpu);
204 ds->springIRQ7 = 0;
205 }
206
207 int32_t nextEvent = cpu->nextEvent;
208 while (cpu->cycles >= nextEvent) {
209 int32_t cycles = cpu->cycles;
210
211 cpu->cycles = 0;
212 cpu->nextEvent = INT_MAX;
213
214#ifndef NDEBUG
215 if (cycles < 0) {
216 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
217 }
218#endif
219 nextEvent = cycles;
220 do {
221 nextEvent = mTimingTick(&ds->timing7, nextEvent);
222 } while (ds->cpuBlocked);
223
224 cpu->nextEvent = nextEvent;
225
226 if (ds->earlyExit) {
227 ds->earlyExit = false;
228 break;
229 }
230 if (cpu->halted) {
231 cpu->cycles = nextEvent;
232 }
233#ifndef NDEBUG
234 else if (nextEvent < 0) {
235 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
236 }
237#endif
238 }
239}
240
241void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
242 ds->debugger = (struct ARMDebugger*) debugger->platform;
243 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
244 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
245 ARMHotplugAttach(ds->arm7, CPU_COMPONENT_DEBUGGER);
246 ARMHotplugAttach(ds->arm9, CPU_COMPONENT_DEBUGGER);
247}
248
249void DSDetachDebugger(struct DS* ds) {
250 ds->debugger = NULL;
251 ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
252 ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
253 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
254 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
255}
256
257bool DSLoadROM(struct DS* ds, struct VFile* vf) {
258 DSUnloadROM(ds);
259 ds->romVf = vf;
260 // TODO: error check
261 return true;
262}
263
264bool DSIsROM(struct VFile* vf) {
265 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
266 return false;
267 }
268 uint8_t signature[sizeof(DS_ROM_MAGIC)];
269 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
270 return false;
271 }
272 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
273}
274
275bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
276 size_t size = vf->size(vf);
277 void* data = NULL;
278 uint32_t crc;
279 if (size == DS7_SIZE_BIOS) {
280 data = vf->map(vf, size, MAP_READ);
281 } else if (size == 0x1000) {
282 data = vf->map(vf, size, MAP_READ);
283 }
284 if (!data) {
285 return false;
286 }
287 crc = doCrc32(data, size);
288 if (crc == DS7_BIOS_CHECKSUM) {
289 ds->bios7Vf = vf;
290 ds->memory.bios7 = data;
291 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
292 } else if (crc == DS9_BIOS_CHECKSUM) {
293 ds->bios9Vf = vf;
294 ds->memory.bios9 = data;
295 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
296 } else {
297 mLOG(DS, WARN, "BIOS checksum incorrect");
298 vf->unmap(vf, data, size);
299 return false;
300 }
301 return true;
302}
303
304void DSGetGameCode(struct DS* ds, char* out) {
305 memset(out, 0, 8);
306 if (!ds->romVf) {
307 return;
308 }
309
310 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
311 memcpy(out, "NTR-", 4);
312 memcpy(&out[4], &cart->id, 4);
313 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
314}
315
316void DSGetGameTitle(struct DS* ds, char* out) {
317 memset(out, 0, 12);
318 if (!ds->romVf) {
319 return;
320 }
321
322 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
323 memcpy(out, &cart->title, 4);
324 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
325}
326
327void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
328 struct DS* ds = (struct DS*) cpu->master;
329 if (ds->debugger) {
330 struct mDebuggerEntryInfo info = {
331 .address = _ARMPCAddress(cpu),
332 .opcode = opcode
333 };
334 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
335 }
336 // TODO: More sensible category?
337 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
338}
339
340void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
341 struct DS* ds = (struct DS*) cpu->master;
342 if (ds->debugger) {
343 struct mDebuggerEntryInfo info = {
344 .address = _ARMPCAddress(cpu),
345 .opcode = opcode
346 };
347 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
348 } else {
349 ARMRaiseUndefined(cpu);
350 }
351}
352
353void DSBreakpoint(struct ARMCore* cpu, int immediate) {
354 struct DS* ds = (struct DS*) cpu->master;
355 if (immediate >= CPU_COMPONENT_MAX) {
356 return;
357 }
358 switch (immediate) {
359 case CPU_COMPONENT_DEBUGGER:
360 if (ds->debugger) {
361 struct mDebuggerEntryInfo info = {
362 .address = _ARMPCAddress(cpu)
363 };
364 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
365 }
366 break;
367 default:
368 break;
369 }
370}
371
372void DS7TestIRQ(struct ARMCore* cpu) {
373 struct DS* ds = (struct DS*) cpu->master;
374 if (0) {
375 ds->springIRQ7 = 1;
376 cpu->nextEvent = cpu->cycles;
377 }
378}
379
380void DS9TestIRQ(struct ARMCore* cpu) {
381 struct DS* ds = (struct DS*) cpu->master;
382 if (0) {
383 ds->springIRQ9 = 1;
384 cpu->nextEvent = cpu->cycles;
385 }
386}
387
388static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
389 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
390}
391
392static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
393 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
394 switch (opcode2) {
395 case 0:
396 cpu->cp15.r2.d = value;
397 break;
398 case 1:
399 cpu->cp15.r2.i = value;
400 break;
401 default:
402 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
403 break;
404 }
405}
406
407static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
408 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
409 switch (opcode2) {
410 case 0:
411 cpu->cp15.r3.d = value;
412 break;
413 default:
414 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
415 break;
416 }
417}
418
419static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
420 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
421}
422
423static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
424 cpu->cp15.r6.region[crm] = value;
425 uint32_t base = ARMProtectionGetBase(value) << 12;
426 uint32_t size = 2 << ARMProtectionGetSize(value);
427 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
428}
429
430static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
431 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
432}
433
434static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
435 uint32_t base = ARMTCMControlGetBase(value) << 12;
436 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
437 mLOG(DS, STUB, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
438 switch (opcode2) {
439 case 0:
440 cpu->cp15.r9.d = value;
441 break;
442 case 1:
443 cpu->cp15.r9.i = value;
444 break;
445 default:
446 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
447 break;
448 }
449}
450
451void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
452 switch (crn) {
453 default:
454 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
455 break;
456 case 0:
457 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
458 ARMRaiseUndefined(cpu);
459 break;
460 case 1:
461 _writeSysControl(cpu, crm, opcode2, value);
462 break;
463 case 2:
464 _writeCacheControl(cpu, crm, opcode2, value);
465 break;
466 case 3:
467 _writeWriteBufferControl(cpu, crm, opcode2, value);
468 break;
469 case 5:
470 _writeAccessControl(cpu, crm, opcode2, value);
471 break;
472 case 6:
473 _writeRegionConfiguration(cpu, crm, opcode2, value);
474 break;
475 case 7:
476 _writeCache(cpu, crm, opcode2, value);
477 break;
478 case 9:
479 _writeTCMControl(cpu, crm, opcode2, value);
480 break;
481 }
482}
483
484void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
485 if (io[DS7_REG_IME >> 1] && (value & io[DS7_REG_IF_LO >> 1] || (value >> 16) & io[DS7_REG_IF_HI >> 1])) {
486 ARMRaiseIRQ(cpu);
487 }
488}
489void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
490 if (value && (io[DS7_REG_IE_LO >> 1] & io[DS7_REG_IF_LO >> 1] || io[DS7_REG_IE_HI >> 1] & io[DS7_REG_IF_HI >> 1])) {
491 ARMRaiseIRQ(cpu);
492 }
493}
494
495void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
496 if (irq < 16) {
497 io[DS7_REG_IF_LO >> 1] |= 1 << irq;
498 } else {
499 io[DS7_REG_IF_HI >> 1] |= 1 << (irq - 16);
500 }
501 cpu->halted = 0;
502
503 if (!io[DS7_REG_IME >> 1]) {
504 return;
505 }
506 if (irq < 16 && (io[DS7_REG_IE_LO >> 1] & 1 << irq)) {
507 ARMRaiseIRQ(cpu);
508 } else if (io[DS7_REG_IE_HI >> 1] & 1 << (irq - 16)) {
509 ARMRaiseIRQ(cpu);
510 }
511}