src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/math.h"
16#include "util/memory.h"
17
18#define IDLE_LOOP_THRESHOLD 10000
19
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25static int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait);
26
27static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
28static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 9 };
29static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
30static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 9 };
31static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
32static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
33static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
34
35void GBAMemoryInit(struct GBA* gba) {
36 struct ARMCore* cpu = gba->cpu;
37 cpu->memory.load32 = GBALoad32;
38 cpu->memory.load16 = GBALoad16;
39 cpu->memory.load8 = GBALoad8;
40 cpu->memory.loadMultiple = GBALoadMultiple;
41 cpu->memory.store32 = GBAStore32;
42 cpu->memory.store16 = GBAStore16;
43 cpu->memory.store8 = GBAStore8;
44 cpu->memory.storeMultiple = GBAStoreMultiple;
45 cpu->memory.stall = GBAMemoryStall;
46
47 gba->memory.bios = (uint32_t*) hleBios;
48 gba->memory.fullBios = 0;
49 gba->memory.wram = 0;
50 gba->memory.iwram = 0;
51 gba->memory.rom = 0;
52 gba->memory.romSize = 0;
53 gba->memory.romMask = 0;
54 gba->memory.hw.p = gba;
55
56 int i;
57 for (i = 0; i < 16; ++i) {
58 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
59 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
60 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
61 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
62 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
63 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
64 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
65 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
66 }
67 for (; i < 256; ++i) {
68 gba->memory.waitstatesNonseq16[i] = 0;
69 gba->memory.waitstatesSeq16[i] = 0;
70 gba->memory.waitstatesNonseq32[i] = 0;
71 gba->memory.waitstatesSeq32[i] = 0;
72 }
73
74 gba->memory.activeRegion = -1;
75 cpu->memory.activeRegion = 0;
76 cpu->memory.activeMask = 0;
77 cpu->memory.setActiveRegion = GBASetActiveRegion;
78 cpu->memory.activeSeqCycles32 = 0;
79 cpu->memory.activeSeqCycles16 = 0;
80 cpu->memory.activeNonseqCycles32 = 0;
81 cpu->memory.activeNonseqCycles16 = 0;
82 gba->memory.biosPrefetch = 0;
83}
84
85void GBAMemoryDeinit(struct GBA* gba) {
86 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
87 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
88 if (gba->memory.rom) {
89 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
90 }
91 GBASavedataDeinit(&gba->memory.savedata);
92}
93
94void GBAMemoryReset(struct GBA* gba) {
95 if (gba->memory.wram) {
96 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
97 }
98 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
99 if (gba->pristineRom && !gba->memory.rom) {
100 // Multiboot
101 memcpy(gba->memory.wram, gba->pristineRom, gba->pristineRomSize);
102 }
103
104 if (gba->memory.iwram) {
105 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
106 }
107 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
108
109 memset(gba->memory.io, 0, sizeof(gba->memory.io));
110 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
111 int i;
112 for (i = 0; i < 4; ++i) {
113 gba->memory.dma[i].count = 0x4000;
114 gba->memory.dma[i].nextEvent = INT_MAX;
115 }
116 gba->memory.dma[3].count = 0x10000;
117 gba->memory.activeDMA = -1;
118 gba->memory.nextDMA = INT_MAX;
119 gba->memory.eventDiff = 0;
120
121 gba->memory.prefetch = false;
122 gba->memory.lastPrefetchedPc = 0;
123
124 if (!gba->memory.wram || !gba->memory.iwram) {
125 GBAMemoryDeinit(gba);
126 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
127 }
128}
129
130static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
131 struct ARMInstructionInfo info;
132 uint32_t nextAddress = address;
133 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
134 if (cpu->executionMode == MODE_THUMB) {
135 while (true) {
136 uint16_t opcode;
137 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
138 ARMDecodeThumb(opcode, &info);
139 switch (info.branchType) {
140 case ARM_BRANCH_NONE:
141 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
142 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
143 gba->idleDetectionStep = -1;
144 return;
145 }
146 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
147 uint32_t offset = 0;
148 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
149 offset = info.memory.offset.immediate;
150 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
151 int reg = info.memory.offset.reg;
152 if (gba->cachedRegisters[reg]) {
153 gba->idleDetectionStep = -1;
154 return;
155 }
156 offset = gba->cachedRegisters[reg];
157 }
158 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
159 loadAddress -= offset;
160 } else {
161 loadAddress += offset;
162 }
163 if ((loadAddress >> BASE_OFFSET) == REGION_IO && !GBAIOIsReadConstant(loadAddress)) {
164 gba->idleDetectionStep = -1;
165 return;
166 }
167 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
168 gba->taintedRegisters[info.op1.reg] = true;
169 } else {
170 switch (info.memory.width) {
171 case 1:
172 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
173 break;
174 case 2:
175 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
176 break;
177 case 4:
178 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
179 break;
180 }
181 }
182 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
183 gba->taintedRegisters[info.op1.reg] = true;
184 }
185 nextAddress += WORD_SIZE_THUMB;
186 break;
187 case ARM_BRANCH:
188 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
189 gba->idleLoop = address;
190 gba->idleOptimization = IDLE_LOOP_REMOVE;
191 }
192 gba->idleDetectionStep = -1;
193 return;
194 default:
195 gba->idleDetectionStep = -1;
196 return;
197 }
198 }
199 } else {
200 gba->idleDetectionStep = -1;
201 }
202}
203
204static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
205 struct GBA* gba = (struct GBA*) cpu->master;
206 struct GBAMemory* memory = &gba->memory;
207
208 int newRegion = address >> BASE_OFFSET;
209 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
210 if (address == gba->idleLoop) {
211 if (gba->haltPending) {
212 gba->haltPending = false;
213 GBAHalt(gba);
214 } else {
215 gba->haltPending = true;
216 }
217 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
218 if (address == gba->lastJump) {
219 switch (gba->idleDetectionStep) {
220 case 0:
221 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
222 ++gba->idleDetectionStep;
223 break;
224 case 1:
225 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
226 gba->idleDetectionStep = -1;
227 ++gba->idleDetectionFailures;
228 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
229 gba->idleOptimization = IDLE_LOOP_IGNORE;
230 }
231 break;
232 }
233 _analyzeForIdleLoop(gba, cpu, address);
234 break;
235 }
236 } else {
237 gba->idleDetectionStep = 0;
238 }
239 }
240 }
241
242 gba->lastJump = address;
243 memory->lastPrefetchedPc = 0;
244 memory->lastPrefetchedLoads = 0;
245 if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
246 return;
247 }
248
249 if (memory->activeRegion == REGION_BIOS) {
250 memory->biosPrefetch = cpu->prefetch[1];
251 }
252 memory->activeRegion = newRegion;
253 switch (newRegion) {
254 case REGION_BIOS:
255 cpu->memory.activeRegion = memory->bios;
256 cpu->memory.activeMask = SIZE_BIOS - 1;
257 break;
258 case REGION_WORKING_RAM:
259 cpu->memory.activeRegion = memory->wram;
260 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
261 break;
262 case REGION_WORKING_IRAM:
263 cpu->memory.activeRegion = memory->iwram;
264 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
265 break;
266 case REGION_VRAM:
267 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
268 cpu->memory.activeMask = 0x0000FFFF;
269 break;
270 case REGION_CART0:
271 case REGION_CART0_EX:
272 case REGION_CART1:
273 case REGION_CART1_EX:
274 case REGION_CART2:
275 case REGION_CART2_EX:
276 cpu->memory.activeRegion = memory->rom;
277 cpu->memory.activeMask = memory->romMask;
278 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
279 break;
280 }
281 // Fall through
282 default:
283 memory->activeRegion = -1;
284 cpu->memory.activeRegion = _deadbeef;
285 cpu->memory.activeMask = 0;
286 enum GBALogLevel errorLevel = GBA_LOG_FATAL;
287 if (gba->yankedRomSize || !gba->hardCrash) {
288 errorLevel = GBA_LOG_GAME_ERROR;
289 }
290 GBALog(gba, errorLevel, "Jumped to invalid address: %08X", address);
291 return;
292 }
293 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
294 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
295 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
296 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
297}
298
299#define LOAD_BAD \
300 if (gba->performingDMA) { \
301 value = gba->bus; \
302 } else { \
303 value = cpu->prefetch[1]; \
304 if (cpu->executionMode == MODE_THUMB) { \
305 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
306 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
307 case REGION_BIOS: \
308 case REGION_OAM: \
309 /* This isn't right half the time, but we don't have $+6 handy */ \
310 value <<= 16; \
311 value |= cpu->prefetch[0]; \
312 break; \
313 case REGION_WORKING_IRAM: \
314 /* This doesn't handle prefetch clobbering */ \
315 if (cpu->gprs[ARM_PC] & 2) { \
316 value |= cpu->prefetch[0] << 16; \
317 } else { \
318 value <<= 16; \
319 value |= cpu->prefetch[0]; \
320 } \
321 default: \
322 value |= value << 16; \
323 } \
324 } \
325 }
326
327#define LOAD_BIOS \
328 if (address < SIZE_BIOS) { \
329 if (memory->activeRegion == REGION_BIOS) { \
330 LOAD_32(value, address, memory->bios); \
331 } else { \
332 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
333 value = memory->biosPrefetch; \
334 } \
335 } else { \
336 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
337 LOAD_BAD; \
338 }
339
340#define LOAD_WORKING_RAM \
341 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
342 wait += waitstatesRegion[REGION_WORKING_RAM];
343
344#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
345#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
346
347#define LOAD_PALETTE_RAM \
348 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
349 wait += waitstatesRegion[REGION_PALETTE_RAM];
350
351#define LOAD_VRAM \
352 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
353 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
354 } else { \
355 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
356 } \
357 wait += waitstatesRegion[REGION_VRAM];
358
359#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
360
361#define LOAD_CART \
362 wait += waitstatesRegion[address >> BASE_OFFSET]; \
363 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
364 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
365 } else { \
366 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
367 value = ((address & ~3) >> 1) & 0xFFFF; \
368 value |= (((address & ~3) + 2) >> 1) << 16; \
369 }
370
371#define LOAD_SRAM \
372 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
373 value = GBALoad8(cpu, address, 0); \
374 value |= value << 8; \
375 value |= value << 16;
376
377uint32_t GBALoadBad(struct ARMCore* cpu) {
378 struct GBA* gba = (struct GBA*) cpu->master;
379 uint32_t value = 0;
380 LOAD_BAD;
381 return value;
382}
383
384uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
385 struct GBA* gba = (struct GBA*) cpu->master;
386 struct GBAMemory* memory = &gba->memory;
387 uint32_t value = 0;
388 int wait = 0;
389 char* waitstatesRegion = memory->waitstatesNonseq32;
390
391 switch (address >> BASE_OFFSET) {
392 case REGION_BIOS:
393 LOAD_BIOS;
394 break;
395 case REGION_WORKING_RAM:
396 LOAD_WORKING_RAM;
397 break;
398 case REGION_WORKING_IRAM:
399 LOAD_WORKING_IRAM;
400 break;
401 case REGION_IO:
402 LOAD_IO;
403 break;
404 case REGION_PALETTE_RAM:
405 LOAD_PALETTE_RAM;
406 break;
407 case REGION_VRAM:
408 LOAD_VRAM;
409 break;
410 case REGION_OAM:
411 LOAD_OAM;
412 break;
413 case REGION_CART0:
414 case REGION_CART0_EX:
415 case REGION_CART1:
416 case REGION_CART1_EX:
417 case REGION_CART2:
418 case REGION_CART2_EX:
419 LOAD_CART;
420 break;
421 case REGION_CART_SRAM:
422 case REGION_CART_SRAM_MIRROR:
423 LOAD_SRAM;
424 break;
425 default:
426 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
427 LOAD_BAD;
428 break;
429 }
430
431 if (cycleCounter) {
432 wait += 2;
433 if (address >> BASE_OFFSET < REGION_CART0) {
434 wait = GBAMemoryStall(cpu, wait);
435 }
436 *cycleCounter += wait;
437 }
438 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
439 int rotate = (address & 3) << 3;
440 return ROR(value, rotate);
441}
442
443uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
444 struct GBA* gba = (struct GBA*) cpu->master;
445 struct GBAMemory* memory = &gba->memory;
446 uint32_t value = 0;
447 int wait = 0;
448
449 switch (address >> BASE_OFFSET) {
450 case REGION_BIOS:
451 if (address < SIZE_BIOS) {
452 if (memory->activeRegion == REGION_BIOS) {
453 LOAD_16(value, address, memory->bios);
454 } else {
455 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
456 value = (memory->biosPrefetch >> ((address & 2) * 8)) & 0xFFFF;
457 }
458 } else {
459 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
460 LOAD_BAD;
461 value = (value >> ((address & 2) * 8)) & 0xFFFF;
462 }
463 break;
464 case REGION_WORKING_RAM:
465 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
466 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
467 break;
468 case REGION_WORKING_IRAM:
469 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
470 break;
471 case REGION_IO:
472 value = GBAIORead(gba, address & (SIZE_IO - 2));
473 break;
474 case REGION_PALETTE_RAM:
475 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
476 break;
477 case REGION_VRAM:
478 if ((address & 0x0001FFFF) < SIZE_VRAM) {
479 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
480 } else {
481 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
482 }
483 break;
484 case REGION_OAM:
485 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
486 break;
487 case REGION_CART0:
488 case REGION_CART0_EX:
489 case REGION_CART1:
490 case REGION_CART1_EX:
491 case REGION_CART2:
492 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
493 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
494 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
495 } else {
496 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
497 value = (address >> 1) & 0xFFFF;
498 }
499 break;
500 case REGION_CART2_EX:
501 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
502 if (memory->savedata.type == SAVEDATA_EEPROM) {
503 value = GBASavedataReadEEPROM(&memory->savedata);
504 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
505 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
506 } else {
507 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
508 value = (address >> 1) & 0xFFFF;
509 }
510 break;
511 case REGION_CART_SRAM:
512 case REGION_CART_SRAM_MIRROR:
513 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
514 value = GBALoad8(cpu, address, 0);
515 value |= value << 8;
516 break;
517 default:
518 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
519 LOAD_BAD;
520 value = (value >> ((address & 2) * 8)) & 0xFFFF;
521 break;
522 }
523
524 if (cycleCounter) {
525 wait += 2;
526 if (address >> BASE_OFFSET < REGION_CART0) {
527 wait = GBAMemoryStall(cpu, wait);
528 }
529 *cycleCounter += wait;
530 }
531 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
532 int rotate = (address & 1) << 3;
533 return ROR(value, rotate);
534}
535
536uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
537 struct GBA* gba = (struct GBA*) cpu->master;
538 struct GBAMemory* memory = &gba->memory;
539 uint32_t value = 0;
540 int wait = 0;
541
542 switch (address >> BASE_OFFSET) {
543 case REGION_BIOS:
544 if (address < SIZE_BIOS) {
545 if (memory->activeRegion == REGION_BIOS) {
546 value = ((uint8_t*) memory->bios)[address];
547 } else {
548 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
549 value = (memory->biosPrefetch >> ((address & 3) * 8)) & 0xFF;
550 }
551 } else {
552 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
553 LOAD_BAD;
554 value = (value >> ((address & 3) * 8)) & 0xFF;
555 }
556 break;
557 case REGION_WORKING_RAM:
558 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
559 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
560 break;
561 case REGION_WORKING_IRAM:
562 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
563 break;
564 case REGION_IO:
565 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
566 break;
567 case REGION_PALETTE_RAM:
568 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
569 break;
570 case REGION_VRAM:
571 if ((address & 0x0001FFFF) < SIZE_VRAM) {
572 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
573 } else {
574 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
575 }
576 break;
577 case REGION_OAM:
578 value = ((uint8_t*) gba->video.oam.raw)[address & (SIZE_OAM - 1)];
579 break;
580 case REGION_CART0:
581 case REGION_CART0_EX:
582 case REGION_CART1:
583 case REGION_CART1_EX:
584 case REGION_CART2:
585 case REGION_CART2_EX:
586 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
587 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
588 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
589 } else {
590 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
591 value = (address >> 1) & 0xFF;
592 }
593 break;
594 case REGION_CART_SRAM:
595 case REGION_CART_SRAM_MIRROR:
596 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
597 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
598 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
599 GBASavedataInitSRAM(&memory->savedata);
600 }
601 if (gba->performingDMA == 1) {
602 break;
603 }
604 if (memory->savedata.type == SAVEDATA_SRAM) {
605 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
606 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
607 value = GBASavedataReadFlash(&memory->savedata, address);
608 } else if (memory->hw.devices & HW_TILT) {
609 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
610 } else {
611 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
612 value = 0xFF;
613 }
614 value &= 0xFF;
615 break;
616 default:
617 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
618 LOAD_BAD;
619 value = (value >> ((address & 3) * 8)) & 0xFF;
620 break;
621 }
622
623 if (cycleCounter) {
624 wait += 2;
625 if (address >> BASE_OFFSET < REGION_CART0) {
626 wait = GBAMemoryStall(cpu, wait);
627 }
628 *cycleCounter += wait;
629 }
630 return value;
631}
632
633#define STORE_WORKING_RAM \
634 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
635 wait += waitstatesRegion[REGION_WORKING_RAM];
636
637#define STORE_WORKING_IRAM \
638 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
639
640#define STORE_IO \
641 GBAIOWrite32(gba, address & (SIZE_IO - 4), value);
642
643#define STORE_PALETTE_RAM \
644 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
645 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
646 wait += waitstatesRegion[REGION_PALETTE_RAM]; \
647 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
648
649#define STORE_VRAM \
650 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
651 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
652 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x0001FFFC) + 2); \
653 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x0001FFFC)); \
654 } else { \
655 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
656 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x00017FFC) + 2); \
657 gba->video.renderer->writeVRAM(gba->video.renderer, (address & 0x00017FFC)); \
658 } \
659 wait += waitstatesRegion[REGION_VRAM];
660
661#define STORE_OAM \
662 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
663 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
664 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
665
666#define STORE_CART \
667 wait += waitstatesRegion[address >> BASE_OFFSET]; \
668 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
669
670#define STORE_SRAM \
671 if (address & 0x3) { \
672 GBALog(gba, GBA_LOG_GAME_ERROR, "Unaligned SRAM Store32: 0x%08X", address); \
673 value = 0; \
674 } \
675 GBAStore8(cpu, address & ~0x3, value, cycleCounter); \
676 GBAStore8(cpu, (address & ~0x3) | 1, value, cycleCounter); \
677 GBAStore8(cpu, (address & ~0x3) | 2, value, cycleCounter); \
678 GBAStore8(cpu, (address & ~0x3) | 3, value, cycleCounter);
679
680#define STORE_BAD \
681 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
682
683void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
684 struct GBA* gba = (struct GBA*) cpu->master;
685 struct GBAMemory* memory = &gba->memory;
686 int wait = 0;
687 char* waitstatesRegion = memory->waitstatesNonseq32;
688
689 switch (address >> BASE_OFFSET) {
690 case REGION_WORKING_RAM:
691 STORE_WORKING_RAM;
692 break;
693 case REGION_WORKING_IRAM:
694 STORE_WORKING_IRAM
695 break;
696 case REGION_IO:
697 STORE_IO;
698 break;
699 case REGION_PALETTE_RAM:
700 STORE_PALETTE_RAM;
701 break;
702 case REGION_VRAM:
703 STORE_VRAM;
704 break;
705 case REGION_OAM:
706 STORE_OAM;
707 break;
708 case REGION_CART0:
709 case REGION_CART0_EX:
710 case REGION_CART1:
711 case REGION_CART1_EX:
712 case REGION_CART2:
713 case REGION_CART2_EX:
714 STORE_CART;
715 break;
716 case REGION_CART_SRAM:
717 case REGION_CART_SRAM_MIRROR:
718 STORE_SRAM;
719 break;
720 default:
721 STORE_BAD;
722 break;
723 }
724
725 if (cycleCounter) {
726 ++wait;
727 if (address >> BASE_OFFSET < REGION_CART0) {
728 wait = GBAMemoryStall(cpu, wait);
729 }
730 *cycleCounter += wait;
731 }
732}
733
734void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
735 struct GBA* gba = (struct GBA*) cpu->master;
736 struct GBAMemory* memory = &gba->memory;
737 int wait = 0;
738
739 switch (address >> BASE_OFFSET) {
740 case REGION_WORKING_RAM:
741 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
742 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
743 break;
744 case REGION_WORKING_IRAM:
745 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
746 break;
747 case REGION_IO:
748 GBAIOWrite(gba, address & (SIZE_IO - 2), value);
749 break;
750 case REGION_PALETTE_RAM:
751 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
752 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
753 break;
754 case REGION_VRAM:
755 if ((address & 0x0001FFFF) < SIZE_VRAM) {
756 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
757 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x0001FFFE);
758 } else {
759 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
760 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x00017FFE);
761 }
762 break;
763 case REGION_OAM:
764 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
765 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
766 break;
767 case REGION_CART0:
768 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
769 uint32_t reg = address & 0xFFFFFE;
770 GBAHardwareGPIOWrite(&memory->hw, reg, value);
771 } else {
772 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
773 }
774 break;
775 case REGION_CART2_EX:
776 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
777 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
778 GBASavedataInitEEPROM(&memory->savedata);
779 }
780 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
781 break;
782 case REGION_CART_SRAM:
783 case REGION_CART_SRAM_MIRROR:
784 GBAStore8(cpu, (address & ~0x1), value, cycleCounter);
785 GBAStore8(cpu, (address & ~0x1) | 1, value, cycleCounter);
786 break;
787 default:
788 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
789 break;
790 }
791
792 if (cycleCounter) {
793 ++wait;
794 if (address >> BASE_OFFSET < REGION_CART0) {
795 wait = GBAMemoryStall(cpu, wait);
796 }
797 *cycleCounter += wait;
798 }
799}
800
801void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
802 struct GBA* gba = (struct GBA*) cpu->master;
803 struct GBAMemory* memory = &gba->memory;
804 int wait = 0;
805
806 switch (address >> BASE_OFFSET) {
807 case REGION_WORKING_RAM:
808 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
809 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
810 break;
811 case REGION_WORKING_IRAM:
812 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
813 break;
814 case REGION_IO:
815 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
816 break;
817 case REGION_PALETTE_RAM:
818 GBAStore16(cpu, address & ~1, ((uint8_t) value) | ((uint8_t) value << 8), cycleCounter);
819 break;
820 case REGION_VRAM:
821 if ((address & 0x0001FFFF) >= 0x00010000) {
822 // TODO: check BG mode
823 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
824 break;
825 }
826 gba->video.renderer->vram[(address & 0x1FFFE) >> 1] = ((uint8_t) value) | (value << 8);
827 gba->video.renderer->writeVRAM(gba->video.renderer, address & 0x0001FFFE);
828 break;
829 case REGION_OAM:
830 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
831 break;
832 case REGION_CART0:
833 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
834 break;
835 case REGION_CART_SRAM:
836 case REGION_CART_SRAM_MIRROR:
837 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
838 if (address == SAVEDATA_FLASH_BASE) {
839 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
840 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
841 } else {
842 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
843 GBASavedataInitSRAM(&memory->savedata);
844 }
845 }
846 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
847 GBASavedataWriteFlash(&memory->savedata, address, value);
848 } else if (memory->savedata.type == SAVEDATA_SRAM) {
849 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
850 memory->savedata.dirty |= SAVEDATA_DIRT_NEW;
851 } else if (memory->hw.devices & HW_TILT) {
852 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
853 } else {
854 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
855 }
856 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
857 break;
858 default:
859 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
860 break;
861 }
862
863 if (cycleCounter) {
864 ++wait;
865 if (address >> BASE_OFFSET < REGION_CART0) {
866 wait = GBAMemoryStall(cpu, wait);
867 }
868 *cycleCounter += wait;
869 }
870}
871
872void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
873 struct GBA* gba = (struct GBA*) cpu->master;
874 struct GBAMemory* memory = &gba->memory;
875 int32_t oldValue = -1;
876
877 switch (address >> BASE_OFFSET) {
878 case REGION_WORKING_RAM:
879 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
880 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
881 break;
882 case REGION_WORKING_IRAM:
883 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
884 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
885 break;
886 case REGION_IO:
887 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
888 break;
889 case REGION_PALETTE_RAM:
890 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
891 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
892 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
893 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
894 break;
895 case REGION_VRAM:
896 if ((address & 0x0001FFFF) < SIZE_VRAM) {
897 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
898 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
899 } else {
900 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
901 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
902 }
903 break;
904 case REGION_OAM:
905 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
906 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
907 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
908 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
909 break;
910 case REGION_CART0:
911 case REGION_CART0_EX:
912 case REGION_CART1:
913 case REGION_CART1_EX:
914 case REGION_CART2:
915 case REGION_CART2_EX:
916 _pristineCow(gba);
917 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
918 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
919 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
920 }
921 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
922 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
923 break;
924 case REGION_CART_SRAM:
925 case REGION_CART_SRAM_MIRROR:
926 if (memory->savedata.type == SAVEDATA_SRAM) {
927 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
928 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
929 } else {
930 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
931 }
932 break;
933 default:
934 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
935 break;
936 }
937 if (old) {
938 *old = oldValue;
939 }
940}
941
942void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
943 struct GBA* gba = (struct GBA*) cpu->master;
944 struct GBAMemory* memory = &gba->memory;
945 int16_t oldValue = -1;
946
947 switch (address >> BASE_OFFSET) {
948 case REGION_WORKING_RAM:
949 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
950 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
951 break;
952 case REGION_WORKING_IRAM:
953 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
954 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
955 break;
956 case REGION_IO:
957 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
958 break;
959 case REGION_PALETTE_RAM:
960 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
961 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
962 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
963 break;
964 case REGION_VRAM:
965 if ((address & 0x0001FFFF) < SIZE_VRAM) {
966 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
967 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
968 } else {
969 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
970 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
971 }
972 break;
973 case REGION_OAM:
974 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
975 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
976 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
977 break;
978 case REGION_CART0:
979 case REGION_CART0_EX:
980 case REGION_CART1:
981 case REGION_CART1_EX:
982 case REGION_CART2:
983 case REGION_CART2_EX:
984 _pristineCow(gba);
985 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
986 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
987 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
988 }
989 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
990 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
991 break;
992 case REGION_CART_SRAM:
993 case REGION_CART_SRAM_MIRROR:
994 if (memory->savedata.type == SAVEDATA_SRAM) {
995 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
996 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
997 } else {
998 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
999 }
1000 break;
1001 default:
1002 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
1003 break;
1004 }
1005 if (old) {
1006 *old = oldValue;
1007 }
1008}
1009
1010void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
1011 struct GBA* gba = (struct GBA*) cpu->master;
1012 struct GBAMemory* memory = &gba->memory;
1013 int8_t oldValue = -1;
1014
1015 switch (address >> BASE_OFFSET) {
1016 case REGION_WORKING_RAM:
1017 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
1018 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
1019 break;
1020 case REGION_WORKING_IRAM:
1021 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
1022 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
1023 break;
1024 case REGION_IO:
1025 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1026 break;
1027 case REGION_PALETTE_RAM:
1028 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1029 break;
1030 case REGION_VRAM:
1031 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1032 break;
1033 case REGION_OAM:
1034 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1035 break;
1036 case REGION_CART0:
1037 case REGION_CART0_EX:
1038 case REGION_CART1:
1039 case REGION_CART1_EX:
1040 case REGION_CART2:
1041 case REGION_CART2_EX:
1042 _pristineCow(gba);
1043 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1044 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1045 gba->memory.romMask = toPow2(gba->memory.romSize) - 1;
1046 }
1047 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
1048 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
1049 break;
1050 case REGION_CART_SRAM:
1051 case REGION_CART_SRAM_MIRROR:
1052 if (memory->savedata.type == SAVEDATA_SRAM) {
1053 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
1054 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
1055 } else {
1056 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1057 }
1058 break;
1059 default:
1060 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
1061 break;
1062 }
1063 if (old) {
1064 *old = oldValue;
1065 }
1066}
1067
1068#define LDM_LOOP(LDM) \
1069 for (i = 0; i < 16; i += 4) { \
1070 if (UNLIKELY(mask & (1 << i))) { \
1071 LDM; \
1072 waitstatesRegion = memory->waitstatesSeq32; \
1073 cpu->gprs[i] = value; \
1074 ++wait; \
1075 address += 4; \
1076 } \
1077 if (UNLIKELY(mask & (2 << i))) { \
1078 LDM; \
1079 waitstatesRegion = memory->waitstatesSeq32; \
1080 cpu->gprs[i + 1] = value; \
1081 ++wait; \
1082 address += 4; \
1083 } \
1084 if (UNLIKELY(mask & (4 << i))) { \
1085 LDM; \
1086 waitstatesRegion = memory->waitstatesSeq32; \
1087 cpu->gprs[i + 2] = value; \
1088 ++wait; \
1089 address += 4; \
1090 } \
1091 if (UNLIKELY(mask & (8 << i))) { \
1092 LDM; \
1093 waitstatesRegion = memory->waitstatesSeq32; \
1094 cpu->gprs[i + 3] = value; \
1095 ++wait; \
1096 address += 4; \
1097 } \
1098 }
1099
1100uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1101 struct GBA* gba = (struct GBA*) cpu->master;
1102 struct GBAMemory* memory = &gba->memory;
1103 uint32_t value;
1104 int wait = 0;
1105 char* waitstatesRegion = memory->waitstatesNonseq32;
1106
1107 int i;
1108 int offset = 4;
1109 int popcount = 0;
1110 if (direction & LSM_D) {
1111 offset = -4;
1112 popcount = popcount32(mask);
1113 address -= (popcount << 2) - 4;
1114 }
1115
1116 if (direction & LSM_B) {
1117 address += offset;
1118 }
1119
1120 uint32_t addressMisalign = address & 0x3;
1121 if (address >> BASE_OFFSET < REGION_CART_SRAM) {
1122 address &= 0xFFFFFFFC;
1123 }
1124
1125 switch (address >> BASE_OFFSET) {
1126 case REGION_BIOS:
1127 LDM_LOOP(LOAD_BIOS);
1128 break;
1129 case REGION_WORKING_RAM:
1130 LDM_LOOP(LOAD_WORKING_RAM);
1131 break;
1132 case REGION_WORKING_IRAM:
1133 LDM_LOOP(LOAD_WORKING_IRAM);
1134 break;
1135 case REGION_IO:
1136 LDM_LOOP(LOAD_IO);
1137 break;
1138 case REGION_PALETTE_RAM:
1139 LDM_LOOP(LOAD_PALETTE_RAM);
1140 break;
1141 case REGION_VRAM:
1142 LDM_LOOP(LOAD_VRAM);
1143 break;
1144 case REGION_OAM:
1145 LDM_LOOP(LOAD_OAM);
1146 break;
1147 case REGION_CART0:
1148 case REGION_CART0_EX:
1149 case REGION_CART1:
1150 case REGION_CART1_EX:
1151 case REGION_CART2:
1152 case REGION_CART2_EX:
1153 LDM_LOOP(LOAD_CART);
1154 break;
1155 case REGION_CART_SRAM:
1156 case REGION_CART_SRAM_MIRROR:
1157 LDM_LOOP(LOAD_SRAM);
1158 break;
1159 default:
1160 LDM_LOOP(LOAD_BAD);
1161 break;
1162 }
1163
1164 if (cycleCounter) {
1165 ++wait;
1166 if (address >> BASE_OFFSET < REGION_CART0) {
1167 wait = GBAMemoryStall(cpu, wait);
1168 }
1169 *cycleCounter += wait;
1170 }
1171
1172 if (direction & LSM_B) {
1173 address -= offset;
1174 }
1175
1176 if (direction & LSM_D) {
1177 address -= (popcount << 2) + 4;
1178 }
1179
1180 return address | addressMisalign;
1181}
1182
1183#define STM_LOOP(STM) \
1184 for (i = 0; i < 16; i += 4) { \
1185 if (UNLIKELY(mask & (1 << i))) { \
1186 value = cpu->gprs[i]; \
1187 STM; \
1188 waitstatesRegion = memory->waitstatesSeq32; \
1189 ++wait; \
1190 address += 4; \
1191 } \
1192 if (UNLIKELY(mask & (2 << i))) { \
1193 value = cpu->gprs[i + 1]; \
1194 STM; \
1195 waitstatesRegion = memory->waitstatesSeq32; \
1196 ++wait; \
1197 address += 4; \
1198 } \
1199 if (UNLIKELY(mask & (4 << i))) { \
1200 value = cpu->gprs[i + 2]; \
1201 STM; \
1202 waitstatesRegion = memory->waitstatesSeq32; \
1203 ++wait; \
1204 address += 4; \
1205 } \
1206 if (UNLIKELY(mask & (8 << i))) { \
1207 value = cpu->gprs[i + 3]; \
1208 STM; \
1209 waitstatesRegion = memory->waitstatesSeq32; \
1210 ++wait; \
1211 address += 4; \
1212 } \
1213 }
1214
1215uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1216 struct GBA* gba = (struct GBA*) cpu->master;
1217 struct GBAMemory* memory = &gba->memory;
1218 uint32_t value;
1219 int wait = 0;
1220 char* waitstatesRegion = memory->waitstatesNonseq32;
1221
1222 int i;
1223 int offset = 4;
1224 int popcount = 0;
1225 if (direction & LSM_D) {
1226 offset = -4;
1227 popcount = popcount32(mask);
1228 address -= (popcount << 2) - 4;
1229 }
1230
1231 if (direction & LSM_B) {
1232 address += offset;
1233 }
1234
1235 uint32_t addressMisalign = address & 0x3;
1236 if (address >> BASE_OFFSET < REGION_CART_SRAM) {
1237 address &= 0xFFFFFFFC;
1238 }
1239
1240 switch (address >> BASE_OFFSET) {
1241 case REGION_WORKING_RAM:
1242 STM_LOOP(STORE_WORKING_RAM);
1243 break;
1244 case REGION_WORKING_IRAM:
1245 STM_LOOP(STORE_WORKING_IRAM);
1246 break;
1247 case REGION_IO:
1248 STM_LOOP(STORE_IO);
1249 break;
1250 case REGION_PALETTE_RAM:
1251 STM_LOOP(STORE_PALETTE_RAM);
1252 break;
1253 case REGION_VRAM:
1254 STM_LOOP(STORE_VRAM);
1255 break;
1256 case REGION_OAM:
1257 STM_LOOP(STORE_OAM);
1258 break;
1259 case REGION_CART0:
1260 case REGION_CART0_EX:
1261 case REGION_CART1:
1262 case REGION_CART1_EX:
1263 case REGION_CART2:
1264 case REGION_CART2_EX:
1265 STM_LOOP(STORE_CART);
1266 break;
1267 case REGION_CART_SRAM:
1268 case REGION_CART_SRAM_MIRROR:
1269 STM_LOOP(STORE_SRAM);
1270 break;
1271 default:
1272 STM_LOOP(STORE_BAD);
1273 break;
1274 }
1275
1276 if (cycleCounter) {
1277 if (address >> BASE_OFFSET < REGION_CART0) {
1278 wait = GBAMemoryStall(cpu, wait);
1279 }
1280 *cycleCounter += wait;
1281 }
1282
1283 if (direction & LSM_B) {
1284 address -= offset;
1285 }
1286
1287 if (direction & LSM_D) {
1288 address -= (popcount << 2) + 4;
1289 }
1290
1291 return address | addressMisalign;
1292}
1293
1294void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1295 struct GBAMemory* memory = &gba->memory;
1296 struct ARMCore* cpu = gba->cpu;
1297 int sram = parameters & 0x0003;
1298 int ws0 = (parameters & 0x000C) >> 2;
1299 int ws0seq = (parameters & 0x0010) >> 4;
1300 int ws1 = (parameters & 0x0060) >> 5;
1301 int ws1seq = (parameters & 0x0080) >> 7;
1302 int ws2 = (parameters & 0x0300) >> 8;
1303 int ws2seq = (parameters & 0x0400) >> 10;
1304 int prefetch = parameters & 0x4000;
1305
1306 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1307 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1308 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1309 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1310
1311 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1312 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1313 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1314
1315 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1316 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1317 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1318
1319 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1320 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1321 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1322
1323 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1324 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1325 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1326
1327 memory->prefetch = prefetch;
1328
1329 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
1330 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
1331
1332 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1333 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1334}
1335
1336static bool _isValidDMASAD(int dma, uint32_t address) {
1337 if (dma == 0 && address >= BASE_CART0 && address < BASE_CART_SRAM) {
1338 return false;
1339 }
1340 return address >= BASE_WORKING_RAM;
1341}
1342
1343static bool _isValidDMADAD(int dma, uint32_t address) {
1344 return dma == 3 || address < BASE_CART0;
1345}
1346
1347uint32_t GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1348 struct GBAMemory* memory = &gba->memory;
1349 address &= 0x0FFFFFFE;
1350 if (_isValidDMASAD(dma, address)) {
1351 memory->dma[dma].source = address;
1352 }
1353 return memory->dma[dma].source;
1354}
1355
1356uint32_t GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1357 struct GBAMemory* memory = &gba->memory;
1358 address &= 0x0FFFFFFE;
1359 if (_isValidDMADAD(dma, address)) {
1360 memory->dma[dma].dest = address;
1361 }
1362 return memory->dma[dma].dest;
1363}
1364
1365void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1366 struct GBAMemory* memory = &gba->memory;
1367 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1368}
1369
1370uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1371 struct GBAMemory* memory = &gba->memory;
1372 struct GBADMA* currentDma = &memory->dma[dma];
1373 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1374 control &= 0xFFE0;
1375 currentDma->reg = control;
1376
1377 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1378 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1379 }
1380
1381 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1382 currentDma->nextSource = currentDma->source;
1383 currentDma->nextDest = currentDma->dest;
1384 currentDma->nextCount = currentDma->count;
1385 GBAMemoryScheduleDMA(gba, dma, currentDma);
1386 }
1387 // If the DMA has already occurred, this value might have changed since the function started
1388 return currentDma->reg;
1389};
1390
1391void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1392 struct ARMCore* cpu = gba->cpu;
1393 switch (GBADMARegisterGetTiming(info->reg)) {
1394 case DMA_TIMING_NOW:
1395 info->nextEvent = cpu->cycles;
1396 GBAMemoryUpdateDMAs(gba, 0);
1397 break;
1398 case DMA_TIMING_HBLANK:
1399 // Handled implicitly
1400 info->nextEvent = INT_MAX;
1401 break;
1402 case DMA_TIMING_VBLANK:
1403 // Handled implicitly
1404 info->nextEvent = INT_MAX;
1405 break;
1406 case DMA_TIMING_CUSTOM:
1407 info->nextEvent = INT_MAX;
1408 switch (number) {
1409 case 0:
1410 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1411 break;
1412 case 1:
1413 case 2:
1414 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1415 break;
1416 case 3:
1417 // GBAVideoScheduleVCaptureDma(dma, info);
1418 break;
1419 }
1420 }
1421}
1422
1423void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1424 struct GBAMemory* memory = &gba->memory;
1425 struct GBADMA* dma;
1426 int i;
1427 for (i = 0; i < 4; ++i) {
1428 dma = &memory->dma[i];
1429 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1430 dma->nextEvent = cycles;
1431 }
1432 }
1433 GBAMemoryUpdateDMAs(gba, 0);
1434}
1435
1436void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1437 struct GBAMemory* memory = &gba->memory;
1438 struct GBADMA* dma;
1439 int i;
1440 for (i = 0; i < 4; ++i) {
1441 dma = &memory->dma[i];
1442 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1443 dma->nextEvent = cycles;
1444 }
1445 }
1446 GBAMemoryUpdateDMAs(gba, 0);
1447}
1448
1449int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1450 struct GBAMemory* memory = &gba->memory;
1451 if (memory->nextDMA == INT_MAX) {
1452 return INT_MAX;
1453 }
1454 memory->nextDMA -= cycles;
1455 memory->eventDiff += cycles;
1456 while (memory->nextDMA <= 0) {
1457 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1458 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1459 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1460 memory->eventDiff = 0;
1461 }
1462 return memory->nextDMA;
1463}
1464
1465void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1466 int i;
1467 struct GBAMemory* memory = &gba->memory;
1468 struct ARMCore* cpu = gba->cpu;
1469 memory->activeDMA = -1;
1470 memory->nextDMA = INT_MAX;
1471 for (i = 3; i >= 0; --i) {
1472 struct GBADMA* dma = &memory->dma[i];
1473 if (dma->nextEvent != INT_MAX) {
1474 dma->nextEvent -= cycles;
1475 if (GBADMARegisterIsEnable(dma->reg)) {
1476 memory->activeDMA = i;
1477 memory->nextDMA = dma->nextEvent;
1478 }
1479 }
1480 }
1481 if (memory->nextDMA < cpu->nextEvent) {
1482 cpu->nextEvent = memory->nextDMA;
1483 }
1484}
1485
1486void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1487 struct GBAMemory* memory = &gba->memory;
1488 struct ARMCore* cpu = gba->cpu;
1489 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1490 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1491 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1492 int32_t wordsRemaining = info->nextCount;
1493 uint32_t source = info->nextSource;
1494 uint32_t dest = info->nextDest;
1495 uint32_t sourceRegion = source >> BASE_OFFSET;
1496 uint32_t destRegion = dest >> BASE_OFFSET;
1497 int32_t cycles = 2;
1498
1499 if (source == info->source) {
1500 // TODO: support 4 cycles for ROM access
1501 cycles += 2;
1502 if (width == 4) {
1503 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1504 source &= 0xFFFFFFFC;
1505 dest &= 0xFFFFFFFC;
1506 } else {
1507 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1508 }
1509 } else {
1510 if (width == 4) {
1511 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1512 } else {
1513 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1514 }
1515 }
1516
1517 gba->performingDMA = 1 | (number << 1);
1518 int32_t word;
1519 if (width == 4) {
1520 word = cpu->memory.load32(cpu, source, 0);
1521 gba->bus = word;
1522 cpu->memory.store32(cpu, dest, word, 0);
1523 source += sourceOffset;
1524 dest += destOffset;
1525 --wordsRemaining;
1526 } else {
1527 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1528 word = GBASavedataReadEEPROM(&memory->savedata);
1529 gba->bus = word | (word << 16);
1530 cpu->memory.store16(cpu, dest, word, 0);
1531 source += sourceOffset;
1532 dest += destOffset;
1533 --wordsRemaining;
1534 } else if (destRegion == REGION_CART2_EX) {
1535 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1536 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1537 GBASavedataInitEEPROM(&memory->savedata);
1538 }
1539 word = cpu->memory.load16(cpu, source, 0);
1540 gba->bus = word | (word << 16);
1541 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1542 source += sourceOffset;
1543 dest += destOffset;
1544 --wordsRemaining;
1545 } else {
1546 word = cpu->memory.load16(cpu, source, 0);
1547 gba->bus = word | (word << 16);
1548 cpu->memory.store16(cpu, dest, word, 0);
1549 source += sourceOffset;
1550 dest += destOffset;
1551 --wordsRemaining;
1552 }
1553 }
1554 gba->performingDMA = 0;
1555
1556 if (!wordsRemaining) {
1557 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1558 info->reg = GBADMARegisterClearEnable(info->reg);
1559 info->nextEvent = INT_MAX;
1560
1561 // Clear the enable bit in memory
1562 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1563 } else {
1564 info->nextCount = info->count;
1565 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1566 info->nextDest = info->dest;
1567 }
1568 GBAMemoryScheduleDMA(gba, number, info);
1569 }
1570 if (GBADMARegisterIsDoIRQ(info->reg)) {
1571 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1572 }
1573 } else {
1574 info->nextDest = dest;
1575 info->nextCount = wordsRemaining;
1576 }
1577 info->nextSource = source;
1578
1579 if (info->nextEvent != INT_MAX) {
1580 info->nextEvent += cycles;
1581 }
1582 cpu->cycles += cycles;
1583}
1584
1585int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
1586 struct GBA* gba = (struct GBA*) cpu->master;
1587 struct GBAMemory* memory = &gba->memory;
1588
1589 if (memory->activeRegion < REGION_CART0 || !memory->prefetch) {
1590 // The wait is the stall
1591 return wait;
1592 }
1593
1594 int32_t s = cpu->memory.activeSeqCycles16 + 1;
1595 int32_t n2s = cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16 + 1;
1596
1597 // Figure out how many sequential loads we can jam in
1598 int32_t stall = s;
1599 int32_t loads = 1;
1600 int32_t previousLoads = 0;
1601
1602 // Don't prefetch too much if we're overlapping with a previous prefetch
1603 uint32_t dist = (memory->lastPrefetchedPc - cpu->gprs[ARM_PC]) >> 1;
1604 if (dist < memory->lastPrefetchedLoads) {
1605 previousLoads = dist;
1606 }
1607 while (stall < wait) {
1608 stall += s;
1609 ++loads;
1610 }
1611 if (loads + previousLoads > 8) {
1612 int diff = (loads + previousLoads) - 8;
1613 loads -= diff;
1614 stall -= s * diff;
1615 } else if (stall > wait && loads == 1) {
1616 // We might need to stall a bit extra if we haven't finished the first S cycle
1617 wait = stall;
1618 }
1619 // This instruction used to have an N, convert it to an S.
1620 wait -= n2s;
1621
1622 // TODO: Invalidate prefetch on branch
1623 memory->lastPrefetchedLoads = loads;
1624 memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * loads;
1625
1626 // The next |loads|S waitstates disappear entirely, so long as they're all in a row
1627 cpu->cycles -= (s - 1) * loads;
1628 return wait;
1629}
1630
1631void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1632 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1633 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1634}
1635
1636void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1637 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1638 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1639}
1640
1641void _pristineCow(struct GBA* gba) {
1642 if (gba->memory.rom != gba->pristineRom) {
1643 return;
1644 }
1645 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1646 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1647 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1648}