1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ARM_H
  7#define ARM_H
  8
  9#include "util/common.h"
 10
 11#include "core/cpu.h"
 12
 13enum {
 14	ARM_SP = 13,
 15	ARM_LR = 14,
 16	ARM_PC = 15
 17};
 18
 19enum ExecutionMode {
 20	MODE_ARM = 0,
 21	MODE_THUMB = 1
 22};
 23
 24enum PrivilegeMode {
 25	MODE_USER = 0x10,
 26	MODE_FIQ = 0x11,
 27	MODE_IRQ = 0x12,
 28	MODE_SUPERVISOR = 0x13,
 29	MODE_ABORT = 0x17,
 30	MODE_UNDEFINED = 0x1B,
 31	MODE_SYSTEM = 0x1F
 32};
 33
 34enum WordSize {
 35	WORD_SIZE_ARM = 4,
 36	WORD_SIZE_THUMB = 2
 37};
 38
 39enum ExecutionVector {
 40	BASE_RESET = 0x00000000,
 41	BASE_UNDEF = 0x00000004,
 42	BASE_SWI = 0x00000008,
 43	BASE_PABT = 0x0000000C,
 44	BASE_DABT = 0x00000010,
 45	BASE_IRQ = 0x00000018,
 46	BASE_FIQ = 0x0000001C
 47};
 48
 49enum RegisterBank {
 50	BANK_NONE = 0,
 51	BANK_FIQ = 1,
 52	BANK_IRQ = 2,
 53	BANK_SUPERVISOR = 3,
 54	BANK_ABORT = 4,
 55	BANK_UNDEFINED = 5
 56};
 57
 58enum LSMDirection {
 59	LSM_B = 1,
 60	LSM_D = 2,
 61	LSM_IA = 0,
 62	LSM_IB = 1,
 63	LSM_DA = 2,
 64	LSM_DB = 3
 65};
 66
 67struct ARMCore;
 68
 69union PSR {
 70	struct {
 71#if defined(__POWERPC__) || defined(__PPC__)
 72		unsigned n : 1;
 73		unsigned z : 1;
 74		unsigned c : 1;
 75		unsigned v : 1;
 76		unsigned : 20;
 77		unsigned i : 1;
 78		unsigned f : 1;
 79		unsigned t : 1;
 80		unsigned priv : 5;
 81#else
 82		unsigned priv : 5;
 83		unsigned t : 1;
 84		unsigned f : 1;
 85		unsigned i : 1;
 86		unsigned : 20;
 87		unsigned v : 1;
 88		unsigned c : 1;
 89		unsigned z : 1;
 90		unsigned n : 1;
 91#endif
 92	};
 93
 94	int32_t packed;
 95};
 96
 97struct ARMMemory {
 98	uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
 99	uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
100	uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
101
102	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
103	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
104	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
105
106	uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
107	                         int* cycleCounter);
108	uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
109	                          int* cycleCounter);
110
111	uint32_t* activeRegion;
112	uint32_t activeMask;
113	uint32_t activeSeqCycles32;
114	uint32_t activeSeqCycles16;
115	uint32_t activeNonseqCycles32;
116	uint32_t activeNonseqCycles16;
117	int32_t (*stall)(struct ARMCore*, int32_t wait);
118	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
119};
120
121struct ARMInterruptHandler {
122	void (*reset)(struct ARMCore* cpu);
123	void (*processEvents)(struct ARMCore* cpu);
124	void (*swi16)(struct ARMCore* cpu, int immediate);
125	void (*swi32)(struct ARMCore* cpu, int immediate);
126	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
127	void (*bkpt16)(struct ARMCore* cpu, int immediate);
128	void (*bkpt32)(struct ARMCore* cpu, int immediate);
129	void (*readCPSR)(struct ARMCore* cpu);
130
131	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
132};
133
134struct ARMCore {
135	int32_t gprs[16];
136	union PSR cpsr;
137	union PSR spsr;
138
139	int32_t cycles;
140	int32_t nextEvent;
141	int halted;
142
143	int32_t bankedRegisters[6][7];
144	int32_t bankedSPSRs[6];
145
146	int32_t shifterOperand;
147	int32_t shifterCarryOut;
148
149	uint32_t prefetch[2];
150	enum ExecutionMode executionMode;
151	enum PrivilegeMode privilegeMode;
152
153	struct ARMMemory memory;
154	struct ARMInterruptHandler irqh;
155
156	struct mCPUComponent* master;
157
158	size_t numComponents;
159	struct mCPUComponent** components;
160};
161
162void ARMInit(struct ARMCore* cpu);
163void ARMDeinit(struct ARMCore* cpu);
164void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras);
165void ARMHotplugAttach(struct ARMCore* cpu, size_t slot);
166void ARMHotplugDetach(struct ARMCore* cpu, size_t slot);
167
168void ARMReset(struct ARMCore* cpu);
169void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
170void ARMRaiseIRQ(struct ARMCore*);
171void ARMRaiseSWI(struct ARMCore*);
172void ARMRaiseUndefined(struct ARMCore*);
173
174void ARMRun(struct ARMCore* cpu);
175void ARMRunLoop(struct ARMCore* cpu);
176void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
177
178#endif