src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-gpio.h"
4#include "gba-io.h"
5#include "gba-serialize.h"
6#include "hle-bios.h"
7#include "memory.h"
8
9#include <limits.h>
10#include <string.h>
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count);
14
15static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
16static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
17static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
18static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
19static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
20static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
21static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
22
23void GBAMemoryInit(struct GBAMemory* memory) {
24 memory->d.load32 = GBALoad32;
25 memory->d.load16 = GBALoad16;
26 memory->d.loadU16 = GBALoadU16;
27 memory->d.load8 = GBALoad8;
28 memory->d.loadU8 = GBALoadU8;
29 memory->d.store32 = GBAStore32;
30 memory->d.store16 = GBAStore16;
31 memory->d.store8 = GBAStore8;
32
33 memory->bios = (uint32_t*) hleBios;
34 memory->fullBios = 0;
35 memory->wram = anonymousMemoryMap(SIZE_WORKING_RAM);
36 memory->iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
37 memory->rom = 0;
38 memory->gpio.p = memory->p;
39 memset(memory->io, 0, sizeof(memory->io));
40 memset(memory->dma, 0, sizeof(memory->dma));
41
42 if (!memory->wram || !memory->iwram) {
43 GBAMemoryDeinit(memory);
44 GBALog(memory->p, GBA_LOG_ERROR, "Could not map memory");
45 return;
46 }
47
48 int i;
49 for (i = 0; i < 16; ++i) {
50 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
51 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
52 memory->waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
53 memory->waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
54 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
55 memory->waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
56 }
57 for (; i < 256; ++i) {
58 memory->waitstates16[i] = 0;
59 memory->waitstatesSeq16[i] = 0;
60 memory->waitstatesPrefetch16[i] = 0;
61 memory->waitstates32[i] = 0;
62 memory->waitstatesSeq32[i] = 0;
63 memory->waitstatesPrefetch32[i] = 0;
64 }
65
66 memory->activeRegion = -1;
67 memory->d.activeRegion = 0;
68 memory->d.activeMask = 0;
69 memory->d.setActiveRegion = GBASetActiveRegion;
70 memory->d.activePrefetchCycles32 = 0;
71 memory->d.activePrefetchCycles16 = 0;
72 memory->biosPrefetch = 0;
73 memory->d.waitMultiple = GBAWaitMultiple;
74}
75
76void GBAMemoryDeinit(struct GBAMemory* memory) {
77 mappedMemoryFree(memory->wram, SIZE_WORKING_RAM);
78 mappedMemoryFree(memory->iwram, SIZE_WORKING_IRAM);
79 GBASavedataDeinit(&memory->savedata);
80}
81
82static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
83 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
84
85 int newRegion = address >> BASE_OFFSET;
86 if (newRegion == gbaMemory->activeRegion) {
87 return;
88 }
89 if (gbaMemory->activeRegion == REGION_BIOS) {
90 gbaMemory->biosPrefetch = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
91 }
92 gbaMemory->activeRegion = newRegion;
93 memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[gbaMemory->activeRegion];
94 memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[gbaMemory->activeRegion];
95 memory->activeNonseqCycles32 = gbaMemory->waitstates32[gbaMemory->activeRegion];
96 memory->activeNonseqCycles16 = gbaMemory->waitstates16[gbaMemory->activeRegion];
97 switch (address & ~OFFSET_MASK) {
98 case BASE_BIOS:
99 memory->activeRegion = gbaMemory->bios;
100 memory->activeMask = SIZE_BIOS - 1;
101 break;
102 case BASE_WORKING_RAM:
103 memory->activeRegion = gbaMemory->wram;
104 memory->activeMask = SIZE_WORKING_RAM - 1;
105 break;
106 case BASE_WORKING_IRAM:
107 memory->activeRegion = gbaMemory->iwram;
108 memory->activeMask = SIZE_WORKING_IRAM - 1;
109 break;
110 case BASE_CART0:
111 case BASE_CART0_EX:
112 case BASE_CART1:
113 case BASE_CART1_EX:
114 case BASE_CART2:
115 case BASE_CART2_EX:
116 memory->activeRegion = gbaMemory->rom;
117 memory->activeMask = SIZE_CART0 - 1;
118 break;
119 default:
120 memory->activeRegion = 0;
121 memory->activeMask = 0;
122 break;
123 }
124}
125
126int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
127 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
128 uint32_t value = 0;
129 int wait = 0;
130
131 switch (address & ~OFFSET_MASK) {
132 case BASE_BIOS:
133 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
134 if (address < SIZE_BIOS) {
135 LOAD_32(value, address, gbaMemory->bios);
136 } else {
137 value = 0;
138 }
139 } else {
140 value = gbaMemory->biosPrefetch;
141 }
142 break;
143 case BASE_WORKING_RAM:
144 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
145 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
146 break;
147 case BASE_WORKING_IRAM:
148 LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
149 break;
150 case BASE_IO:
151 value = GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
152 break;
153 case BASE_PALETTE_RAM:
154 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
155 break;
156 case BASE_VRAM:
157 LOAD_32(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
158 break;
159 case BASE_OAM:
160 LOAD_32(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
161 break;
162 case BASE_CART0:
163 case BASE_CART0_EX:
164 case BASE_CART1:
165 case BASE_CART1_EX:
166 case BASE_CART2:
167 case BASE_CART2_EX:
168 wait = gbaMemory->waitstates32[address >> BASE_OFFSET];
169 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
170 LOAD_32(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
171 }
172 break;
173 case BASE_CART_SRAM:
174 case BASE_CART_SRAM_MIRROR:
175 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
176 break;
177 default:
178 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
179 if (gbaMemory->p->cpu.executionMode == MODE_ARM) {
180 value = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
181 } else {
182 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_THUMB * 2, 0);
183 value |= value << 16;
184 }
185 break;
186 }
187
188
189 if (cycleCounter) {
190 *cycleCounter += 2 + wait;
191 }
192 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
193 int rotate = (address & 3) << 3;
194 return (value >> rotate) | (value << (32 - rotate));
195}
196
197uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
198 return GBALoad16(memory, address, cycleCounter);
199}
200
201int16_t GBALoad16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
202 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
203 uint16_t value = 0;
204 int wait = 0;
205
206 switch (address & ~OFFSET_MASK) {
207 case BASE_BIOS:
208 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
209 if (address < SIZE_BIOS) {
210 LOAD_16(value, address, gbaMemory->bios);
211 } else {
212 value = 0;
213 }
214 } else {
215 value = gbaMemory->biosPrefetch;
216 }
217 break;
218 case BASE_WORKING_RAM:
219 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
220 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
221 break;
222 case BASE_WORKING_IRAM:
223 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
224 break;
225 case BASE_IO:
226 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
227 break;
228 case BASE_PALETTE_RAM:
229 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
230 break;
231 case BASE_VRAM:
232 LOAD_16(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
233 break;
234 case BASE_OAM:
235 LOAD_16(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
236 break;
237 case BASE_CART0:
238 case BASE_CART0_EX:
239 case BASE_CART1:
240 case BASE_CART1_EX:
241 case BASE_CART2:
242 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
243 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
244 LOAD_16(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
245 }
246 break;
247 case BASE_CART2_EX:
248 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
249 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
250 value = GBASavedataReadEEPROM(&gbaMemory->savedata);
251 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
252 LOAD_16(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
253 }
254 break;
255 case BASE_CART_SRAM:
256 case BASE_CART_SRAM_MIRROR:
257 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
258 break;
259 default:
260 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
261 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0);
262 break;
263 }
264
265 if (cycleCounter) {
266 *cycleCounter += 2 + wait;
267 }
268 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
269 int rotate = (address & 1) << 3;
270 return (value >> rotate) | (value << (16 - rotate));
271}
272
273uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
274 return GBALoad8(memory, address, cycleCounter);
275}
276
277int8_t GBALoad8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
278 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
279 int8_t value = 0;
280 int wait = 0;
281
282 switch (address & ~OFFSET_MASK) {
283 case BASE_BIOS:
284 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
285 if (address < SIZE_BIOS) {
286 value = ((int8_t*) gbaMemory->bios)[address];
287 } else {
288 value = 0;
289 }
290 } else {
291 value = gbaMemory->biosPrefetch;
292 }
293 break;
294 case BASE_WORKING_RAM:
295 value = ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
296 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
297 break;
298 case BASE_WORKING_IRAM:
299 value = ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
300 break;
301 case BASE_IO:
302 value = (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
303 break;
304 case BASE_PALETTE_RAM:
305 value = ((int8_t*) gbaMemory->p->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
306 break;
307 case BASE_VRAM:
308 value = ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x0001FFFF];
309 break;
310 case BASE_OAM:
311 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
312 break;
313 case BASE_CART0:
314 case BASE_CART0_EX:
315 case BASE_CART1:
316 case BASE_CART1_EX:
317 case BASE_CART2:
318 case BASE_CART2_EX:
319 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
320 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
321 value = ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
322 }
323 break;
324 case BASE_CART_SRAM:
325 case BASE_CART_SRAM_MIRROR:
326 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
327 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
328 GBASavedataInitSRAM(&gbaMemory->savedata);
329 }
330 if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
331 value = gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
332 } else if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
333 value = GBASavedataReadFlash(&gbaMemory->savedata, address);
334 }
335 break;
336 default:
337 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
338 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0) >> ((address & 1) << 3);
339 break;
340 }
341
342 if (cycleCounter) {
343 *cycleCounter += 2 + wait;
344 }
345 return value;
346}
347
348void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value, int* cycleCounter) {
349 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
350 int wait = 0;
351
352 switch (address & ~OFFSET_MASK) {
353 case BASE_WORKING_RAM:
354 STORE_32(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
355 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
356 break;
357 case BASE_WORKING_IRAM:
358 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
359 break;
360 case BASE_IO:
361 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
362 break;
363 case BASE_PALETTE_RAM:
364 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
365 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
366 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
367 break;
368 case BASE_VRAM:
369 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
370 STORE_32(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
371 }
372 break;
373 case BASE_OAM:
374 STORE_32(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
375 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
376 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
377 break;
378 case BASE_CART0:
379 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
380 break;
381 case BASE_CART_SRAM:
382 case BASE_CART_SRAM_MIRROR:
383 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
384 break;
385 default:
386 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
387 break;
388 }
389
390 if (cycleCounter) {
391 *cycleCounter += 1 + wait;
392 }
393}
394
395void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value, int* cycleCounter) {
396 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
397 int wait = 0;
398
399 switch (address & ~OFFSET_MASK) {
400 case BASE_WORKING_RAM:
401 STORE_16(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
402 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
403 break;
404 case BASE_WORKING_IRAM:
405 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
406 break;
407 case BASE_IO:
408 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
409 break;
410 case BASE_PALETTE_RAM:
411 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
412 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
413 break;
414 case BASE_VRAM:
415 if ((address & OFFSET_MASK) < SIZE_VRAM) {
416 STORE_16(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
417 }
418 break;
419 case BASE_OAM:
420 STORE_16(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
421 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
422 break;
423 case BASE_CART0:
424 if (IS_GPIO_REGISTER(address & 0xFFFFFF)) {
425 uint32_t reg = address & 0xFFFFFF;
426 GBAGPIOWrite(&gbaMemory->gpio, reg, value);
427 } else {
428 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
429 }
430 break;
431 case BASE_CART2_EX:
432 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
433 GBASavedataInitEEPROM(&gbaMemory->savedata);
434 }
435 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
436 break;
437 case BASE_CART_SRAM:
438 case BASE_CART_SRAM_MIRROR:
439 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
440 break;
441 default:
442 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
443 break;
444 }
445
446 if (cycleCounter) {
447 *cycleCounter += 1 + wait;
448 }
449}
450
451void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value, int* cycleCounter) {
452 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
453 int wait = 0;
454
455 switch (address & ~OFFSET_MASK) {
456 case BASE_WORKING_RAM:
457 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
458 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
459 break;
460 case BASE_WORKING_IRAM:
461 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
462 break;
463 case BASE_IO:
464 GBAIOWrite8(gbaMemory->p, address & (SIZE_IO - 1), value);
465 break;
466 case BASE_PALETTE_RAM:
467 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
468 break;
469 case BASE_VRAM:
470 if (address >= 0x06018000) {
471 // TODO: check BG mode
472 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
473 break;
474 }
475 ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x1FFFE] = value;
476 ((int8_t*) gbaMemory->p->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
477 break;
478 case BASE_OAM:
479 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
480 break;
481 case BASE_CART0:
482 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
483 break;
484 case BASE_CART_SRAM:
485 case BASE_CART_SRAM_MIRROR:
486 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
487 if (address == SAVEDATA_FLASH_BASE) {
488 GBASavedataInitFlash(&gbaMemory->savedata);
489 } else {
490 GBASavedataInitSRAM(&gbaMemory->savedata);
491 }
492 }
493 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
494 GBASavedataWriteFlash(&gbaMemory->savedata, address, value);
495 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
496 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
497 }
498 wait = gbaMemory->waitstates16[REGION_CART_SRAM];
499 break;
500 default:
501 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
502 break;
503 }
504
505 if (cycleCounter) {
506 *cycleCounter += 1 + wait;
507 }
508}
509
510static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count) {
511 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
512 int wait = 1 + gbaMemory->waitstates32[startAddress >> BASE_OFFSET];
513 wait += (1 + gbaMemory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
514 return wait;
515}
516
517void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
518 int sram = parameters & 0x0003;
519 int ws0 = (parameters & 0x000C) >> 2;
520 int ws0seq = (parameters & 0x0010) >> 4;
521 int ws1 = (parameters & 0x0060) >> 5;
522 int ws1seq = (parameters & 0x0080) >> 7;
523 int ws2 = (parameters & 0x0300) >> 8;
524 int ws2seq = (parameters & 0x0400) >> 10;
525 int prefetch = parameters & 0x4000;
526
527 memory->waitstates16[REGION_CART_SRAM] = memory->waitstates16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
528 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
529 memory->waitstates32[REGION_CART_SRAM] = memory->waitstates32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
530 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
531
532 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
533 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
534 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
535
536 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
537 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
538 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
539
540 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
541 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
542 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
543
544 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
545 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
546 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
547
548 if (!prefetch) {
549 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
550 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
551 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
552
553 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
554 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
555 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
556 } else {
557 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
558 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
559 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
560
561 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
562 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
563 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
564 }
565
566 memory->d.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
567 memory->d.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
568 memory->d.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
569 memory->d.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
570}
571
572int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
573 struct GBADMA* dma;
574 int32_t test = INT_MAX;
575
576 dma = &memory->dma[0];
577 dma->nextIRQ -= cycles;
578 if (dma->enable && dma->doIrq && dma->nextIRQ) {
579 if (dma->nextIRQ <= 0) {
580 dma->nextIRQ = INT_MAX;
581 GBARaiseIRQ(memory->p, IRQ_DMA0);
582 } else if (dma->nextIRQ < test) {
583 test = dma->nextIRQ;
584 }
585 }
586
587 dma = &memory->dma[1];
588 dma->nextIRQ -= cycles;
589 if (dma->enable && dma->doIrq && dma->nextIRQ) {
590 if (dma->nextIRQ <= 0) {
591 dma->nextIRQ = INT_MAX;
592 GBARaiseIRQ(memory->p, IRQ_DMA1);
593 } else if (dma->nextIRQ < test) {
594 test = dma->nextIRQ;
595 }
596 }
597
598 dma = &memory->dma[2];
599 dma->nextIRQ -= cycles;
600 if (dma->enable && dma->doIrq && dma->nextIRQ) {
601 if (dma->nextIRQ <= 0) {
602 dma->nextIRQ = INT_MAX;
603 GBARaiseIRQ(memory->p, IRQ_DMA2);
604 } else if (dma->nextIRQ < test) {
605 test = dma->nextIRQ;
606 }
607 }
608
609 dma = &memory->dma[3];
610 dma->nextIRQ -= cycles;
611 if (dma->enable && dma->doIrq && dma->nextIRQ) {
612 if (dma->nextIRQ <= 0) {
613 dma->nextIRQ = INT_MAX;
614 GBARaiseIRQ(memory->p, IRQ_DMA3);
615 } else if (dma->nextIRQ < test) {
616 test = dma->nextIRQ;
617 }
618 }
619
620 return test;
621}
622
623void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
624 memory->dma[dma].source = address & 0xFFFFFFFE;
625}
626
627void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
628 memory->dma[dma].dest = address & 0xFFFFFFFE;
629}
630
631void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
632 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
633}
634
635uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
636 struct GBADMA* currentDma = &memory->dma[dma];
637 int wasEnabled = currentDma->enable;
638 currentDma->packed = control;
639 currentDma->nextIRQ = 0;
640
641 if (currentDma->drq) {
642 GBALog(memory->p, GBA_LOG_STUB, "DRQ not implemented");
643 }
644
645 if (!wasEnabled && currentDma->enable) {
646 currentDma->nextSource = currentDma->source;
647 currentDma->nextDest = currentDma->dest;
648 currentDma->nextCount = currentDma->count;
649 GBAMemoryScheduleDMA(memory, dma, currentDma);
650 }
651 // If the DMA has already occurred, this value might have changed since the function started
652 return currentDma->packed;
653};
654
655void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
656 switch (info->timing) {
657 case DMA_TIMING_NOW:
658 GBAMemoryServiceDMA(memory, number, info);
659 break;
660 case DMA_TIMING_HBLANK:
661 // Handled implicitly
662 break;
663 case DMA_TIMING_VBLANK:
664 // Handled implicitly
665 break;
666 case DMA_TIMING_CUSTOM:
667 switch (number) {
668 case 0:
669 GBALog(memory->p, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
670 break;
671 case 1:
672 case 2:
673 GBAAudioScheduleFifoDma(&memory->p->audio, number, info);
674 break;
675 case 3:
676 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
677 break;
678 }
679 }
680}
681
682void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
683 struct GBADMA* dma;
684 int i;
685 for (i = 0; i < 4; ++i) {
686 dma = &memory->dma[i];
687 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
688 GBAMemoryServiceDMA(memory, i, dma);
689 }
690 }
691}
692
693void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
694 struct GBADMA* dma;
695 int i;
696 for (i = 0; i < 4; ++i) {
697 dma = &memory->dma[i];
698 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
699 GBAMemoryServiceDMA(memory, i, dma);
700 }
701 }
702}
703
704void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
705 if (!info->enable) {
706 // There was a DMA scheduled that got canceled
707 return;
708 }
709
710 uint32_t width = info->width ? 4 : 2;
711 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
712 int destOffset = DMA_OFFSET[info->dstControl] * width;
713 int32_t wordsRemaining = info->nextCount;
714 uint32_t source = info->nextSource;
715 uint32_t dest = info->nextDest;
716 uint32_t sourceRegion = source >> BASE_OFFSET;
717 uint32_t destRegion = dest >> BASE_OFFSET;
718
719 if (width == 4) {
720 int32_t word;
721 source &= 0xFFFFFFFC;
722 dest &= 0xFFFFFFFC;
723 while (wordsRemaining--) {
724 word = memory->d.load32(&memory->d, source, 0);
725 memory->d.store32(&memory->d, dest, word, 0);
726 source += sourceOffset;
727 dest += destOffset;
728 }
729 } else {
730 uint16_t word;
731 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
732 while (wordsRemaining--) {
733 word = GBASavedataReadEEPROM(&memory->savedata);
734 memory->d.store16(&memory->d, dest, word, 0);
735 source += sourceOffset;
736 dest += destOffset;
737 }
738 } else if (destRegion == REGION_CART2_EX) {
739 if (memory->savedata.type == SAVEDATA_NONE) {
740 GBASavedataInitEEPROM(&memory->savedata);
741 }
742 while (wordsRemaining) {
743 word = memory->d.load16(&memory->d, source, 0);
744 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
745 source += sourceOffset;
746 dest += destOffset;
747 --wordsRemaining;
748 }
749 } else {
750 while (wordsRemaining--) {
751 word = memory->d.load16(&memory->d, source, 0);
752 memory->d.store16(&memory->d, dest, word, 0);
753 source += sourceOffset;
754 dest += destOffset;
755 }
756 }
757 }
758
759 if (info->doIrq) {
760 info->nextIRQ = memory->p->cpu.cycles + 2;
761 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
762 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
763 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
764 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
765 }
766
767 info->nextSource = source;
768 info->nextDest = dest;
769 info->nextCount = wordsRemaining;
770
771 if (!info->repeat) {
772 info->enable = 0;
773
774 // Clear the enable bit in memory
775 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
776 } else {
777 info->nextCount = info->count;
778 if (info->dstControl == DMA_INCREMENT_RELOAD) {
779 info->nextDest = info->dest;
780 }
781 GBAMemoryScheduleDMA(memory, number, info);
782 }
783}
784
785void GBAMemorySerialize(struct GBAMemory* memory, struct GBASerializedState* state) {
786 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
787 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
788}
789
790void GBAMemoryDeserialize(struct GBAMemory* memory, struct GBASerializedState* state) {
791 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
792 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
793}