src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-arm.h"
7
8#include "arm.h"
9#include "emitter-arm.h"
10#include "isa-inlines.h"
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 int immediate = (opcode & 0x00000F80) >> 7;
20 if (!immediate) {
21 cpu->shifterOperand = cpu->gprs[rm];
22 cpu->shifterCarryOut = cpu->cpsr.c;
23 } else {
24 cpu->shifterOperand = cpu->gprs[rm] << immediate;
25 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
26 }
27}
28
29static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
30 int rm = opcode & 0x0000000F;
31 int rs = (opcode >> 8) & 0x0000000F;
32 ++cpu->cycles;
33 int shift = cpu->gprs[rs];
34 if (rs == ARM_PC) {
35 shift += 4;
36 }
37 shift &= 0xFF;
38 int32_t shiftVal = cpu->gprs[rm];
39 if (rm == ARM_PC) {
40 shiftVal += 4;
41 }
42 if (!shift) {
43 cpu->shifterOperand = shiftVal;
44 cpu->shifterCarryOut = cpu->cpsr.c;
45 } else if (shift < 32) {
46 cpu->shifterOperand = shiftVal << shift;
47 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
48 } else if (shift == 32) {
49 cpu->shifterOperand = 0;
50 cpu->shifterCarryOut = shiftVal & 1;
51 } else {
52 cpu->shifterOperand = 0;
53 cpu->shifterCarryOut = 0;
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 int immediate = (opcode & 0x00000F80) >> 7;
60 if (immediate) {
61 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
62 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
63 } else {
64 cpu->shifterOperand = 0;
65 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
66 }
67}
68
69static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
70 int rm = opcode & 0x0000000F;
71 int rs = (opcode >> 8) & 0x0000000F;
72 ++cpu->cycles;
73 int shift = cpu->gprs[rs];
74 if (rs == ARM_PC) {
75 shift += 4;
76 }
77 shift &= 0xFF;
78 uint32_t shiftVal = cpu->gprs[rm];
79 if (rm == ARM_PC) {
80 shiftVal += 4;
81 }
82 if (!shift) {
83 cpu->shifterOperand = shiftVal;
84 cpu->shifterCarryOut = cpu->cpsr.c;
85 } else if (shift < 32) {
86 cpu->shifterOperand = shiftVal >> shift;
87 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
88 } else if (shift == 32) {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = shiftVal >> 31;
91 } else {
92 cpu->shifterOperand = 0;
93 cpu->shifterCarryOut = 0;
94 }
95}
96
97static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
98 int rm = opcode & 0x0000000F;
99 int immediate = (opcode & 0x00000F80) >> 7;
100 if (immediate) {
101 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
102 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
103 } else {
104 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
105 cpu->shifterOperand = cpu->shifterCarryOut;
106 }
107}
108
109static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
110 int rm = opcode & 0x0000000F;
111 int rs = (opcode >> 8) & 0x0000000F;
112 ++cpu->cycles;
113 int shift = cpu->gprs[rs];
114 if (rs == ARM_PC) {
115 shift += 4;
116 }
117 shift &= 0xFF;
118 int shiftVal = cpu->gprs[rm];
119 if (rm == ARM_PC) {
120 shiftVal += 4;
121 }
122 if (!shift) {
123 cpu->shifterOperand = shiftVal;
124 cpu->shifterCarryOut = cpu->cpsr.c;
125 } else if (shift < 32) {
126 cpu->shifterOperand = shiftVal >> shift;
127 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
128 } else if (cpu->gprs[rm] >> 31) {
129 cpu->shifterOperand = 0xFFFFFFFF;
130 cpu->shifterCarryOut = 1;
131 } else {
132 cpu->shifterOperand = 0;
133 cpu->shifterCarryOut = 0;
134 }
135}
136
137static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
138 int rm = opcode & 0x0000000F;
139 int immediate = (opcode & 0x00000F80) >> 7;
140 if (immediate) {
141 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
142 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
143 } else {
144 // RRX
145 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
146 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
147 }
148}
149
150static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
151 int rm = opcode & 0x0000000F;
152 int rs = (opcode >> 8) & 0x0000000F;
153 ++cpu->cycles;
154 int shift = cpu->gprs[rs];
155 if (rs == ARM_PC) {
156 shift += 4;
157 }
158 shift &= 0xFF;
159 int shiftVal = cpu->gprs[rm];
160 if (rm == ARM_PC) {
161 shiftVal += 4;
162 }
163 int rotate = shift & 0x1F;
164 if (!shift) {
165 cpu->shifterOperand = shiftVal;
166 cpu->shifterCarryOut = cpu->cpsr.c;
167 } else if (rotate) {
168 cpu->shifterOperand = ROR(shiftVal, rotate);
169 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
170 } else {
171 cpu->shifterOperand = shiftVal;
172 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
173 }
174}
175
176static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
177 int rotate = (opcode & 0x00000F00) >> 7;
178 int immediate = opcode & 0x000000FF;
179 if (!rotate) {
180 cpu->shifterOperand = immediate;
181 cpu->shifterCarryOut = cpu->cpsr.c;
182 } else {
183 cpu->shifterOperand = ROR(immediate, rotate);
184 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
185 }
186}
187
188// Instruction definitions
189// Beware pre-processor antics
190
191#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
192
193#define ARM_ADDITION_S(M, N, D) \
194 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
195 cpu->cpsr = cpu->spsr; \
196 _ARMReadCPSR(cpu); \
197 } else { \
198 cpu->cpsr.n = ARM_SIGN(D); \
199 cpu->cpsr.z = !(D); \
200 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
201 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
202 }
203
204#define ARM_SUBTRACTION_S(M, N, D) \
205 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
206 cpu->cpsr = cpu->spsr; \
207 _ARMReadCPSR(cpu); \
208 } else { \
209 cpu->cpsr.n = ARM_SIGN(D); \
210 cpu->cpsr.z = !(D); \
211 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
212 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
213 }
214
215#define ARM_NEUTRAL_S(M, N, D) \
216 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
217 cpu->cpsr = cpu->spsr; \
218 _ARMReadCPSR(cpu); \
219 } else { \
220 cpu->cpsr.n = ARM_SIGN(D); \
221 cpu->cpsr.z = !(D); \
222 cpu->cpsr.c = cpu->shifterCarryOut; \
223 }
224
225#define ARM_NEUTRAL_HI_S(DLO, DHI) \
226 cpu->cpsr.n = ARM_SIGN(DHI); \
227 cpu->cpsr.z = !((DHI) | (DLO));
228
229#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
230#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
231#define ADDR_MODE_2_ADDRESS (address)
232#define ADDR_MODE_2_RN (cpu->gprs[rn])
233#define ADDR_MODE_2_RM (cpu->gprs[rm])
234#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
235#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
236#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
237#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
238#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
239#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
240#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
241
242#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
243#define ADDR_MODE_3_RN ADDR_MODE_2_RN
244#define ADDR_MODE_3_RM ADDR_MODE_2_RM
245#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
246#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
247#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
248
249#define ADDR_MODE_4_WRITEBACK_LDM \
250 if (!((1 << rn) & rs)) { \
251 cpu->gprs[rn] = address; \
252 }
253
254#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
255
256#define ARM_LOAD_POST_BODY \
257 ++currentCycles; \
258 if (rd == ARM_PC) { \
259 ARM_WRITE_PC; \
260 }
261
262#define ARM_STORE_POST_BODY \
263 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
264
265#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
266 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
267 int currentCycles = ARM_PREFETCH_CYCLES; \
268 BODY; \
269 cpu->cycles += currentCycles; \
270 }
271
272#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
273 DEFINE_INSTRUCTION_ARM(NAME, \
274 int rd = (opcode >> 12) & 0xF; \
275 int rn = (opcode >> 16) & 0xF; \
276 UNUSED(rn); \
277 SHIFTER(cpu, opcode); \
278 BODY; \
279 S_BODY; \
280 if (rd == ARM_PC) { \
281 if (cpu->executionMode == MODE_ARM) { \
282 ARM_WRITE_PC; \
283 } else { \
284 THUMB_WRITE_PC; \
285 } \
286 })
287
288#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
289 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
290 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
291 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
292 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
295 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
296 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
297 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
298 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
307
308#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
310 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
318
319#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
320 DEFINE_INSTRUCTION_ARM(NAME, \
321 int rd = (opcode >> 12) & 0xF; \
322 int rdHi = (opcode >> 16) & 0xF; \
323 int rs = (opcode >> 8) & 0xF; \
324 int rm = opcode & 0xF; \
325 UNUSED(rdHi); \
326 ARM_WAIT_MUL(cpu->gprs[rs]); \
327 BODY; \
328 S_BODY; \
329 if (rd == ARM_PC) { \
330 ARM_WRITE_PC; \
331 })
332
333#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
334 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
335 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
336
337#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
338 DEFINE_INSTRUCTION_ARM(NAME, \
339 uint32_t address; \
340 int rn = (opcode >> 16) & 0xF; \
341 int rd = (opcode >> 12) & 0xF; \
342 int rm = opcode & 0xF; \
343 UNUSED(rm); \
344 address = ADDRESS; \
345 WRITEBACK; \
346 BODY;)
347
348#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
350 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
351 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
354 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
355
356#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
357 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
358 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
367
368#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
370 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
371 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
381
382#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
383 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
384 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
385
386#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
387 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
388 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
389 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
390 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
393
394#define ARM_MS_PRE \
395 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
396 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
397
398#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
399
400#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
401 DEFINE_INSTRUCTION_ARM(NAME, \
402 int rn = (opcode >> 16) & 0xF; \
403 int rs = opcode & 0x0000FFFF; \
404 uint32_t address = cpu->gprs[rn]; \
405 S_PRE; \
406 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
407 S_POST; \
408 POST_BODY; \
409 WRITEBACK;)
410
411
412#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
413 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
414 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
415 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
416 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
417 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
418 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
419 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
420 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
421 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
422 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
423 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
424 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
425 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
426 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
427 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
428 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
429
430// Begin ALU definitions
431
432DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
433 int32_t n = cpu->gprs[rn];
434 cpu->gprs[rd] = n + cpu->shifterOperand;)
435
436DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
437 int32_t n = cpu->gprs[rn];
438 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
439
440DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
441 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
442
443DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
444 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
445
446DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
447 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
448
449DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
450 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
451
452DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
453 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
454
455DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
456 cpu->gprs[rd] = cpu->shifterOperand;)
457
458DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
459 cpu->gprs[rd] = ~cpu->shifterOperand;)
460
461DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
462 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
463
464DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
465 int32_t n = cpu->gprs[rn];
466 cpu->gprs[rd] = cpu->shifterOperand - n;)
467
468DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
469 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
470 cpu->gprs[rd] = cpu->shifterOperand - n;)
471
472DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
473 int32_t n = cpu->gprs[rn];
474 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
475 cpu->gprs[rd] = n - shifterOperand;)
476
477DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
478 int32_t n = cpu->gprs[rn];
479 cpu->gprs[rd] = n - cpu->shifterOperand;)
480
481DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
482 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
483
484DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
485 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
486
487// End ALU definitions
488
489// Begin multiply definitions
490
491DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
492DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
493
494DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
495 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
496 int32_t dm = cpu->gprs[rd];
497 int32_t dn = d;
498 cpu->gprs[rd] = dm + dn;
499 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
500 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
501
502DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
503 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
504 cpu->gprs[rd] = d;
505 cpu->gprs[rdHi] = d >> 32;,
506 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
507
508DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
509 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
510 int32_t dm = cpu->gprs[rd];
511 int32_t dn = d;
512 cpu->gprs[rd] = dm + dn;
513 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
514 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
515
516DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
517 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
518 cpu->gprs[rd] = d;
519 cpu->gprs[rdHi] = d >> 32;,
520 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
521
522// End multiply definitions
523
524// Begin load/store definitions
525
526DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
527DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
528DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
529DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
530DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
531DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
532DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
533DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
534
535DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
536 enum PrivilegeMode priv = cpu->privilegeMode;
537 ARMSetPrivilegeMode(cpu, MODE_USER);
538 cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles);
539 ARMSetPrivilegeMode(cpu, priv);
540 ARM_LOAD_POST_BODY;)
541
542DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
543 enum PrivilegeMode priv = cpu->privilegeMode;
544 ARMSetPrivilegeMode(cpu, MODE_USER);
545 cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles);
546 ARMSetPrivilegeMode(cpu, priv);
547 ARM_LOAD_POST_BODY;)
548
549DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
550 enum PrivilegeMode priv = cpu->privilegeMode;
551 ARMSetPrivilegeMode(cpu, MODE_USER);
552 cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles);
553 ARMSetPrivilegeMode(cpu, priv);
554 ARM_STORE_POST_BODY;)
555
556DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
557 enum PrivilegeMode priv = cpu->privilegeMode;
558 ARMSetPrivilegeMode(cpu, MODE_USER);
559 cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles);
560 ARMSetPrivilegeMode(cpu, priv);
561 ARM_STORE_POST_BODY;)
562
563DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
564 load,
565 ++currentCycles;
566 if (rs & 0x8000) {
567 ARM_WRITE_PC;
568 })
569
570DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
571 store,
572 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
573
574DEFINE_INSTRUCTION_ARM(SWP,
575 int rm = opcode & 0xF;
576 int rd = (opcode >> 12) & 0xF;
577 int rn = (opcode >> 16) & 0xF;
578 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
579 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
580 cpu->gprs[rd] = d;)
581
582DEFINE_INSTRUCTION_ARM(SWPB,
583 int rm = opcode & 0xF;
584 int rd = (opcode >> 12) & 0xF;
585 int rn = (opcode >> 16) & 0xF;
586 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
587 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
588 cpu->gprs[rd] = d;)
589
590// End load/store definitions
591
592// Begin branch definitions
593
594DEFINE_INSTRUCTION_ARM(B,
595 int32_t offset = opcode << 8;
596 offset >>= 6;
597 cpu->gprs[ARM_PC] += offset;
598 ARM_WRITE_PC;)
599
600DEFINE_INSTRUCTION_ARM(BL,
601 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
602 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
603 cpu->gprs[ARM_PC] += immediate >> 6;
604 ARM_WRITE_PC;)
605
606DEFINE_INSTRUCTION_ARM(BX,
607 int rm = opcode & 0x0000000F;
608 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
609 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
610 if (cpu->executionMode == MODE_THUMB) {
611 THUMB_WRITE_PC;
612 } else {
613 ARM_WRITE_PC;
614 })
615
616// End branch definitions
617
618// Begin coprocessor definitions
619
620DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
621DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
622DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
623DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
624DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
625
626// Begin miscellaneous definitions
627
628DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
629DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
630
631DEFINE_INSTRUCTION_ARM(MSR,
632 int c = opcode & 0x00010000;
633 int f = opcode & 0x00080000;
634 int32_t operand = cpu->gprs[opcode & 0x0000000F];
635 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
636 if (mask & PSR_USER_MASK) {
637 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
638 }
639 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
640 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
641 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
642 }
643 _ARMReadCPSR(cpu);)
644
645DEFINE_INSTRUCTION_ARM(MSRR,
646 int c = opcode & 0x00010000;
647 int f = opcode & 0x00080000;
648 int32_t operand = cpu->gprs[opcode & 0x0000000F];
649 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
650 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
651 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
652
653DEFINE_INSTRUCTION_ARM(MRS, \
654 int rd = (opcode >> 12) & 0xF; \
655 cpu->gprs[rd] = cpu->cpsr.packed;)
656
657DEFINE_INSTRUCTION_ARM(MRSR, \
658 int rd = (opcode >> 12) & 0xF; \
659 cpu->gprs[rd] = cpu->spsr.packed;)
660
661DEFINE_INSTRUCTION_ARM(MSRI,
662 int c = opcode & 0x00010000;
663 int f = opcode & 0x00080000;
664 int rotate = (opcode & 0x00000F00) >> 7;
665 int32_t operand = ROR(opcode & 0x000000FF, rotate);
666 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
667 if (mask & PSR_USER_MASK) {
668 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
669 }
670 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
671 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
672 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
673 }
674 _ARMReadCPSR(cpu);)
675
676DEFINE_INSTRUCTION_ARM(MSRRI,
677 int c = opcode & 0x00010000;
678 int f = opcode & 0x00080000;
679 int rotate = (opcode & 0x00000F00) >> 7;
680 int32_t operand = ROR(opcode & 0x000000FF, rotate);
681 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
682 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
683 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
684
685DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
686
687const ARMInstruction _armTable[0x1000] = {
688 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
689};