1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ISA_INLINES_H
  7#define ISA_INLINES_H
  8
  9#include "macros.h"
 10
 11#include "arm.h"
 12
 13#define ARM_COND_EQ (cpu->cpsr.z)
 14#define ARM_COND_NE (!cpu->cpsr.z)
 15#define ARM_COND_CS (cpu->cpsr.c)
 16#define ARM_COND_CC (!cpu->cpsr.c)
 17#define ARM_COND_MI (cpu->cpsr.n)
 18#define ARM_COND_PL (!cpu->cpsr.n)
 19#define ARM_COND_VS (cpu->cpsr.v)
 20#define ARM_COND_VC (!cpu->cpsr.v)
 21#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
 22#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
 23#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
 24#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
 25#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
 26#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
 27#define ARM_COND_AL 1
 28
 29#define ARM_SIGN(I) ((I) >> 31)
 30#define ARM_SXT_8(I) (((int8_t) (I) << 24) >> 24)
 31#define ARM_SXT_16(I) (((int16_t) (I) << 16) >> 16)
 32#define ARM_UXT_64(I) (uint64_t)(uint32_t) (I)
 33
 34#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
 35#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
 36#define ARM_BORROW_FROM_CARRY(M, N, D, C) (ARM_UXT_64(M) >= (ARM_UXT_64(N)) + (uint64_t) (C))
 37#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
 38#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
 39
 40#define ARM_WAIT_MUL(R, WAIT)                                             \
 41	{                                                                     \
 42		int32_t wait = WAIT;                                              \
 43		if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) {        \
 44			wait += 1;                                                    \
 45		} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
 46			wait += 2;                                                    \
 47		} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
 48			wait += 3;                                                    \
 49		} else {                                                          \
 50			wait += 4;                                                    \
 51		}                                                                 \
 52		currentCycles += cpu->memory.stall(cpu, wait);                    \
 53	}
 54
 55#define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
 56#define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
 57
 58static inline int32_t ARMWritePC(struct ARMCore* cpu) {
 59	uint32_t pc = cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB;
 60	cpu->memory.setActiveRegion(cpu, pc);
 61	LOAD_32(cpu->prefetch[0], pc & cpu->memory.activeMask, cpu->memory.activeRegion);
 62	pc += WORD_SIZE_ARM;
 63	LOAD_32(cpu->prefetch[1], pc & cpu->memory.activeMask, cpu->memory.activeRegion);
 64	cpu->gprs[ARM_PC] = pc;
 65	return 2 + cpu->memory.activeNonseqCycles32 + cpu->memory.activeSeqCycles32;
 66}
 67
 68static inline int32_t ThumbWritePC(struct ARMCore* cpu) {
 69	uint32_t pc = cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB;
 70	cpu->memory.setActiveRegion(cpu, pc);
 71	LOAD_16(cpu->prefetch[0], pc & cpu->memory.activeMask, cpu->memory.activeRegion);
 72	pc += WORD_SIZE_THUMB;
 73	LOAD_16(cpu->prefetch[1], pc & cpu->memory.activeMask, cpu->memory.activeRegion);
 74	cpu->gprs[ARM_PC] = pc;
 75	return 2 + cpu->memory.activeNonseqCycles16 + cpu->memory.activeSeqCycles16;
 76}
 77
 78static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
 79	return mode != MODE_SYSTEM && mode != MODE_USER;
 80}
 81
 82static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
 83	if (executionMode == cpu->executionMode) {
 84		return;
 85	}
 86
 87	cpu->executionMode = executionMode;
 88	switch (executionMode) {
 89	case MODE_ARM:
 90		cpu->cpsr.t = 0;
 91		cpu->memory.activeMask &= ~2;
 92		break;
 93	case MODE_THUMB:
 94		cpu->cpsr.t = 1;
 95		cpu->memory.activeMask |= 2;
 96	}
 97	cpu->nextEvent = cpu->cycles;
 98}
 99
100static inline void _ARMReadCPSR(struct ARMCore* cpu) {
101	_ARMSetMode(cpu, cpu->cpsr.t);
102	ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
103	cpu->irqh.readCPSR(cpu);
104}
105
106static inline uint32_t _ARMInstructionLength(struct ARMCore* cpu) {
107	return cpu->cpsr.t == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB;
108}
109
110static inline uint32_t _ARMPCAddress(struct ARMCore* cpu) {
111	return cpu->gprs[ARM_PC] - _ARMInstructionLength(cpu) * 2;
112}
113
114static inline bool ARMTestCondition(struct ARMCore* cpu, unsigned condition) {
115	switch (condition) {
116		case 0x0:
117			return ARM_COND_EQ;
118		case 0x1:
119			return ARM_COND_NE;
120		case 0x2:
121			return ARM_COND_CS;
122		case 0x3:
123			return ARM_COND_CC;
124		case 0x4:
125			return ARM_COND_MI;
126		case 0x5:
127			return ARM_COND_PL;
128		case 0x6:
129			return ARM_COND_VS;
130		case 0x7:
131			return ARM_COND_VC;
132		case 0x8:
133			return ARM_COND_HI;
134		case 0x9:
135			return ARM_COND_LS;
136		case 0xA:
137			return ARM_COND_GE;
138		case 0xB:
139			return ARM_COND_LT;
140		case 0xC:
141			return ARM_COND_GT;
142		case 0xD:
143			return ARM_COND_LE;
144		default:
145			return true;
146	}
147}
148
149static inline enum RegisterBank ARMSelectBank(enum PrivilegeMode mode) {
150	switch (mode) {
151	case MODE_USER:
152	case MODE_SYSTEM:
153		// No banked registers
154		return BANK_NONE;
155	case MODE_FIQ:
156		return BANK_FIQ;
157	case MODE_IRQ:
158		return BANK_IRQ;
159	case MODE_SUPERVISOR:
160		return BANK_SUPERVISOR;
161	case MODE_ABORT:
162		return BANK_ABORT;
163	case MODE_UNDEFINED:
164		return BANK_UNDEFINED;
165	default:
166		// This should be unreached
167		return BANK_NONE;
168	}
169}
170
171#endif