src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
14 int rm = opcode & 0x0000000F;
15 int immediate = (opcode & 0x00000F80) >> 7;
16 if (!immediate) {
17 cpu->shifterOperand = cpu->gprs[rm];
18 cpu->shifterCarryOut = cpu->cpsr.c;
19 } else {
20 cpu->shifterOperand = cpu->gprs[rm] << immediate;
21 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (32 - immediate));
22 }
23}
24
25static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
26 int rm = opcode & 0x0000000F;
27 ARM_STUB;
28}
29
30static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
31 int rm = opcode & 0x0000000F;
32 int immediate = (opcode & 0x00000F80) >> 7;
33 if (immediate) {
34 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
35 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
36 } else {
37 cpu->shifterOperand = 0;
38 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
39 }
40}
41
42static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
43 int rm = opcode & 0x0000000F;
44 ARM_STUB;
45}
46
47static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
48 int rm = opcode & 0x0000000F;
49 int immediate = (opcode & 0x00000F80) >> 7;
50 if (immediate) {
51 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
52 cpu->shifterCarryOut = cpu->gprs[rm] & (1 << (immediate - 1));
53 } else {
54 cpu->shifterCarryOut = cpu->gprs[rm] & 0x80000000;
55 cpu->shifterOperand = cpu->shifterCarryOut >> 31; // Ensure sign extension
56 }
57}
58
59static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
60 int rm = opcode & 0x0000000F;
61 ARM_STUB;
62}
63
64static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
65 int rm = opcode & 0x0000000F;
66 int immediate = (opcode & 0x00000F80) >> 7;
67 ARM_STUB;
68}
69
70static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
71 int rm = opcode & 0x0000000F;
72 ARM_STUB;
73}
74
75static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
76 int rotate = (opcode & 0x00000F00) >> 7;
77 int immediate = opcode & 0x000000FF;
78 if (!rotate) {
79 cpu->shifterOperand = immediate;
80 cpu->shifterCarryOut = cpu->cpsr.c;
81 } else {
82 cpu->shifterOperand = ARM_ROR(immediate, rotate);
83 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
84 }
85}
86
87static const ARMInstruction _armTable[0x1000];
88
89static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
90 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
91 *opcodeOut = opcode;
92 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
93}
94
95void ARMStep(struct ARMCore* cpu) {
96 // TODO
97 uint32_t opcode;
98 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
99 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
100
101 int condition = opcode >> 28;
102 if (condition == 0xE) {
103 instruction(cpu, opcode);
104 return;
105 } else {
106 switch (condition) {
107 case 0x0:
108 if (!ARM_COND_EQ) {
109 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
110 return;
111 }
112 break;
113 case 0x1:
114 if (!ARM_COND_NE) {
115 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
116 return;
117 }
118 break;
119 case 0x2:
120 if (!ARM_COND_CS) {
121 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
122 return;
123 }
124 break;
125 case 0x3:
126 if (!ARM_COND_CC) {
127 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
128 return;
129 }
130 break;
131 case 0x4:
132 if (!ARM_COND_MI) {
133 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
134 return;
135 }
136 break;
137 case 0x5:
138 if (!ARM_COND_PL) {
139 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
140 return;
141 }
142 break;
143 case 0x6:
144 if (!ARM_COND_VS) {
145 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
146 return;
147 }
148 break;
149 case 0x7:
150 if (!ARM_COND_VC) {
151 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
152 return;
153 }
154 break;
155 case 0x8:
156 if (!ARM_COND_HI) {
157 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
158 return;
159 }
160 break;
161 case 0x9:
162 if (!ARM_COND_LS) {
163 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
164 return;
165 }
166 break;
167 case 0xA:
168 if (!ARM_COND_GE) {
169 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
170 return;
171 }
172 break;
173 case 0xB:
174 if (!ARM_COND_LT) {
175 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
176 return;
177 }
178 break;
179 case 0xC:
180 if (!ARM_COND_GT) {
181 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
182 return;
183 }
184 break;
185 case 0xD:
186 if (!ARM_COND_GE) {
187 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
188 return;
189 }
190 break;
191 default:
192 break;
193 }
194 }
195 instruction(cpu, opcode);
196}
197
198// Instruction definitions
199// Beware pre-processor antics
200
201#define ARM_ADDITION_S(M, N, D) \
202 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
203 cpu->cpsr = cpu->spsr; \
204 _ARMReadCPSR(cpu); \
205 } else { \
206 cpu->cpsr.n = ARM_SIGN(D); \
207 cpu->cpsr.z = !(D); \
208 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
209 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
210 }
211
212#define ARM_SUBTRACTION_S(M, N, D) \
213 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
214 cpu->cpsr = cpu->spsr; \
215 _ARMReadCPSR(cpu); \
216 } else { \
217 cpu->cpsr.n = ARM_SIGN(D); \
218 cpu->cpsr.z = !(D); \
219 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
220 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
221 }
222
223#define ARM_NEUTRAL_S(M, N, D) \
224 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
225 cpu->cpsr = cpu->spsr; \
226 _ARMReadCPSR(cpu); \
227 } else { \
228 cpu->cpsr.n = ARM_SIGN(D); \
229 cpu->cpsr.z = !(D); \
230 cpu->cpsr.c = cpu->shifterCarryOut; \
231 }
232
233#define ADDR_MODE_2_ADDRESS (address)
234#define ADDR_MODE_2_RN (cpu->gprs[rn])
235#define ADDR_MODE_2_RM (cpu->gprs[rm])
236#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
237#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
238#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
239#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
240#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
241#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
242#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
243
244#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
245#define ADDR_MODE_3_RN ADDR_MODE_2_RN
246#define ADDR_MODE_3_RM ADDR_MODE_2_RM
247#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
248#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
249#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
250
251#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
252 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
253 BODY; \
254 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32; \
255 }
256
257#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
258 DEFINE_INSTRUCTION_ARM(NAME, \
259 int rd = (opcode >> 12) & 0xF; \
260 int rn = (opcode >> 16) & 0xF; \
261 UNUSED(rn); \
262 SHIFTER(cpu, opcode); \
263 BODY; \
264 S_BODY; \
265 POST_BODY; \
266 if (rd == ARM_PC) { \
267 ARM_WRITE_PC; \
268 })
269
270#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
271 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY, POST_BODY) \
272 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
273 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY, POST_BODY) \
274 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
275 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY, POST_BODY) \
276 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
277 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY, POST_BODY) \
278 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
279 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY, POST_BODY) \
280 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
281 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY, POST_BODY) \
282 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
283 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY, POST_BODY) \
284 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
285 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY, POST_BODY) \
286 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
287 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
288 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
289
290#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY, POST_BODY) \
291 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY, POST_BODY) \
292 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY, POST_BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY, POST_BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY, POST_BODY) \
295 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY, POST_BODY) \
296 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY, POST_BODY) \
297 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY, POST_BODY) \
298 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY, POST_BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY, POST_BODY)
300
301#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
302 DEFINE_INSTRUCTION_ARM(NAME, \
303 uint32_t address; \
304 int rn = (opcode >> 16) & 0xF; \
305 int rd = (opcode >> 12) & 0xF; \
306 int rm = opcode & 0xF; \
307 UNUSED(rm); \
308 address = ADDRESS; \
309 BODY; \
310 WRITEBACK;)
311
312#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
313 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
314 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
315 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
316 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
317 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
318 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
319
320#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
321 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
322 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
323 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
324 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
325 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
326 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
327 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
328 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
329 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
330 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
331
332#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
333 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
334 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
335 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
336 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
337 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
338 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
339 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
340 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
341 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
342 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
343 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
344 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
345
346#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
347 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
349
350#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
351 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
352 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
353 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
354 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
355 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
356 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
357
358// TODO
359#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
360 DEFINE_INSTRUCTION_ARM(NAME, BODY;)
361
362#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
363 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
364 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DAW, , , BODY) \
365 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , , BODY) \
366 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DBW, , , BODY) \
367 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , , BODY) \
368 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IAW, , , BODY) \
369 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , , BODY) \
370 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IBW, , , BODY) \
371 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, S_PRE, S_POST, BODY) \
372 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DAW, S_PRE, S_POST, BODY) \
373 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, S_PRE, S_POST, BODY) \
374 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DBW, S_PRE, S_POST, BODY) \
375 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, S_PRE, S_POST, BODY) \
376 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IAW, S_PRE, S_POST, BODY) \
377 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, S_PRE, S_POST, BODY) \
378 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IBW, S_PRE, S_POST, BODY)
379
380// Begin ALU definitions
381
382DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
383 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
384
385DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
386 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
387 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
388
389DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
390 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
391
392DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
393 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
394
395DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
396 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
397
398DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
399 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
400
401DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
402 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
403
404DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
405 cpu->gprs[rd] = cpu->shifterOperand;, )
406
407DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
408 cpu->gprs[rd] = ~cpu->shifterOperand;, )
409
410DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
411 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
412
413DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d),
414 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
415
416DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d),
417 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
418 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
419
420DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d),
421 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
422 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
423
424DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d),
425 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
426
427DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
428 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
429
430DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
431 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
432
433// End ALU definitions
434
435// Begin multiply definitions
436
437DEFINE_INSTRUCTION_ARM(MLA, ARM_STUB)
438DEFINE_INSTRUCTION_ARM(MLAS, ARM_STUB)
439DEFINE_INSTRUCTION_ARM(MUL, ARM_STUB)
440DEFINE_INSTRUCTION_ARM(MULS, ARM_STUB)
441DEFINE_INSTRUCTION_ARM(SMLAL, ARM_STUB)
442DEFINE_INSTRUCTION_ARM(SMLALS, ARM_STUB)
443DEFINE_INSTRUCTION_ARM(SMULL, ARM_STUB)
444DEFINE_INSTRUCTION_ARM(SMULLS, ARM_STUB)
445DEFINE_INSTRUCTION_ARM(UMLAL, ARM_STUB)
446DEFINE_INSTRUCTION_ARM(UMLALS, ARM_STUB)
447DEFINE_INSTRUCTION_ARM(UMULL, ARM_STUB)
448DEFINE_INSTRUCTION_ARM(UMULLS, ARM_STUB)
449
450// End multiply definitions
451
452// Begin load/store definitions
453
454DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
455DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
456DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
457DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
458DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
459DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
460DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
461DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
462
463DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
464 enum PrivilegeMode priv = cpu->privilegeMode;
465 ARMSetPrivilegeMode(cpu, MODE_USER);
466 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address);
467 ARMSetPrivilegeMode(cpu, priv);)
468
469DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
470 enum PrivilegeMode priv = cpu->privilegeMode;
471 ARMSetPrivilegeMode(cpu, MODE_USER);
472 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address);
473 ARMSetPrivilegeMode(cpu, priv);)
474
475DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
476 enum PrivilegeMode priv = cpu->privilegeMode;
477 ARMSetPrivilegeMode(cpu, MODE_USER);
478 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]);
479 ARMSetPrivilegeMode(cpu, priv);)
480
481DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
482 enum PrivilegeMode priv = cpu->privilegeMode;
483 ARMSetPrivilegeMode(cpu, MODE_USER);
484 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]);
485 ARMSetPrivilegeMode(cpu, priv);)
486
487DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM, ARM_STUB)
488DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, ARM_STUB)
489
490DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
491DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
492
493// End load/store definitions
494
495// Begin branch definitions
496
497DEFINE_INSTRUCTION_ARM(B,
498 int32_t offset = opcode << 8;
499 offset >>= 6;
500 cpu->gprs[ARM_PC] += offset;
501 ARM_WRITE_PC;)
502
503DEFINE_INSTRUCTION_ARM(BL, ARM_STUB)
504DEFINE_INSTRUCTION_ARM(BX,
505 int rm = opcode & 0x0000000F;
506 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
507 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
508 if (cpu->executionMode == MODE_THUMB) {
509 THUMB_WRITE_PC;
510 } else {
511 ARM_WRITE_PC;
512 })
513
514// End branch definitions
515
516// Begin miscellaneous definitions
517
518DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
519DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
520
521DEFINE_INSTRUCTION_ARM(MSR,
522 int c = opcode & 0x00010000;
523 int f = opcode & 0x00080000;
524 int32_t operand;
525 if (opcode & 0x02000000) {
526 int rotate = (opcode & 0x00000F00) >> 8;
527 operand = ARM_ROR(opcode & 0x000000FF, rotate);
528 } else {
529 operand = cpu->gprs[opcode & 0x0000000F];
530 }
531 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
532 if (opcode & 0x00400000) {
533 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
534 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);
535 } else {
536 if (mask & PSR_USER_MASK) {
537 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
538 }
539 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
540 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
541 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
542 }
543 })
544
545DEFINE_INSTRUCTION_ARM(MRS, ARM_STUB)
546DEFINE_INSTRUCTION_ARM(MSRI, ARM_STUB)
547DEFINE_INSTRUCTION_ARM(MRSI, ARM_STUB)
548DEFINE_INSTRUCTION_ARM(SWI, ARM_STUB)
549
550#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
551 EMITTER ## NAME
552
553#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
554 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
555 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
556
557#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
558 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
559 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
560 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
561 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
562 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
563 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
564 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
565 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
566 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
567 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
568 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
569 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
570 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
571 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
572 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
573 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
574
575#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
576 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
577 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
578
579#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
580 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
581 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
582 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
583 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
584 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
585 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
586 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
587 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
588 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
589 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
590 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
591 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
592 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
593 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
594 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
595 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
596
597#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
598 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
599 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
600
601#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
602 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
603
604// TODO: Support coprocessors
605#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
606 DO_8(0), \
607 DO_8(0)
608
609#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
610 DO_8(DO_8(DO_INTERLACE(0, 0))), \
611 DO_8(DO_8(DO_INTERLACE(0, 0)))
612
613#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
614 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
615
616#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
617 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
618 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
619 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
620 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
621 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
622 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
623 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
624 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
625 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
626 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
627 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
628 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
629 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
630 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
631 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
632 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
633 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
634 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
635 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
636 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
637 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
638 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
639 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
640 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
641 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
642 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
643 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
644 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
645 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
646 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
647 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
648 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
649 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
650 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
651 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
652 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
653 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
654 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
655 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
656 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
657 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
658 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
659 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
660 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
661 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
662 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
663 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
664 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
665 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
666 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
667 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
668 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
669 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
670 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
671 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
672 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
673 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
674 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
675 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
676 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
677 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
678 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
679 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
680 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
681 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
682 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
683 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
684 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
685 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
686 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
687 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
688 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
689 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
690 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
691 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
692 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
693 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
694 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
695 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
696 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
697 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
698 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
699 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
700 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
701 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
702 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
703 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
704 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
705 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
706 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
707 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
708 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
709 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
710 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
711 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
712 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
713 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
714 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
715 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
716 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
717 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
718 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
719 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
720 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
721 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
722 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
723 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
724 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
725 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
726 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
727 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
728 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
729 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
730 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
731 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
732 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
733 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
734 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
735 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
736 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
737 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
738 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
739 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
740 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
741 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
742 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
743 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
744 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
745 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
746 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
747 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
748 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
749 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
750 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
751 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
752 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
753 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
754 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
755 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
756 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
757 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
758 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
759 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
760 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
761 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
762 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
763 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
764 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
765 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
766 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
767 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
768 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
769 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
770 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
771 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
772 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
773 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
774 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
775 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
776 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
777 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
778 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
779 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
780 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
781 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
782 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
783 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
784 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
785 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
786 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
787 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
788 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
789 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
790 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
791 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
792 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
793 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
794 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
795 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
796 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
797 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
798 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
799 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
800 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
801 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
802 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
803 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
804 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
805 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
806 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
807 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
808 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
809 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
810 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
811 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
812 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
813 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
814 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
815 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
816 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
817 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
818 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
819 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
820 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
821 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
822 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
823 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
824 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
825 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
826 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
827 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
828 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
829 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
830 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
831 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
832 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
833 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
834 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
835 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
836 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
837 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
838 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
839 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
840 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
841 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
842 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
843 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
844 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
845 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
846 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
847 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
848 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
849 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
850 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
851 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
852 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
853 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
854 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
855 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
856 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
857 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
858 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
859 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
860 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
861 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
862 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
863 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
864 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
865 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
866 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
867 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
868 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
869 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
870 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
871 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
872 DECLARE_ARM_SWI_BLOCK(EMITTER)
873
874static const ARMInstruction _armTable[0x1000] = {
875 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
876};