src/gba/bios.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gba/bios.h>
7
8#include <mgba/internal/arm/isa-inlines.h>
9#include <mgba/internal/arm/macros.h>
10#include <mgba/internal/gba/gba.h>
11#include <mgba/internal/gba/io.h>
12#include <mgba/internal/gba/memory.h>
13#include <mgba-util/math.h>
14
15const uint32_t GBA_BIOS_CHECKSUM = 0xBAAE187F;
16const uint32_t GBA_DS_BIOS_CHECKSUM = 0xBAAE1880;
17
18mLOG_DEFINE_CATEGORY(GBA_BIOS, "GBA BIOS", "gba.bios");
19
20static void _unLz77(struct GBA* gba, int width);
21static void _unHuffman(struct GBA* gba);
22static void _unRl(struct GBA* gba, int width);
23static void _unFilter(struct GBA* gba, int inwidth, int outwidth);
24static void _unBitPack(struct GBA* gba);
25
26static int _mulWait(int32_t r) {
27 if ((r & 0xFFFFFF00) == 0xFFFFFF00 || !(r & 0xFFFFFF00)) {
28 return 1;
29 } else if ((r & 0xFFFF0000) == 0xFFFF0000 || !(r & 0xFFFF0000)) {
30 return 2;
31 } else if ((r & 0xFF000000) == 0xFF000000 || !(r & 0xFF000000)) {
32 return 3;
33 } else {
34 return 4;
35 }
36}
37
38static void _SoftReset(struct GBA* gba) {
39 struct ARMCore* cpu = gba->cpu;
40 ARMSetPrivilegeMode(cpu, MODE_IRQ);
41 cpu->spsr.packed = 0;
42 cpu->gprs[ARM_LR] = 0;
43 cpu->gprs[ARM_SP] = SP_BASE_IRQ;
44 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
45 cpu->spsr.packed = 0;
46 cpu->gprs[ARM_LR] = 0;
47 cpu->gprs[ARM_SP] = SP_BASE_SUPERVISOR;
48 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
49 cpu->gprs[ARM_LR] = 0;
50 cpu->gprs[ARM_SP] = SP_BASE_SYSTEM;
51 int8_t flag = ((int8_t*) gba->memory.iwram)[0x7FFA];
52 memset(((int8_t*) gba->memory.iwram) + SIZE_WORKING_IRAM - 0x200, 0, 0x200);
53 if (flag) {
54 cpu->gprs[ARM_PC] = BASE_WORKING_RAM;
55 } else {
56 cpu->gprs[ARM_PC] = BASE_CART0;
57 }
58 _ARMSetMode(cpu, MODE_ARM);
59 ARMWritePC(cpu);
60}
61
62static void _RegisterRamReset(struct GBA* gba) {
63 uint32_t registers = gba->cpu->gprs[0];
64 struct ARMCore* cpu = gba->cpu;
65 cpu->memory.store16(cpu, BASE_IO | REG_DISPCNT, 0x0080, 0);
66 if (registers & 0x01) {
67 memset(gba->memory.wram, 0, SIZE_WORKING_RAM);
68 }
69 if (registers & 0x02) {
70 memset(gba->memory.iwram, 0, SIZE_WORKING_IRAM - 0x200);
71 }
72 if (registers & 0x04) {
73 memset(gba->video.palette, 0, SIZE_PALETTE_RAM);
74 }
75 if (registers & 0x08) {
76 memset(gba->video.vram, 0, SIZE_VRAM);
77 }
78 if (registers & 0x10) {
79 memset(gba->video.oam.raw, 0, SIZE_OAM);
80 }
81 if (registers & 0x20) {
82 cpu->memory.store16(cpu, BASE_IO | REG_SIOCNT, 0x0000, 0);
83 cpu->memory.store16(cpu, BASE_IO | REG_RCNT, RCNT_INITIAL, 0);
84 cpu->memory.store16(cpu, BASE_IO | REG_SIOMLT_SEND, 0, 0);
85 cpu->memory.store16(cpu, BASE_IO | REG_JOYCNT, 0, 0);
86 cpu->memory.store32(cpu, BASE_IO | REG_JOY_RECV_LO, 0, 0);
87 cpu->memory.store32(cpu, BASE_IO | REG_JOY_TRANS_LO, 0, 0);
88 }
89 if (registers & 0x40) {
90 cpu->memory.store16(cpu, BASE_IO | REG_SOUND1CNT_LO, 0, 0);
91 cpu->memory.store16(cpu, BASE_IO | REG_SOUND1CNT_HI, 0, 0);
92 cpu->memory.store16(cpu, BASE_IO | REG_SOUND1CNT_X, 0, 0);
93 cpu->memory.store16(cpu, BASE_IO | REG_SOUND2CNT_LO, 0, 0);
94 cpu->memory.store16(cpu, BASE_IO | REG_SOUND2CNT_HI, 0, 0);
95 cpu->memory.store16(cpu, BASE_IO | REG_SOUND3CNT_LO, 0, 0);
96 cpu->memory.store16(cpu, BASE_IO | REG_SOUND3CNT_HI, 0, 0);
97 cpu->memory.store16(cpu, BASE_IO | REG_SOUND3CNT_X, 0, 0);
98 cpu->memory.store16(cpu, BASE_IO | REG_SOUND4CNT_LO, 0, 0);
99 cpu->memory.store16(cpu, BASE_IO | REG_SOUND4CNT_HI, 0, 0);
100 cpu->memory.store16(cpu, BASE_IO | REG_SOUNDCNT_LO, 0, 0);
101 cpu->memory.store16(cpu, BASE_IO | REG_SOUNDCNT_HI, 0, 0);
102 cpu->memory.store16(cpu, BASE_IO | REG_SOUNDCNT_X, 0, 0);
103 cpu->memory.store16(cpu, BASE_IO | REG_SOUNDBIAS, 0x200, 0);
104 memset(gba->audio.psg.ch3.wavedata32, 0, sizeof(gba->audio.psg.ch3.wavedata32));
105 }
106 if (registers & 0x80) {
107 cpu->memory.store16(cpu, BASE_IO | REG_DISPSTAT, 0, 0);
108 cpu->memory.store16(cpu, BASE_IO | REG_VCOUNT, 0, 0);
109 cpu->memory.store16(cpu, BASE_IO | REG_BG0CNT, 0, 0);
110 cpu->memory.store16(cpu, BASE_IO | REG_BG1CNT, 0, 0);
111 cpu->memory.store16(cpu, BASE_IO | REG_BG2CNT, 0, 0);
112 cpu->memory.store16(cpu, BASE_IO | REG_BG3CNT, 0, 0);
113 cpu->memory.store16(cpu, BASE_IO | REG_BG0HOFS, 0, 0);
114 cpu->memory.store16(cpu, BASE_IO | REG_BG0VOFS, 0, 0);
115 cpu->memory.store16(cpu, BASE_IO | REG_BG1HOFS, 0, 0);
116 cpu->memory.store16(cpu, BASE_IO | REG_BG1VOFS, 0, 0);
117 cpu->memory.store16(cpu, BASE_IO | REG_BG2HOFS, 0, 0);
118 cpu->memory.store16(cpu, BASE_IO | REG_BG2VOFS, 0, 0);
119 cpu->memory.store16(cpu, BASE_IO | REG_BG3HOFS, 0, 0);
120 cpu->memory.store16(cpu, BASE_IO | REG_BG3VOFS, 0, 0);
121 cpu->memory.store16(cpu, BASE_IO | REG_BG2PA, 0x100, 0);
122 cpu->memory.store16(cpu, BASE_IO | REG_BG2PB, 0, 0);
123 cpu->memory.store16(cpu, BASE_IO | REG_BG2PC, 0, 0);
124 cpu->memory.store16(cpu, BASE_IO | REG_BG2PD, 0x100, 0);
125 cpu->memory.store32(cpu, BASE_IO | REG_BG2X_LO, 0, 0);
126 cpu->memory.store32(cpu, BASE_IO | REG_BG2Y_LO, 0, 0);
127 cpu->memory.store16(cpu, BASE_IO | REG_BG3PA, 0x100, 0);
128 cpu->memory.store16(cpu, BASE_IO | REG_BG3PB, 0, 0);
129 cpu->memory.store16(cpu, BASE_IO | REG_BG3PC, 0, 0);
130 cpu->memory.store16(cpu, BASE_IO | REG_BG3PD, 0x100, 0);
131 cpu->memory.store32(cpu, BASE_IO | REG_BG3X_LO, 0, 0);
132 cpu->memory.store32(cpu, BASE_IO | REG_BG3Y_LO, 0, 0);
133 cpu->memory.store16(cpu, BASE_IO | REG_WIN0H, 0, 0);
134 cpu->memory.store16(cpu, BASE_IO | REG_WIN1H, 0, 0);
135 cpu->memory.store16(cpu, BASE_IO | REG_WIN0V, 0, 0);
136 cpu->memory.store16(cpu, BASE_IO | REG_WIN1V, 0, 0);
137 cpu->memory.store16(cpu, BASE_IO | REG_WININ, 0, 0);
138 cpu->memory.store16(cpu, BASE_IO | REG_WINOUT, 0, 0);
139 cpu->memory.store16(cpu, BASE_IO | REG_MOSAIC, 0, 0);
140 cpu->memory.store16(cpu, BASE_IO | REG_BLDCNT, 0, 0);
141 cpu->memory.store16(cpu, BASE_IO | REG_BLDALPHA, 0, 0);
142 cpu->memory.store16(cpu, BASE_IO | REG_BLDY, 0, 0);
143 cpu->memory.store16(cpu, BASE_IO | REG_DMA0SAD_LO, 0, 0);
144 cpu->memory.store16(cpu, BASE_IO | REG_DMA0SAD_HI, 0, 0);
145 cpu->memory.store16(cpu, BASE_IO | REG_DMA0DAD_LO, 0, 0);
146 cpu->memory.store16(cpu, BASE_IO | REG_DMA0DAD_HI, 0, 0);
147 cpu->memory.store16(cpu, BASE_IO | REG_DMA0CNT_LO, 0, 0);
148 cpu->memory.store16(cpu, BASE_IO | REG_DMA0CNT_HI, 0, 0);
149 cpu->memory.store16(cpu, BASE_IO | REG_DMA1SAD_LO, 0, 0);
150 cpu->memory.store16(cpu, BASE_IO | REG_DMA1SAD_HI, 0, 0);
151 cpu->memory.store16(cpu, BASE_IO | REG_DMA1DAD_LO, 0, 0);
152 cpu->memory.store16(cpu, BASE_IO | REG_DMA1DAD_HI, 0, 0);
153 cpu->memory.store16(cpu, BASE_IO | REG_DMA1CNT_LO, 0, 0);
154 cpu->memory.store16(cpu, BASE_IO | REG_DMA1CNT_HI, 0, 0);
155 cpu->memory.store16(cpu, BASE_IO | REG_DMA2SAD_LO, 0, 0);
156 cpu->memory.store16(cpu, BASE_IO | REG_DMA2SAD_HI, 0, 0);
157 cpu->memory.store16(cpu, BASE_IO | REG_DMA2DAD_LO, 0, 0);
158 cpu->memory.store16(cpu, BASE_IO | REG_DMA2DAD_HI, 0, 0);
159 cpu->memory.store16(cpu, BASE_IO | REG_DMA2CNT_LO, 0, 0);
160 cpu->memory.store16(cpu, BASE_IO | REG_DMA2CNT_HI, 0, 0);
161 cpu->memory.store16(cpu, BASE_IO | REG_DMA3SAD_LO, 0, 0);
162 cpu->memory.store16(cpu, BASE_IO | REG_DMA3SAD_HI, 0, 0);
163 cpu->memory.store16(cpu, BASE_IO | REG_DMA3DAD_LO, 0, 0);
164 cpu->memory.store16(cpu, BASE_IO | REG_DMA3DAD_HI, 0, 0);
165 cpu->memory.store16(cpu, BASE_IO | REG_DMA3CNT_LO, 0, 0);
166 cpu->memory.store16(cpu, BASE_IO | REG_DMA3CNT_HI, 0, 0);
167 cpu->memory.store16(cpu, BASE_IO | REG_TM0CNT_LO, 0, 0);
168 cpu->memory.store16(cpu, BASE_IO | REG_TM0CNT_HI, 0, 0);
169 cpu->memory.store16(cpu, BASE_IO | REG_TM1CNT_LO, 0, 0);
170 cpu->memory.store16(cpu, BASE_IO | REG_TM1CNT_HI, 0, 0);
171 cpu->memory.store16(cpu, BASE_IO | REG_TM2CNT_LO, 0, 0);
172 cpu->memory.store16(cpu, BASE_IO | REG_TM2CNT_HI, 0, 0);
173 cpu->memory.store16(cpu, BASE_IO | REG_TM3CNT_LO, 0, 0);
174 cpu->memory.store16(cpu, BASE_IO | REG_TM3CNT_HI, 0, 0);
175 cpu->memory.store16(cpu, BASE_IO | REG_IE, 0, 0);
176 cpu->memory.store16(cpu, BASE_IO | REG_IF, 0xFFFF, 0);
177 cpu->memory.store16(cpu, BASE_IO | REG_WAITCNT, 0, 0);
178 cpu->memory.store16(cpu, BASE_IO | REG_IME, 0, 0);
179 }
180 if (registers & 0x9C) {
181 gba->video.renderer->reset(gba->video.renderer);
182 gba->video.renderer->writeVideoRegister(gba->video.renderer, REG_DISPCNT, gba->memory.io[REG_DISPCNT >> 1]);
183 int i;
184 for (i = REG_BG0CNT; i < REG_SOUND1CNT_LO; i += 2) {
185 gba->video.renderer->writeVideoRegister(gba->video.renderer, i, gba->memory.io[i >> 1]);
186 }
187 }
188}
189
190static void _BgAffineSet(struct GBA* gba) {
191 struct ARMCore* cpu = gba->cpu;
192 int i = cpu->gprs[2];
193 float ox, oy;
194 float cx, cy;
195 float sx, sy;
196 float theta;
197 int offset = cpu->gprs[0];
198 int destination = cpu->gprs[1];
199 float a, b, c, d;
200 float rx, ry;
201 while (i--) {
202 // [ sx 0 0 ] [ cos(theta) -sin(theta) 0 ] [ 1 0 cx - ox ] [ A B rx ]
203 // [ 0 sy 0 ] * [ sin(theta) cos(theta) 0 ] * [ 0 1 cy - oy ] = [ C D ry ]
204 // [ 0 0 1 ] [ 0 0 1 ] [ 0 0 1 ] [ 0 0 1 ]
205 ox = (int32_t) cpu->memory.load32(cpu, offset, 0) / 256.f;
206 oy = (int32_t) cpu->memory.load32(cpu, offset + 4, 0) / 256.f;
207 cx = (int16_t) cpu->memory.load16(cpu, offset + 8, 0);
208 cy = (int16_t) cpu->memory.load16(cpu, offset + 10, 0);
209 sx = (int16_t) cpu->memory.load16(cpu, offset + 12, 0) / 256.f;
210 sy = (int16_t) cpu->memory.load16(cpu, offset + 14, 0) / 256.f;
211 theta = (cpu->memory.load16(cpu, offset + 16, 0) >> 8) / 128.f * M_PI;
212 offset += 20;
213 // Rotation
214 a = d = cosf(theta);
215 b = c = sinf(theta);
216 // Scale
217 a *= sx;
218 b *= -sx;
219 c *= sy;
220 d *= sy;
221 // Translate
222 rx = ox - (a * cx + b * cy);
223 ry = oy - (c * cx + d * cy);
224 cpu->memory.store16(cpu, destination, a * 256, 0);
225 cpu->memory.store16(cpu, destination + 2, b * 256, 0);
226 cpu->memory.store16(cpu, destination + 4, c * 256, 0);
227 cpu->memory.store16(cpu, destination + 6, d * 256, 0);
228 cpu->memory.store32(cpu, destination + 8, rx * 256, 0);
229 cpu->memory.store32(cpu, destination + 12, ry * 256, 0);
230 destination += 16;
231 }
232}
233
234static void _ObjAffineSet(struct GBA* gba) {
235 struct ARMCore* cpu = gba->cpu;
236 int i = cpu->gprs[2];
237 float sx, sy;
238 float theta;
239 int offset = cpu->gprs[0];
240 int destination = cpu->gprs[1];
241 int diff = cpu->gprs[3];
242 float a, b, c, d;
243 while (i--) {
244 // [ sx 0 ] [ cos(theta) -sin(theta) ] [ A B ]
245 // [ 0 sy ] * [ sin(theta) cos(theta) ] = [ C D ]
246 sx = (int16_t) cpu->memory.load16(cpu, offset, 0) / 256.f;
247 sy = (int16_t) cpu->memory.load16(cpu, offset + 2, 0) / 256.f;
248 theta = (cpu->memory.load16(cpu, offset + 4, 0) >> 8) / 128.f * M_PI;
249 offset += 8;
250 // Rotation
251 a = d = cosf(theta);
252 b = c = sinf(theta);
253 // Scale
254 a *= sx;
255 b *= -sx;
256 c *= sy;
257 d *= sy;
258 cpu->memory.store16(cpu, destination, a * 256, 0);
259 cpu->memory.store16(cpu, destination + diff, b * 256, 0);
260 cpu->memory.store16(cpu, destination + diff * 2, c * 256, 0);
261 cpu->memory.store16(cpu, destination + diff * 3, d * 256, 0);
262 destination += diff * 4;
263 }
264}
265
266static void _MidiKey2Freq(struct GBA* gba) {
267 struct ARMCore* cpu = gba->cpu;
268
269 int oldRegion = gba->memory.activeRegion;
270 gba->memory.activeRegion = REGION_BIOS;
271 uint32_t key = cpu->memory.load32(cpu, cpu->gprs[0] + 4, 0);
272 gba->memory.activeRegion = oldRegion;
273
274 cpu->gprs[0] = key / exp2f((180.f - cpu->gprs[1] - cpu->gprs[2] / 256.f) / 12.f);
275}
276
277static void _Div(struct GBA* gba, int32_t num, int32_t denom) {
278 struct ARMCore* cpu = gba->cpu;
279 if (denom != 0 && (denom != -1 || num != INT32_MIN)) {
280 div_t result = div(num, denom);
281 cpu->gprs[0] = result.quot;
282 cpu->gprs[1] = result.rem;
283 cpu->gprs[3] = abs(result.quot);
284 } else if (denom == 0) {
285 mLOG(GBA_BIOS, GAME_ERROR, "Attempting to divide %i by zero!", num);
286 // If abs(num) > 1, this should hang, but that would be painful to
287 // emulate in HLE, and no game will get into a state where it hangs...
288 cpu->gprs[0] = (num < 0) ? -1 : 1;
289 cpu->gprs[1] = num;
290 cpu->gprs[3] = 1;
291 } else {
292 mLOG(GBA_BIOS, GAME_ERROR, "Attempting to divide INT_MIN by -1!");
293 cpu->gprs[0] = INT32_MIN;
294 cpu->gprs[1] = 0;
295 cpu->gprs[3] = INT32_MIN;
296 }
297 int loops = clz32(denom) - clz32(num);
298 if (loops < 1) {
299 loops = 1;
300 }
301 gba->biosStall = 4 /* prologue */ + 13 * loops + 7 /* epilogue */;
302}
303
304static int16_t _ArcTan(int32_t i, int32_t* r1, int32_t* r3, uint32_t* cycles) {
305 int currentCycles = 37;
306 currentCycles += _mulWait(i * i);
307 int32_t a = -((i * i) >> 14);
308 currentCycles += _mulWait(0xA9 * a);
309 int32_t b = ((0xA9 * a) >> 14) + 0x390;
310 currentCycles += _mulWait(b * a);
311 b = ((b * a) >> 14) + 0x91C;
312 currentCycles += _mulWait(b * a);
313 b = ((b * a) >> 14) + 0xFB6;
314 currentCycles += _mulWait(b * a);
315 b = ((b * a) >> 14) + 0x16AA;
316 currentCycles += _mulWait(b * a);
317 b = ((b * a) >> 14) + 0x2081;
318 currentCycles += _mulWait(b * a);
319 b = ((b * a) >> 14) + 0x3651;
320 currentCycles += _mulWait(b * a);
321 b = ((b * a) >> 14) + 0xA2F9;
322 if (r1) {
323 *r1 = a;
324 }
325 if (r3) {
326 *r3 = b;
327 }
328 *cycles = currentCycles;
329 return (i * b) >> 16;
330}
331
332static int16_t _ArcTan2(int32_t x, int32_t y, int32_t* r1, uint32_t* cycles) {
333 if (!y) {
334 if (x >= 0) {
335 return 0;
336 }
337 return 0x8000;
338 }
339 if (!x) {
340 if (y >= 0) {
341 return 0x4000;
342 }
343 return 0xC000;
344 }
345 if (y >= 0) {
346 if (x >= 0) {
347 if (x >= y) {
348 return _ArcTan((y << 14) / x, r1, NULL, cycles);
349 }
350 } else if (-x >= y) {
351 return _ArcTan((y << 14) / x, r1, NULL, cycles) + 0x8000;
352 }
353 return 0x4000 - _ArcTan((x << 14) / y, r1, NULL, cycles);
354 } else {
355 if (x <= 0) {
356 if (-x > -y) {
357 return _ArcTan((y << 14) / x, r1, NULL, cycles) + 0x8000;
358 }
359 } else if (x >= -y) {
360 return _ArcTan((y << 14) / x, r1, NULL, cycles) + 0x10000;
361 }
362 return 0xC000 - _ArcTan((x << 14) / y, r1, NULL, cycles);
363 }
364}
365
366static int32_t _Sqrt(uint32_t x, uint32_t* cycles) {
367 if (!x) {
368 *cycles = 53;
369 return 0;
370 }
371 int32_t currentCycles = 15;
372 uint32_t lower;
373 uint32_t upper = x;
374 uint32_t bound = 1;
375 while (bound < upper) {
376 upper >>= 1;
377 bound <<= 1;
378 currentCycles += 6;
379 }
380 while (true) {
381 currentCycles += 6;
382 upper = x;
383 uint32_t accum = 0;
384 lower = bound;
385 while (true) {
386 currentCycles += 5;
387 uint32_t oldLower = lower;
388 if (lower <= upper >> 1) {
389 lower <<= 1;
390 }
391 if (oldLower >= upper >> 1) {
392 break;
393 }
394 }
395 while (true) {
396 currentCycles += 8;
397 accum <<= 1;
398 if (upper >= lower) {
399 ++accum;
400 upper -= lower;
401 }
402 if (lower == bound) {
403 break;
404 }
405 lower >>= 1;
406 }
407 uint32_t oldBound = bound;
408 bound += accum;
409 bound >>= 1;
410 if (bound >= oldBound) {
411 bound = oldBound;
412 break;
413 }
414 }
415 *cycles = currentCycles;
416 return bound;
417}
418
419void GBASwi16(struct ARMCore* cpu, int immediate) {
420 struct GBA* gba = (struct GBA*) cpu->master;
421 mLOG(GBA_BIOS, DEBUG, "SWI: %02X r0: %08X r1: %08X r2: %08X r3: %08X",
422 immediate, cpu->gprs[0], cpu->gprs[1], cpu->gprs[2], cpu->gprs[3]);
423
424 switch (immediate) {
425 case 0xF0: // Used for internal stall counting
426 cpu->gprs[12] = gba->biosStall;
427 return;
428 case 0xFA:
429 GBAPrintFlush(gba);
430 return;
431 }
432
433 if (gba->memory.fullBios) {
434 ARMRaiseSWI(cpu);
435 return;
436 }
437
438 bool useStall = false;
439 switch (immediate) {
440 case GBA_SWI_SOFT_RESET:
441 _SoftReset(gba);
442 break;
443 case GBA_SWI_REGISTER_RAM_RESET:
444 _RegisterRamReset(gba);
445 break;
446 case GBA_SWI_HALT:
447 ARMRaiseSWI(cpu);
448 return;
449 case GBA_SWI_STOP:
450 GBAStop(gba);
451 break;
452 case GBA_SWI_VBLANK_INTR_WAIT:
453 // VBlankIntrWait
454 // Fall through:
455 case GBA_SWI_INTR_WAIT:
456 // IntrWait
457 ARMRaiseSWI(cpu);
458 return;
459 case GBA_SWI_DIV:
460 useStall = true;
461 _Div(gba, cpu->gprs[0], cpu->gprs[1]);
462 break;
463 case GBA_SWI_DIV_ARM:
464 useStall = true;
465 _Div(gba, cpu->gprs[1], cpu->gprs[0]);
466 break;
467 case GBA_SWI_SQRT:
468 useStall = true;
469 cpu->gprs[0] = _Sqrt(cpu->gprs[0], &gba->biosStall);
470 break;
471 case GBA_SWI_ARCTAN:
472 useStall = true;
473 cpu->gprs[0] = _ArcTan(cpu->gprs[0], &cpu->gprs[1], &cpu->gprs[3], &gba->biosStall);
474 break;
475 case GBA_SWI_ARCTAN2:
476 useStall = true;
477 cpu->gprs[0] = (uint16_t) _ArcTan2(cpu->gprs[0], cpu->gprs[1], &cpu->gprs[1], &gba->biosStall);
478 cpu->gprs[3] = 0x170;
479 break;
480 case GBA_SWI_CPU_SET:
481 case GBA_SWI_CPU_FAST_SET:
482 if (cpu->gprs[0] >> BASE_OFFSET < REGION_WORKING_RAM) {
483 mLOG(GBA_BIOS, GAME_ERROR, "Cannot CpuSet from BIOS");
484 break;
485 }
486 if (cpu->gprs[0] & (cpu->gprs[2] & (1 << 26) ? 3 : 1)) {
487 mLOG(GBA_BIOS, GAME_ERROR, "Misaligned CpuSet source");
488 }
489 if (cpu->gprs[1] & (cpu->gprs[2] & (1 << 26) ? 3 : 1)) {
490 mLOG(GBA_BIOS, GAME_ERROR, "Misaligned CpuSet destination");
491 }
492 ARMRaiseSWI(cpu);
493 return;
494 case GBA_SWI_GET_BIOS_CHECKSUM:
495 cpu->gprs[0] = GBA_BIOS_CHECKSUM;
496 cpu->gprs[1] = 1;
497 cpu->gprs[3] = SIZE_BIOS;
498 break;
499 case GBA_SWI_BG_AFFINE_SET:
500 _BgAffineSet(gba);
501 break;
502 case GBA_SWI_OBJ_AFFINE_SET:
503 _ObjAffineSet(gba);
504 break;
505 case GBA_SWI_BIT_UNPACK:
506 if (cpu->gprs[0] < BASE_WORKING_RAM) {
507 mLOG(GBA_BIOS, GAME_ERROR, "Bad BitUnPack source");
508 break;
509 }
510 switch (cpu->gprs[1] >> BASE_OFFSET) {
511 default:
512 mLOG(GBA_BIOS, GAME_ERROR, "Bad BitUnPack destination");
513 // Fall through
514 case REGION_WORKING_RAM:
515 case REGION_WORKING_IRAM:
516 case REGION_VRAM:
517 _unBitPack(gba);
518 break;
519 }
520 break;
521 case GBA_SWI_LZ77_UNCOMP_WRAM:
522 case GBA_SWI_LZ77_UNCOMP_VRAM:
523 if (cpu->gprs[0] < BASE_WORKING_RAM) {
524 mLOG(GBA_BIOS, GAME_ERROR, "Bad LZ77 source");
525 break;
526 }
527 switch (cpu->gprs[1] >> BASE_OFFSET) {
528 default:
529 mLOG(GBA_BIOS, GAME_ERROR, "Bad LZ77 destination");
530 // Fall through
531 case REGION_WORKING_RAM:
532 case REGION_WORKING_IRAM:
533 case REGION_VRAM:
534 _unLz77(gba, immediate == GBA_SWI_LZ77_UNCOMP_WRAM ? 1 : 2);
535 break;
536 }
537 break;
538 case GBA_SWI_HUFFMAN_UNCOMP:
539 if (cpu->gprs[0] < BASE_WORKING_RAM) {
540 mLOG(GBA_BIOS, GAME_ERROR, "Bad Huffman source");
541 break;
542 }
543 switch (cpu->gprs[1] >> BASE_OFFSET) {
544 default:
545 mLOG(GBA_BIOS, GAME_ERROR, "Bad Huffman destination");
546 // Fall through
547 case REGION_WORKING_RAM:
548 case REGION_WORKING_IRAM:
549 case REGION_VRAM:
550 _unHuffman(gba);
551 break;
552 }
553 break;
554 case GBA_SWI_RL_UNCOMP_WRAM:
555 case GBA_SWI_RL_UNCOMP_VRAM:
556 if (cpu->gprs[0] < BASE_WORKING_RAM) {
557 mLOG(GBA_BIOS, GAME_ERROR, "Bad RL source");
558 break;
559 }
560 switch (cpu->gprs[1] >> BASE_OFFSET) {
561 default:
562 mLOG(GBA_BIOS, GAME_ERROR, "Bad RL destination");
563 // Fall through
564 case REGION_WORKING_RAM:
565 case REGION_WORKING_IRAM:
566 case REGION_VRAM:
567 _unRl(gba, immediate == GBA_SWI_RL_UNCOMP_WRAM ? 1 : 2);
568 break;
569 }
570 break;
571 case GBA_SWI_DIFF_8BIT_UNFILTER_WRAM:
572 case GBA_SWI_DIFF_8BIT_UNFILTER_VRAM:
573 case GBA_SWI_DIFF_16BIT_UNFILTER:
574 if (cpu->gprs[0] < BASE_WORKING_RAM) {
575 mLOG(GBA_BIOS, GAME_ERROR, "Bad UnFilter source");
576 break;
577 }
578 switch (cpu->gprs[1] >> BASE_OFFSET) {
579 default:
580 mLOG(GBA_BIOS, GAME_ERROR, "Bad UnFilter destination");
581 // Fall through
582 case REGION_WORKING_RAM:
583 case REGION_WORKING_IRAM:
584 case REGION_VRAM:
585 _unFilter(gba, immediate == GBA_SWI_DIFF_16BIT_UNFILTER ? 2 : 1, immediate == GBA_SWI_DIFF_8BIT_UNFILTER_WRAM ? 1 : 2);
586 break;
587 }
588 break;
589 case GBA_SWI_SOUND_BIAS:
590 // SoundBias is mostly meaningless here
591 mLOG(GBA_BIOS, STUB, "Stub software interrupt: SoundBias (19)");
592 break;
593 case GBA_SWI_MIDI_KEY_2_FREQ:
594 _MidiKey2Freq(gba);
595 break;
596 case GBA_SWI_SOUND_DRIVER_GET_JUMP_LIST:
597 ARMRaiseSWI(cpu);
598 return;
599 default:
600 mLOG(GBA_BIOS, STUB, "Stub software interrupt: %02X", immediate);
601 }
602 if (useStall) {
603 if (gba->biosStall >= 18) {
604 gba->biosStall -= 18;
605 gba->cpu->cycles += gba->biosStall & 3;
606 gba->biosStall &= ~3;
607 ARMRaiseSWI(cpu);
608 } else {
609 gba->cpu->cycles += gba->biosStall;
610 useStall = false;
611 }
612 }
613 if (!useStall) {
614 gba->cpu->cycles += 45 + cpu->memory.activeNonseqCycles16 /* 8 bit load for SWI # */;
615 // Return cycles
616 if (gba->cpu->executionMode == MODE_ARM) {
617 gba->cpu->cycles += cpu->memory.activeNonseqCycles32 + cpu->memory.activeSeqCycles32;
618 } else {
619 gba->cpu->cycles += cpu->memory.activeNonseqCycles16 + cpu->memory.activeSeqCycles16;
620 }
621 }
622 gba->memory.biosPrefetch = 0xE3A02004;
623}
624
625void GBASwi32(struct ARMCore* cpu, int immediate) {
626 GBASwi16(cpu, immediate >> 16);
627}
628
629uint32_t GBAChecksum(uint32_t* memory, size_t size) {
630 size_t i;
631 uint32_t sum = 0;
632 for (i = 0; i < size; i += 4) {
633 sum += memory[i >> 2];
634 }
635 return sum;
636}
637
638static void _unLz77(struct GBA* gba, int width) {
639 struct ARMCore* cpu = gba->cpu;
640 uint32_t source = cpu->gprs[0];
641 uint32_t dest = cpu->gprs[1];
642 int remaining = (cpu->memory.load32(cpu, source, 0) & 0xFFFFFF00) >> 8;
643 // We assume the signature byte (0x10) is correct
644 int blockheader = 0; // Some compilers warn if this isn't set, even though it's trivially provably always set
645 source += 4;
646 int blocksRemaining = 0;
647 uint32_t disp;
648 int bytes;
649 int byte;
650 int halfword = 0;
651 while (remaining > 0) {
652 if (blocksRemaining) {
653 if (blockheader & 0x80) {
654 // Compressed
655 int block = cpu->memory.load8(cpu, source + 1, 0) | (cpu->memory.load8(cpu, source, 0) << 8);
656 source += 2;
657 disp = dest - (block & 0x0FFF) - 1;
658 bytes = (block >> 12) + 3;
659 while (bytes--) {
660 if (remaining) {
661 --remaining;
662 }
663 if (width == 2) {
664 byte = (int16_t) cpu->memory.load16(cpu, disp & ~1, 0);
665 if (dest & 1) {
666 byte >>= (disp & 1) * 8;
667 halfword |= byte << 8;
668 cpu->memory.store16(cpu, dest ^ 1, halfword, 0);
669 } else {
670 byte >>= (disp & 1) * 8;
671 halfword = byte & 0xFF;
672 }
673 } else {
674 byte = cpu->memory.load8(cpu, disp, 0);
675 cpu->memory.store8(cpu, dest, byte, 0);
676 }
677 ++disp;
678 ++dest;
679 }
680 } else {
681 // Uncompressed
682 byte = cpu->memory.load8(cpu, source, 0);
683 ++source;
684 if (width == 2) {
685 if (dest & 1) {
686 halfword |= byte << 8;
687 cpu->memory.store16(cpu, dest ^ 1, halfword, 0);
688 } else {
689 halfword = byte;
690 }
691 } else {
692 cpu->memory.store8(cpu, dest, byte, 0);
693 }
694 ++dest;
695 --remaining;
696 }
697 blockheader <<= 1;
698 --blocksRemaining;
699 } else {
700 blockheader = cpu->memory.load8(cpu, source, 0);
701 ++source;
702 blocksRemaining = 8;
703 }
704 }
705 cpu->gprs[0] = source;
706 cpu->gprs[1] = dest;
707 cpu->gprs[3] = 0;
708}
709
710DECL_BITFIELD(HuffmanNode, uint8_t);
711DECL_BITS(HuffmanNode, Offset, 0, 6);
712DECL_BIT(HuffmanNode, RTerm, 6);
713DECL_BIT(HuffmanNode, LTerm, 7);
714
715static void _unHuffman(struct GBA* gba) {
716 struct ARMCore* cpu = gba->cpu;
717 uint32_t source = cpu->gprs[0] & 0xFFFFFFFC;
718 uint32_t dest = cpu->gprs[1];
719 uint32_t header = cpu->memory.load32(cpu, source, 0);
720 int remaining = header >> 8;
721 unsigned bits = header & 0xF;
722 if (bits == 0) {
723 mLOG(GBA_BIOS, GAME_ERROR, "Invalid Huffman bits");
724 bits = 8;
725 }
726 if (32 % bits || bits == 1) {
727 mLOG(GBA_BIOS, STUB, "Unimplemented unaligned Huffman");
728 return;
729 }
730 // We assume the signature byte (0x20) is correct
731 int treesize = (cpu->memory.load8(cpu, source + 4, 0) << 1) + 1;
732 int block = 0;
733 uint32_t treeBase = source + 5;
734 source += 5 + treesize;
735 uint32_t nPointer = treeBase;
736 HuffmanNode node;
737 int bitsRemaining;
738 int readBits;
739 int bitsSeen = 0;
740 node = cpu->memory.load8(cpu, nPointer, 0);
741 while (remaining > 0) {
742 uint32_t bitstream = cpu->memory.load32(cpu, source, 0);
743 source += 4;
744 for (bitsRemaining = 32; bitsRemaining > 0 && remaining > 0; --bitsRemaining, bitstream <<= 1) {
745 uint32_t next = (nPointer & ~1) + HuffmanNodeGetOffset(node) * 2 + 2;
746 if (bitstream & 0x80000000) {
747 // Go right
748 if (HuffmanNodeIsRTerm(node)) {
749 readBits = cpu->memory.load8(cpu, next + 1, 0);
750 } else {
751 nPointer = next + 1;
752 node = cpu->memory.load8(cpu, nPointer, 0);
753 continue;
754 }
755 } else {
756 // Go left
757 if (HuffmanNodeIsLTerm(node)) {
758 readBits = cpu->memory.load8(cpu, next, 0);
759 } else {
760 nPointer = next;
761 node = cpu->memory.load8(cpu, nPointer, 0);
762 continue;
763 }
764 }
765
766 block |= (readBits & ((1 << bits) - 1)) << bitsSeen;
767 bitsSeen += bits;
768 nPointer = treeBase;
769 node = cpu->memory.load8(cpu, nPointer, 0);
770 if (bitsSeen == 32) {
771 bitsSeen = 0;
772 cpu->memory.store32(cpu, dest, block, 0);
773 dest += 4;
774 remaining -= 4;
775 block = 0;
776 }
777 }
778 }
779 cpu->gprs[0] = source;
780 cpu->gprs[1] = dest;
781}
782
783static void _unRl(struct GBA* gba, int width) {
784 struct ARMCore* cpu = gba->cpu;
785 uint32_t source = cpu->gprs[0];
786 int remaining = (cpu->memory.load32(cpu, source & 0xFFFFFFFC, 0) & 0xFFFFFF00) >> 8;
787 int padding = (4 - remaining) & 0x3;
788 // We assume the signature byte (0x30) is correct
789 int blockheader;
790 int block;
791 source += 4;
792 uint32_t dest = cpu->gprs[1];
793 int halfword = 0;
794 while (remaining > 0) {
795 blockheader = cpu->memory.load8(cpu, source, 0);
796 ++source;
797 if (blockheader & 0x80) {
798 // Compressed
799 blockheader &= 0x7F;
800 blockheader += 3;
801 block = cpu->memory.load8(cpu, source, 0);
802 ++source;
803 while (blockheader-- && remaining) {
804 --remaining;
805 if (width == 2) {
806 if (dest & 1) {
807 halfword |= block << 8;
808 cpu->memory.store16(cpu, dest ^ 1, halfword, 0);
809 } else {
810 halfword = block;
811 }
812 } else {
813 cpu->memory.store8(cpu, dest, block, 0);
814 }
815 ++dest;
816 }
817 } else {
818 // Uncompressed
819 blockheader++;
820 while (blockheader-- && remaining) {
821 --remaining;
822 int byte = cpu->memory.load8(cpu, source, 0);
823 ++source;
824 if (width == 2) {
825 if (dest & 1) {
826 halfword |= byte << 8;
827 cpu->memory.store16(cpu, dest ^ 1, halfword, 0);
828 } else {
829 halfword = byte;
830 }
831 } else {
832 cpu->memory.store8(cpu, dest, byte, 0);
833 }
834 ++dest;
835 }
836 }
837 }
838 if (width == 2) {
839 if (dest & 1) {
840 --padding;
841 ++dest;
842 }
843 for (; padding > 0; padding -= 2, dest += 2) {
844 cpu->memory.store16(cpu, dest, 0, 0);
845 }
846 } else {
847 while (padding--) {
848 cpu->memory.store8(cpu, dest, 0, 0);
849 ++dest;
850 }
851 }
852 cpu->gprs[0] = source;
853 cpu->gprs[1] = dest;
854}
855
856static void _unFilter(struct GBA* gba, int inwidth, int outwidth) {
857 struct ARMCore* cpu = gba->cpu;
858 uint32_t source = cpu->gprs[0] & 0xFFFFFFFC;
859 uint32_t dest = cpu->gprs[1];
860 uint32_t header = cpu->memory.load32(cpu, source, 0);
861 int remaining = header >> 8;
862 // We assume the signature nybble (0x8) is correct
863 uint16_t halfword = 0;
864 uint16_t old = 0;
865 source += 4;
866 while (remaining > 0) {
867 uint16_t new;
868 if (inwidth == 1) {
869 new = cpu->memory.load8(cpu, source, 0);
870 } else {
871 new = cpu->memory.load16(cpu, source, 0);
872 }
873 new += old;
874 if (outwidth > inwidth) {
875 halfword >>= 8;
876 halfword |= (new << 8);
877 if (source & 1) {
878 cpu->memory.store16(cpu, dest, halfword, 0);
879 dest += outwidth;
880 remaining -= outwidth;
881 }
882 } else if (outwidth == 1) {
883 cpu->memory.store8(cpu, dest, new, 0);
884 dest += outwidth;
885 remaining -= outwidth;
886 } else {
887 cpu->memory.store16(cpu, dest, new, 0);
888 dest += outwidth;
889 remaining -= outwidth;
890 }
891 old = new;
892 source += inwidth;
893 }
894 cpu->gprs[0] = source;
895 cpu->gprs[1] = dest;
896}
897
898static void _unBitPack(struct GBA* gba) {
899 struct ARMCore* cpu = gba->cpu;
900 uint32_t source = cpu->gprs[0];
901 uint32_t dest = cpu->gprs[1];
902 uint32_t info = cpu->gprs[2];
903 unsigned sourceLen = cpu->memory.load16(cpu, info, 0);
904 unsigned sourceWidth = cpu->memory.load8(cpu, info + 2, 0);
905 unsigned destWidth = cpu->memory.load8(cpu, info + 3, 0);
906 switch (sourceWidth) {
907 case 1:
908 case 2:
909 case 4:
910 case 8:
911 break;
912 default:
913 mLOG(GBA_BIOS, GAME_ERROR, "Bad BitUnPack source width: %u", sourceWidth);
914 return;
915 }
916 switch (destWidth) {
917 case 1:
918 case 2:
919 case 4:
920 case 8:
921 case 16:
922 case 32:
923 break;
924 default:
925 mLOG(GBA_BIOS, GAME_ERROR, "Bad BitUnPack destination width: %u", destWidth);
926 return;
927 }
928 uint32_t bias = cpu->memory.load32(cpu, info + 4, 0);
929 uint8_t in = 0;
930 uint32_t out = 0;
931 int bitsRemaining = 0;
932 int bitsEaten = 0;
933 while (sourceLen > 0 || bitsRemaining) {
934 if (!bitsRemaining) {
935 in = cpu->memory.load8(cpu, source, 0);
936 bitsRemaining = 8;
937 ++source;
938 --sourceLen;
939 }
940 unsigned scaled = in & ((1 << sourceWidth) - 1);
941 in >>= sourceWidth;
942 if (scaled || bias & 0x80000000) {
943 scaled += bias & 0x7FFFFFFF;
944 }
945 bitsRemaining -= sourceWidth;
946 out |= scaled << bitsEaten;
947 bitsEaten += destWidth;
948 if (bitsEaten == 32) {
949 cpu->memory.store32(cpu, dest, out, 0);
950 bitsEaten = 0;
951 out = 0;
952 dest += 4;
953 }
954 }
955 cpu->gprs[0] = source;
956 cpu->gprs[1] = dest;
957}