src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/sm83/sm83.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value);
39static void _GBPKJD(struct GB* gb, uint16_t address, uint8_t value);
40static void _GBBBD(struct GB* gb, uint16_t address, uint8_t value);
41static void _GBHitek(struct GB* gb, uint16_t address, uint8_t value);
42
43static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
44static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
45static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
46static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
47
48static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
49static uint8_t _GBPKJDRead(struct GBMemory*, uint16_t address);
50static uint8_t _GBBBDRead(struct GBMemory*, uint16_t address);
51static uint8_t _GBHitekRead(struct GBMemory*, uint16_t address);
52
53static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
54static void _GBPocketCamCapture(struct GBMemory*);
55
56static void _GBMBC6MapChip(struct GB*, int half, uint8_t value);
57
58void GBMBCSwitchBank(struct GB* gb, int bank) {
59 size_t bankStart = bank * GB_SIZE_CART_BANK0;
60 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
61 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
62 bankStart &= (gb->memory.romSize - 1);
63 bank = bankStart / GB_SIZE_CART_BANK0;
64 }
65 gb->memory.romBank = &gb->memory.rom[bankStart];
66 gb->memory.currentBank = bank;
67 if (gb->cpu->pc < GB_BASE_VRAM) {
68 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
69 }
70}
71
72void GBMBCSwitchBank0(struct GB* gb, int bank) {
73 size_t bankStart = bank * GB_SIZE_CART_BANK0;
74 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
75 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
76 bankStart &= (gb->memory.romSize - 1);
77 }
78 gb->memory.romBase = &gb->memory.rom[bankStart];
79 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
80 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
81 }
82}
83
84void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
85 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
86 bool isFlash = half ? gb->memory.mbcState.mbc6.flashBank1 : gb->memory.mbcState.mbc6.flashBank0;
87 if (isFlash) {
88 if (bankStart + GB_SIZE_CART_HALFBANK > GB_SIZE_MBC6_FLASH) {
89 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid Flash bank: %0X", bank);
90 bankStart &= GB_SIZE_MBC6_FLASH - 1;
91 bank = bankStart / GB_SIZE_CART_HALFBANK;
92 }
93 bankStart += gb->sramSize - GB_SIZE_MBC6_FLASH;
94 } else {
95 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
96 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
97 bankStart &= gb->memory.romSize - 1;
98 bank = bankStart / GB_SIZE_CART_HALFBANK;
99 if (!bank) {
100 ++bank;
101 }
102 }
103 }
104 if (!half) {
105 if (isFlash) {
106 gb->memory.romBank = &gb->memory.sram[bankStart];
107 } else {
108 gb->memory.romBank = &gb->memory.rom[bankStart];
109 }
110 gb->memory.currentBank = bank;
111 } else {
112 if (isFlash) {
113 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.sram[bankStart];
114 } else {
115 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
116 }
117 gb->memory.mbcState.mbc6.currentBank1 = bank;
118 }
119 if (gb->cpu->pc < GB_BASE_VRAM) {
120 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
121 }
122}
123
124static bool _isMulticart(const uint8_t* mem) {
125 bool success;
126 struct VFile* vf;
127
128 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
129 success = GBIsROM(vf);
130 vf->close(vf);
131
132 if (!success) {
133 return false;
134 }
135
136 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
137 success = GBIsROM(vf);
138 vf->close(vf);
139
140 if (!success) {
141 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
142 success = GBIsROM(vf);
143 vf->close(vf);
144 }
145
146 return success;
147}
148
149static bool _isWisdomTree(const uint8_t* mem, size_t size) {
150 size_t i;
151 for (i = 0x134; i < 0x14C; i += 4) {
152 if (*(uint32_t*) &mem[i] != 0) {
153 return false;
154 }
155 }
156 for (i = 0xF0; i < 0x100; i += 4) {
157 if (*(uint32_t*) &mem[i] != 0) {
158 return false;
159 }
160 }
161 if (mem[0x14D] != 0xE7) {
162 return false;
163 }
164 for (i = 0x300; i < size - 11; ++i) {
165 if (memcmp(&mem[i], "WISDOM", 6) == 0 && memcmp(&mem[i + 7], "TREE", 4) == 0) {
166 return true;
167 }
168 }
169 return false;
170}
171
172static enum GBMemoryBankControllerType _detectUnlMBC(const uint8_t* mem, size_t size) {
173 const struct GBCartridge* cart = (const struct GBCartridge*) &mem[0x100];
174
175 switch (cart->type) {
176 case 0:
177 if (_isWisdomTree(mem, size)) {
178 return GB_UNL_WISDOM_TREE;
179 }
180 break;
181 }
182
183 uint32_t secondaryLogo = doCrc32(&mem[0x184], 0x30);
184 switch (secondaryLogo) {
185 case 0x4fdab691:
186 return GB_UNL_HITEK;
187 case 0xc7d8c1df:
188 case 0x6d1ea662: // Garou
189 if (mem[0x7FFF] != 0x01) { // Make sure we're not using a "fixed" version
190 return GB_UNL_BBD;
191 }
192 }
193
194 return GB_MBC_AUTODETECT;
195}
196
197void GBMBCSwitchSramBank(struct GB* gb, int bank) {
198 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
199 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
200 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
201 bankStart &= (gb->sramSize - 1);
202 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
203 }
204 gb->memory.sramBank = &gb->memory.sram[bankStart];
205 gb->memory.sramCurrentBank = bank;
206}
207
208void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
209 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
210 size_t sramSize = gb->sramSize - GB_SIZE_MBC6_FLASH;
211 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > sramSize) {
212 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
213 bankStart &= (sramSize - 1);
214 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
215 }
216 if (!half) {
217 gb->memory.sramBank = &gb->memory.sram[bankStart];
218 gb->memory.sramCurrentBank = bank;
219 } else {
220 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
221 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
222 }
223}
224
225void GBMBCInit(struct GB* gb) {
226 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
227 if (gb->memory.rom) {
228 if (gb->memory.romSize >= 0x8000) {
229 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
230 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
231 cart = cartFooter;
232 }
233 }
234 switch (cart->ramSize) {
235 case 0:
236 gb->sramSize = 0;
237 break;
238 case 1:
239 gb->sramSize = 0x800;
240 break;
241 default:
242 case 2:
243 gb->sramSize = 0x2000;
244 break;
245 case 3:
246 gb->sramSize = 0x8000;
247 break;
248 case 4:
249 gb->sramSize = 0x20000;
250 break;
251 case 5:
252 gb->sramSize = 0x10000;
253 break;
254 }
255 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
256 gb->memory.mbcType = _detectUnlMBC(gb->memory.rom, gb->memory.romSize);
257 }
258
259 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
260 switch (cart->type) {
261 case 0:
262 case 8:
263 case 9:
264 gb->memory.mbcType = GB_MBC_NONE;
265 break;
266 case 1:
267 case 2:
268 case 3:
269 gb->memory.mbcType = GB_MBC1;
270 break;
271 case 5:
272 case 6:
273 gb->memory.mbcType = GB_MBC2;
274 break;
275 case 0x0B:
276 case 0x0C:
277 case 0x0D:
278 gb->memory.mbcType = GB_MMM01;
279 break;
280 case 0x0F:
281 case 0x10:
282 gb->memory.mbcType = GB_MBC3_RTC;
283 break;
284 case 0x11:
285 case 0x12:
286 case 0x13:
287 gb->memory.mbcType = GB_MBC3;
288 break;
289 default:
290 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
291 // Fall through
292 case 0x19:
293 case 0x1A:
294 case 0x1B:
295 gb->memory.mbcType = GB_MBC5;
296 break;
297 case 0x1C:
298 case 0x1D:
299 case 0x1E:
300 gb->memory.mbcType = GB_MBC5_RUMBLE;
301 break;
302 case 0x20:
303 gb->memory.mbcType = GB_MBC6;
304 break;
305 case 0x22:
306 gb->memory.mbcType = GB_MBC7;
307 break;
308 case 0xFC:
309 gb->memory.mbcType = GB_POCKETCAM;
310 break;
311 case 0xFD:
312 gb->memory.mbcType = GB_TAMA5;
313 break;
314 case 0xFE:
315 gb->memory.mbcType = GB_HuC3;
316 break;
317 case 0xFF:
318 gb->memory.mbcType = GB_HuC1;
319 break;
320 }
321 }
322 } else {
323 gb->memory.mbcType = GB_MBC_NONE;
324 }
325 gb->memory.mbcRead = NULL;
326 gb->memory.directSramAccess = true;
327 switch (gb->memory.mbcType) {
328 case GB_MBC_NONE:
329 gb->memory.mbcWrite = _GBMBCNone;
330 break;
331 case GB_MBC1:
332 gb->memory.mbcWrite = _GBMBC1;
333 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
334 gb->memory.mbcState.mbc1.multicartStride = 4;
335 } else {
336 gb->memory.mbcState.mbc1.multicartStride = 5;
337 }
338 break;
339 case GB_MBC2:
340 gb->memory.mbcWrite = _GBMBC2;
341 gb->memory.mbcRead = _GBMBC2Read;
342 gb->memory.directSramAccess = false;
343 gb->sramSize = 0x100;
344 break;
345 case GB_MBC3:
346 gb->memory.mbcWrite = _GBMBC3;
347 break;
348 default:
349 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
350 // Fall through
351 case GB_MBC5:
352 gb->memory.mbcWrite = _GBMBC5;
353 break;
354 case GB_MBC6:
355 gb->memory.mbcWrite = _GBMBC6;
356 gb->memory.mbcRead = _GBMBC6Read;
357 gb->memory.directSramAccess = false;
358 gb->sramSize += GB_SIZE_MBC6_FLASH; // Flash is concatenated at the end
359 break;
360 case GB_MBC7:
361 gb->memory.mbcWrite = _GBMBC7;
362 gb->memory.mbcRead = _GBMBC7Read;
363 gb->sramSize = 0x100;
364 break;
365 case GB_MMM01:
366 gb->memory.mbcWrite = _GBMMM01;
367 break;
368 case GB_HuC1:
369 gb->memory.mbcWrite = _GBHuC1;
370 break;
371 case GB_HuC3:
372 gb->memory.mbcWrite = _GBHuC3;
373 break;
374 case GB_TAMA5:
375 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
376 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
377 gb->memory.mbcWrite = _GBTAMA5;
378 gb->memory.mbcRead = _GBTAMA5Read;
379 gb->sramSize = 0x20;
380 break;
381 case GB_MBC3_RTC:
382 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
383 gb->memory.mbcWrite = _GBMBC3;
384 break;
385 case GB_MBC5_RUMBLE:
386 gb->memory.mbcWrite = _GBMBC5;
387 break;
388 case GB_POCKETCAM:
389 gb->memory.mbcWrite = _GBPocketCam;
390 gb->memory.mbcRead = _GBPocketCamRead;
391 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
392 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
393 }
394 break;
395 case GB_UNL_WISDOM_TREE:
396 gb->memory.mbcWrite = _GBWisdomTree;
397 break;
398 case GB_UNL_BBD:
399 gb->memory.mbcWrite = _GBBBD;
400 gb->memory.mbcRead = _GBBBDRead;
401 break;
402 case GB_UNL_HITEK:
403 gb->memory.mbcWrite = _GBHitek;
404 gb->memory.mbcRead = _GBHitekRead;
405 gb->memory.mbcState.bbd.dataSwapMode = 7;
406 gb->memory.mbcState.bbd.bankSwapMode = 7;
407 break;
408 case GB_UNL_PKJD:
409 gb->memory.mbcWrite = _GBPKJD;
410 gb->memory.mbcRead = _GBPKJDRead;
411 break;
412 }
413
414 gb->memory.currentBank = 1;
415 gb->memory.sramCurrentBank = 0;
416 gb->memory.sramAccess = false;
417 gb->memory.rtcAccess = false;
418 gb->memory.activeRtcReg = 0;
419 gb->memory.rtcLatched = false;
420 gb->memory.rtcLastLatch = 0;
421 if (gb->memory.rtc) {
422 if (gb->memory.rtc->sample) {
423 gb->memory.rtc->sample(gb->memory.rtc);
424 }
425 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
426 } else {
427 gb->memory.rtcLastLatch = time(0);
428 }
429 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
430
431 GBResizeSram(gb, gb->sramSize);
432
433 if (gb->memory.mbcType == GB_MBC3_RTC) {
434 GBMBCRTCRead(gb);
435 }
436}
437
438static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
439 time_t t;
440 if (rtc) {
441 if (rtc->sample) {
442 rtc->sample(rtc);
443 }
444 t = rtc->unixTime(rtc);
445 } else {
446 t = time(0);
447 }
448 time_t currentLatch = t;
449 t -= *rtcLastLatch;
450 *rtcLastLatch = currentLatch;
451
452 int64_t diff;
453 diff = rtcRegs[0] + t % 60;
454 if (diff < 0) {
455 diff += 60;
456 t -= 60;
457 }
458 rtcRegs[0] = diff % 60;
459 t /= 60;
460 t += diff / 60;
461
462 diff = rtcRegs[1] + t % 60;
463 if (diff < 0) {
464 diff += 60;
465 t -= 60;
466 }
467 rtcRegs[1] = diff % 60;
468 t /= 60;
469 t += diff / 60;
470
471 diff = rtcRegs[2] + t % 24;
472 if (diff < 0) {
473 diff += 24;
474 t -= 24;
475 }
476 rtcRegs[2] = diff % 24;
477 t /= 24;
478 t += diff / 24;
479
480 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
481 rtcRegs[3] = diff;
482 rtcRegs[4] &= 0xFE;
483 rtcRegs[4] |= (diff >> 8) & 1;
484 if (diff & 0x200) {
485 rtcRegs[4] |= 0x80;
486 }
487}
488
489static void _GBMBC1Update(struct GB* gb) {
490 struct GBMBC1State* state = &gb->memory.mbcState.mbc1;
491 int bank = state->bankLo;
492 bank &= (1 << state->multicartStride) - 1;
493 bank |= state->bankHi << state->multicartStride;
494 if (state->mode) {
495 GBMBCSwitchBank0(gb, state->bankHi << state->multicartStride);
496 GBMBCSwitchSramBank(gb, state->bankHi & 3);
497 } else {
498 GBMBCSwitchBank0(gb, 0);
499 GBMBCSwitchSramBank(gb, 0);
500 }
501 if (!(state->bankLo & 0x1F)) {
502 ++state->bankLo;
503 ++bank;
504 }
505 GBMBCSwitchBank(gb, bank);
506}
507
508void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
509 struct GBMemory* memory = &gb->memory;
510 int bank = value & 0x1F;
511 switch (address >> 13) {
512 case 0x0:
513 switch (value & 0xF) {
514 case 0:
515 memory->sramAccess = false;
516 break;
517 case 0xA:
518 memory->sramAccess = true;
519 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
520 break;
521 default:
522 // TODO
523 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
524 break;
525 }
526 break;
527 case 0x1:
528 memory->mbcState.mbc1.bankLo = bank;
529 _GBMBC1Update(gb);
530 break;
531 case 0x2:
532 bank &= 3;
533 memory->mbcState.mbc1.bankHi = bank;
534 _GBMBC1Update(gb);
535 break;
536 case 0x3:
537 memory->mbcState.mbc1.mode = value & 1;
538 _GBMBC1Update(gb);
539 break;
540 default:
541 // TODO
542 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
543 break;
544 }
545}
546
547void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
548 struct GBMemory* memory = &gb->memory;
549 int shift = (address & 1) * 4;
550 int bank = value & 0xF;
551 switch ((address & 0xC100) >> 8) {
552 case 0x0:
553 switch (value & 0x0F) {
554 case 0:
555 memory->sramAccess = false;
556 break;
557 case 0xA:
558 memory->sramAccess = true;
559 break;
560 default:
561 // TODO
562 mLOG(GB_MBC, STUB, "MBC2 unknown value %02X", value);
563 break;
564 }
565 break;
566 case 0x1:
567 if (!bank) {
568 ++bank;
569 }
570 GBMBCSwitchBank(gb, bank);
571 break;
572 case 0x80:
573 case 0x81:
574 case 0x82:
575 case 0x83:
576 if (!memory->sramAccess) {
577 return;
578 }
579 address &= 0x1FF;
580 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
581 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
582 break;
583 default:
584 // TODO
585 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
586 break;
587 }
588}
589
590static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
591 if (!memory->sramAccess) {
592 return 0xFF;
593 }
594 address &= 0x1FF;
595 int shift = (address & 1) * 4;
596 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
597}
598
599void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
600 struct GBMemory* memory = &gb->memory;
601 int bank = value;
602 switch (address >> 13) {
603 case 0x0:
604 switch (value & 0xF) {
605 case 0:
606 memory->sramAccess = false;
607 break;
608 case 0xA:
609 memory->sramAccess = true;
610 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
611 break;
612 default:
613 // TODO
614 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
615 break;
616 }
617 break;
618 case 0x1:
619 if (gb->memory.romSize < GB_SIZE_CART_BANK0 * 0x80) {
620 bank &= 0x7F;
621 }
622 if (!bank) {
623 ++bank;
624 }
625 GBMBCSwitchBank(gb, bank);
626 break;
627 case 0x2:
628 bank &= 0xF;
629 if (bank < 8) {
630 GBMBCSwitchSramBank(gb, value);
631 memory->rtcAccess = false;
632 } else if (bank <= 0xC) {
633 memory->activeRtcReg = bank - 8;
634 memory->rtcAccess = true;
635 }
636 break;
637 case 0x3:
638 if (memory->rtcLatched && value == 0) {
639 memory->rtcLatched = false;
640 } else if (!memory->rtcLatched && value == 1) {
641 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
642 memory->rtcLatched = true;
643 }
644 break;
645 }
646}
647
648void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
649 struct GBMemory* memory = &gb->memory;
650 int bank;
651 switch (address >> 12) {
652 case 0x0:
653 case 0x1:
654 switch (value) {
655 case 0:
656 memory->sramAccess = false;
657 break;
658 case 0xA:
659 memory->sramAccess = true;
660 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
661 break;
662 default:
663 // TODO
664 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
665 break;
666 }
667 break;
668 case 0x2:
669 bank = (memory->currentBank & 0x100) | value;
670 GBMBCSwitchBank(gb, bank);
671 break;
672 case 0x3:
673 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
674 GBMBCSwitchBank(gb, bank);
675 break;
676 case 0x4:
677 case 0x5:
678 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
679 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
680 value &= ~8;
681 }
682 GBMBCSwitchSramBank(gb, value & 0xF);
683 break;
684 default:
685 // TODO
686 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
687 break;
688 }
689}
690
691void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
692 struct GBMemory* memory = &gb->memory;
693 int bank = value;
694 switch (address >> 10) {
695 case 0:
696 switch (value) {
697 case 0:
698 memory->sramAccess = false;
699 break;
700 case 0xA:
701 memory->sramAccess = true;
702 break;
703 default:
704 // TODO
705 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
706 break;
707 }
708 break;
709 case 0x1:
710 GBMBCSwitchSramHalfBank(gb, 0, bank);
711 break;
712 case 0x2:
713 GBMBCSwitchSramHalfBank(gb, 1, bank);
714 break;
715 case 0x3:
716 mLOG(GB_MBC, STUB, "MBC6 unimplemented flash OE write: %04X:%02X", address, value);
717 break;
718 case 0x4:
719 mLOG(GB_MBC, STUB, "MBC6 unimplemented flash WE write: %04X:%02X", address, value);
720 break;
721 case 0x8:
722 case 0x9:
723 GBMBCSwitchHalfBank(gb, 0, bank);
724 break;
725 case 0xA:
726 case 0xB:
727 _GBMBC6MapChip(gb, 0, value);
728 break;
729 case 0xC:
730 case 0xD:
731 GBMBCSwitchHalfBank(gb, 1, bank);
732 break;
733 case 0xE:
734 case 0xF:
735 _GBMBC6MapChip(gb, 1, value);
736 break;
737 case 0x28:
738 case 0x29:
739 case 0x2A:
740 case 0x2B:
741 if (memory->sramAccess) {
742 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
743 }
744 break;
745 case 0x2C:
746 case 0x2D:
747 case 0x2E:
748 case 0x2F:
749 if (memory->sramAccess) {
750 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
751 }
752 break;
753 default:
754 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
755 break;
756 }
757}
758
759uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
760 if (!memory->sramAccess) {
761 return 0xFF;
762 }
763 switch (address >> 12) {
764 case 0xA:
765 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
766 case 0xB:
767 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
768 }
769 return 0xFF;
770}
771
772static void _GBMBC6MapChip(struct GB* gb, int half, uint8_t value) {
773 if (!half) {
774 gb->memory.mbcState.mbc6.flashBank0 = !!(value & 0x08);
775 GBMBCSwitchHalfBank(gb, half, gb->memory.currentBank);
776 } else {
777 gb->memory.mbcState.mbc6.flashBank1 = !!(value & 0x08);
778 GBMBCSwitchHalfBank(gb, half, gb->memory.mbcState.mbc6.currentBank1);
779 }
780}
781
782void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
783 int bank = value & 0x7F;
784 switch (address >> 13) {
785 case 0x0:
786 switch (value) {
787 default:
788 case 0:
789 gb->memory.mbcState.mbc7.access = 0;
790 break;
791 case 0xA:
792 gb->memory.mbcState.mbc7.access |= 1;
793 break;
794 }
795 break;
796 case 0x1:
797 GBMBCSwitchBank(gb, bank);
798 break;
799 case 0x2:
800 if (value == 0x40) {
801 gb->memory.mbcState.mbc7.access |= 2;
802 } else {
803 gb->memory.mbcState.mbc7.access &= ~2;
804 }
805 break;
806 case 0x5:
807 _GBMBC7Write(&gb->memory, address, value);
808 break;
809 default:
810 // TODO
811 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
812 break;
813 }
814}
815
816uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
817 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
818 if (mbc7->access != 3) {
819 return 0xFF;
820 }
821 switch (address & 0xF0) {
822 case 0x20:
823 if (memory->rotation && memory->rotation->readTiltX) {
824 int32_t x = -memory->rotation->readTiltX(memory->rotation);
825 x >>= 21;
826 x += 0x81D0;
827 return x;
828 }
829 return 0xFF;
830 case 0x30:
831 if (memory->rotation && memory->rotation->readTiltX) {
832 int32_t x = -memory->rotation->readTiltX(memory->rotation);
833 x >>= 21;
834 x += 0x81D0;
835 return x >> 8;
836 }
837 return 7;
838 case 0x40:
839 if (memory->rotation && memory->rotation->readTiltY) {
840 int32_t y = -memory->rotation->readTiltY(memory->rotation);
841 y >>= 21;
842 y += 0x81D0;
843 return y;
844 }
845 return 0xFF;
846 case 0x50:
847 if (memory->rotation && memory->rotation->readTiltY) {
848 int32_t y = -memory->rotation->readTiltY(memory->rotation);
849 y >>= 21;
850 y += 0x81D0;
851 return y >> 8;
852 }
853 return 7;
854 case 0x60:
855 return 0;
856 case 0x80:
857 return mbc7->eeprom;
858 default:
859 return 0xFF;
860 }
861}
862
863static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
864 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
865 if (mbc7->access != 3) {
866 return;
867 }
868 switch (address & 0xF0) {
869 case 0x00:
870 mbc7->latch = (value & 0x55) == 0x55;
871 return;
872 case 0x10:
873 mbc7->latch |= (value & 0xAA);
874 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
875 memory->rotation->sample(memory->rotation);
876 }
877 mbc7->latch = 0;
878 return;
879 default:
880 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
881 return;
882 case 0x80:
883 break;
884 }
885 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
886 value = GBMBC7FieldFillDO(value); // Hi-Z
887 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
888 mbc7->state = GBMBC7_STATE_IDLE;
889 }
890 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
891 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
892 mbc7->sr <<= 1;
893 mbc7->sr |= GBMBC7FieldGetDI(value);
894 ++mbc7->srBits;
895 }
896 switch (mbc7->state) {
897 case GBMBC7_STATE_IDLE:
898 if (GBMBC7FieldIsDI(value)) {
899 mbc7->state = GBMBC7_STATE_READ_COMMAND;
900 mbc7->srBits = 0;
901 mbc7->sr = 0;
902 }
903 break;
904 case GBMBC7_STATE_READ_COMMAND:
905 if (mbc7->srBits == 10) {
906 mbc7->state = 0x10 | (mbc7->sr >> 6);
907 if (mbc7->state & 0xC) {
908 mbc7->state &= ~0x3;
909 }
910 mbc7->srBits = 0;
911 mbc7->address = mbc7->sr & 0x7F;
912 }
913 break;
914 case GBMBC7_STATE_DO:
915 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
916 mbc7->sr <<= 1;
917 --mbc7->srBits;
918 if (!mbc7->srBits) {
919 mbc7->state = GBMBC7_STATE_IDLE;
920 }
921 break;
922 default:
923 break;
924 }
925 switch (mbc7->state) {
926 case GBMBC7_STATE_EEPROM_EWEN:
927 mbc7->writable = true;
928 mbc7->state = GBMBC7_STATE_IDLE;
929 break;
930 case GBMBC7_STATE_EEPROM_EWDS:
931 mbc7->writable = false;
932 mbc7->state = GBMBC7_STATE_IDLE;
933 break;
934 case GBMBC7_STATE_EEPROM_WRITE:
935 if (mbc7->srBits == 16) {
936 if (mbc7->writable) {
937 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
938 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
939 }
940 mbc7->state = GBMBC7_STATE_IDLE;
941 }
942 break;
943 case GBMBC7_STATE_EEPROM_ERASE:
944 if (mbc7->writable) {
945 memory->sram[mbc7->address * 2] = 0xFF;
946 memory->sram[mbc7->address * 2 + 1] = 0xFF;
947 }
948 mbc7->state = GBMBC7_STATE_IDLE;
949 break;
950 case GBMBC7_STATE_EEPROM_READ:
951 mbc7->srBits = 16;
952 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
953 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
954 mbc7->state = GBMBC7_STATE_DO;
955 value = GBMBC7FieldClearDO(value);
956 break;
957 case GBMBC7_STATE_EEPROM_WRAL:
958 if (mbc7->srBits == 16) {
959 if (mbc7->writable) {
960 int i;
961 for (i = 0; i < 128; ++i) {
962 memory->sram[i * 2] = mbc7->sr >> 8;
963 memory->sram[i * 2 + 1] = mbc7->sr;
964 }
965 }
966 mbc7->state = GBMBC7_STATE_IDLE;
967 }
968 break;
969 case GBMBC7_STATE_EEPROM_ERAL:
970 if (mbc7->writable) {
971 int i;
972 for (i = 0; i < 128; ++i) {
973 memory->sram[i * 2] = 0xFF;
974 memory->sram[i * 2 + 1] = 0xFF;
975 }
976 }
977 mbc7->state = GBMBC7_STATE_IDLE;
978 break;
979 default:
980 break;
981 }
982 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
983 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
984 }
985 mbc7->eeprom = value;
986}
987
988void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
989 struct GBMemory* memory = &gb->memory;
990 if (!memory->mbcState.mmm01.locked) {
991 switch (address >> 13) {
992 case 0x0:
993 memory->mbcState.mmm01.locked = true;
994 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
995 break;
996 case 0x1:
997 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
998 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
999 break;
1000 case 0x2:
1001 memory->mbcState.mmm01.currentBank0 &= ~0x180;
1002 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
1003 break;
1004 default:
1005 // TODO
1006 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
1007 break;
1008 }
1009 return;
1010 }
1011 switch (address >> 13) {
1012 case 0x0:
1013 switch (value) {
1014 case 0xA:
1015 memory->sramAccess = true;
1016 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1017 break;
1018 default:
1019 memory->sramAccess = false;
1020 break;
1021 }
1022 break;
1023 case 0x1:
1024 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
1025 break;
1026 case 0x2:
1027 GBMBCSwitchSramBank(gb, value);
1028 break;
1029 default:
1030 // TODO
1031 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
1032 break;
1033 }
1034}
1035
1036void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
1037 struct GBMemory* memory = &gb->memory;
1038 int bank = value & 0x3F;
1039 switch (address >> 13) {
1040 case 0x0:
1041 switch (value) {
1042 case 0xE:
1043 memory->sramAccess = false;
1044 break;
1045 default:
1046 memory->sramAccess = true;
1047 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1048 break;
1049 }
1050 break;
1051 case 0x1:
1052 GBMBCSwitchBank(gb, bank);
1053 break;
1054 case 0x2:
1055 GBMBCSwitchSramBank(gb, value);
1056 break;
1057 default:
1058 // TODO
1059 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
1060 break;
1061 }
1062}
1063
1064void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
1065 struct GBMemory* memory = &gb->memory;
1066 int bank = value & 0x3F;
1067 if (address & 0x1FFF) {
1068 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
1069 }
1070
1071 switch (address >> 13) {
1072 case 0x0:
1073 switch (value) {
1074 case 0xA:
1075 memory->sramAccess = true;
1076 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1077 break;
1078 default:
1079 memory->sramAccess = false;
1080 break;
1081 }
1082 break;
1083 case 0x1:
1084 GBMBCSwitchBank(gb, bank);
1085 break;
1086 case 0x2:
1087 GBMBCSwitchSramBank(gb, bank);
1088 break;
1089 default:
1090 // TODO
1091 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
1092 break;
1093 }
1094}
1095
1096void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
1097 struct GBMemory* memory = &gb->memory;
1098 int bank = value & 0x3F;
1099 switch (address >> 13) {
1100 case 0x0:
1101 switch (value) {
1102 case 0:
1103 memory->sramAccess = false;
1104 break;
1105 case 0xA:
1106 memory->sramAccess = true;
1107 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1108 break;
1109 default:
1110 // TODO
1111 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
1112 break;
1113 }
1114 break;
1115 case 0x1:
1116 GBMBCSwitchBank(gb, bank);
1117 break;
1118 case 0x2:
1119 if (value < 0x10) {
1120 GBMBCSwitchSramBank(gb, value);
1121 memory->mbcState.pocketCam.registersActive = false;
1122 } else {
1123 memory->mbcState.pocketCam.registersActive = true;
1124 }
1125 break;
1126 case 0x5:
1127 address &= 0x7F;
1128 if (address == 0 && value & 1) {
1129 value &= 6; // TODO: Timing
1130 _GBPocketCamCapture(memory);
1131 }
1132 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
1133 memory->mbcState.pocketCam.registers[address] = value;
1134 }
1135 break;
1136 default:
1137 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
1138 break;
1139 }
1140}
1141
1142uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1143 if (memory->mbcState.pocketCam.registersActive) {
1144 if ((address & 0x7F) == 0) {
1145 return memory->mbcState.pocketCam.registers[0];
1146 }
1147 return 0;
1148 }
1149 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1150}
1151
1152void _GBPocketCamCapture(struct GBMemory* memory) {
1153 if (!memory->cam) {
1154 return;
1155 }
1156 const void* image = NULL;
1157 size_t stride;
1158 enum mColorFormat format;
1159 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1160 if (!image) {
1161 return;
1162 }
1163 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1164 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1165 size_t x, y;
1166 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1167 for (x = 0; x < GBCAM_WIDTH; ++x) {
1168 uint32_t gray;
1169 uint32_t color;
1170 switch (format) {
1171 case mCOLOR_XBGR8:
1172 case mCOLOR_XRGB8:
1173 case mCOLOR_ARGB8:
1174 case mCOLOR_ABGR8:
1175 color = ((const uint32_t*) image)[y * stride + x];
1176 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1177 break;
1178 case mCOLOR_BGRX8:
1179 case mCOLOR_RGBX8:
1180 case mCOLOR_RGBA8:
1181 case mCOLOR_BGRA8:
1182 color = ((const uint32_t*) image)[y * stride + x];
1183 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1184 break;
1185 case mCOLOR_BGR5:
1186 case mCOLOR_RGB5:
1187 case mCOLOR_ARGB5:
1188 case mCOLOR_ABGR5:
1189 color = ((const uint16_t*) image)[y * stride + x];
1190 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1191 break;
1192 case mCOLOR_BGR565:
1193 case mCOLOR_RGB565:
1194 color = ((const uint16_t*) image)[y * stride + x];
1195 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1196 break;
1197 case mCOLOR_BGRA5:
1198 case mCOLOR_RGBA5:
1199 color = ((const uint16_t*) image)[y * stride + x];
1200 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1201 break;
1202 default:
1203 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1204 return;
1205 }
1206 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1207 gray = (gray + 1) * exposure / 0x300;
1208 // TODO: Additional processing
1209 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1210 if (gray < pocketCam->registers[matrixEntry + 6]) {
1211 gray = 0x101;
1212 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1213 gray = 0x100;
1214 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1215 gray = 0x001;
1216 } else {
1217 gray = 0;
1218 }
1219 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1220 uint16_t existing;
1221 LOAD_16LE(existing, coord + 0x100, memory->sram);
1222 existing |= gray << (7 - (x & 7));
1223 STORE_16LE(existing, coord + 0x100, memory->sram);
1224 }
1225 }
1226}
1227
1228void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1229 struct GBMemory* memory = &gb->memory;
1230 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1231 switch (address >> 13) {
1232 case 0x5:
1233 if (address & 1) {
1234 tama5->reg = value;
1235 } else {
1236 value &= 0xF;
1237 if (tama5->reg < GBTAMA5_MAX) {
1238 tama5->registers[tama5->reg] = value;
1239 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1240 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1241 switch (tama5->reg) {
1242 case GBTAMA5_BANK_LO:
1243 case GBTAMA5_BANK_HI:
1244 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1245 break;
1246 case GBTAMA5_WRITE_LO:
1247 case GBTAMA5_WRITE_HI:
1248 case GBTAMA5_CS:
1249 break;
1250 case GBTAMA5_ADDR_LO:
1251 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1252 case 0x0: // RAM write
1253 memory->sram[address] = out;
1254 break;
1255 case 0x1: // RAM read
1256 break;
1257 default:
1258 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1259 }
1260 break;
1261 default:
1262 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1263 break;
1264 }
1265 } else {
1266 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1267 }
1268 }
1269 break;
1270 default:
1271 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1272 }
1273}
1274
1275uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1276 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1277 if ((address & 0x1FFF) > 1) {
1278 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1279 }
1280 if (address & 1) {
1281 return 0xFF;
1282 } else {
1283 uint8_t value = 0xF0;
1284 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1285 switch (tama5->reg) {
1286 case GBTAMA5_ACTIVE:
1287 return 0xF1;
1288 case GBTAMA5_READ_LO:
1289 case GBTAMA5_READ_HI:
1290 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1291 case 1:
1292 value = memory->sram[address];
1293 break;
1294 default:
1295 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1296 break;
1297 }
1298 if (tama5->reg == GBTAMA5_READ_HI) {
1299 value >>= 4;
1300 }
1301 value |= 0xF0;
1302 return value;
1303 default:
1304 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1305 return 0xF1;
1306 }
1307 }
1308}
1309
1310void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) {
1311 UNUSED(value);
1312 int bank = address & 0x3F;
1313 switch (address >> 14) {
1314 case 0x0:
1315 GBMBCSwitchBank0(gb, bank * 2);
1316 GBMBCSwitchBank(gb, bank * 2 + 1);
1317 break;
1318 default:
1319 // TODO
1320 mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value);
1321 break;
1322 }
1323}
1324
1325void _GBPKJD(struct GB* gb, uint16_t address, uint8_t value) {
1326 struct GBMemory* memory = &gb->memory;
1327 switch (address >> 13) {
1328 case 0x2:
1329 if (value < 8) {
1330 memory->directSramAccess = true;
1331 memory->activeRtcReg = 0;
1332 } else if (value >= 0xD && value <= 0xF) {
1333 memory->directSramAccess = false;
1334 memory->rtcAccess = false;
1335 memory->activeRtcReg = value - 8;
1336 }
1337 break;
1338 case 0x5:
1339 if (!memory->sramAccess) {
1340 return;
1341 }
1342 switch (memory->activeRtcReg) {
1343 case 0:
1344 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
1345 break;
1346 case 5:
1347 case 6:
1348 memory->mbcState.pkjd.reg[memory->activeRtcReg - 5] = value;
1349 break;
1350 case 7:
1351 switch (value) {
1352 case 0x11:
1353 memory->mbcState.pkjd.reg[0]--;
1354 break;
1355 case 0x12:
1356 memory->mbcState.pkjd.reg[1]--;
1357 break;
1358 case 0x41:
1359 memory->mbcState.pkjd.reg[0] += memory->mbcState.pkjd.reg[1];
1360 break;
1361 case 0x42:
1362 memory->mbcState.pkjd.reg[1] += memory->mbcState.pkjd.reg[0];
1363 break;
1364 case 0x51:
1365 memory->mbcState.pkjd.reg[0]++;
1366 break;
1367 case 0x52:
1368 memory->mbcState.pkjd.reg[1]--;
1369 break;
1370 }
1371 break;
1372 }
1373 return;
1374 }
1375 _GBMBC3(gb, address, value);
1376}
1377
1378static uint8_t _GBPKJDRead(struct GBMemory* memory, uint16_t address) {
1379 if (!memory->sramAccess) {
1380 return 0xFF;
1381 }
1382 switch (memory->activeRtcReg) {
1383 case 0:
1384 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1385 case 5:
1386 case 6:
1387 return memory->mbcState.pkjd.reg[memory->activeRtcReg - 5];
1388 default:
1389 return 0;
1390 }
1391}
1392
1393static uint8_t _reorderBits(uint8_t input, const uint8_t* reorder) {
1394 uint8_t newbyte = 0;
1395 int i;
1396 for(i = 0; i < 8; ++i) {
1397 int oldbit = reorder[i];
1398 int newbit = i;
1399 newbyte += ((input >> oldbit) & 1) << newbit;
1400 }
1401
1402 return newbyte;
1403}
1404
1405static const uint8_t _bbdDataReordering[8][8] = {
1406 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 00 - Normal
1407 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 01 - NOT KNOWN YET
1408 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 02 - NOT KNOWN YET
1409 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 03 - NOT KNOWN YET
1410 { 0, 5, 1, 3, 4, 2, 6, 7 }, // 04 - Garou
1411 { 0, 4, 2, 3, 1, 5, 6, 7 }, // 05 - Harry
1412 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 06 - NOT KNOWN YET
1413 { 0, 1, 5, 3, 4, 2, 6, 7 }, // 07 - Digimon
1414};
1415
1416static const uint8_t _bbdBankReordering[8][8] = {
1417 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 00 - Normal
1418 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 01 - NOT KNOWN YET
1419 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 02 - NOT KNOWN YET
1420 { 3, 4, 2, 0, 1, 5, 6, 7 }, // 03 - 0,1 unconfirmed. Digimon/Garou
1421 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 04 - NOT KNOWN YET
1422 { 1, 2, 3, 4, 0, 5, 6, 7 }, // 05 - 0,1 unconfirmed. Harry
1423 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 06 - NOT KNOWN YET
1424 { 0, 1, 2, 3, 4, 5, 6, 7 }, // 07 - NOT KNOWN YET
1425};
1426
1427void _GBBBD(struct GB* gb, uint16_t address, uint8_t value) {
1428 struct GBMemory* memory = &gb->memory;
1429 switch (address & 0xF0FF) {
1430 case 0x2000:
1431 value = _reorderBits(value, _bbdBankReordering[memory->mbcState.bbd.bankSwapMode]);
1432 break;
1433 case 0x2001:
1434 memory->mbcState.bbd.dataSwapMode = value & 0x07;
1435 if (!(memory->mbcState.bbd.dataSwapMode == 0x07 || memory->mbcState.bbd.dataSwapMode == 0x05 || memory->mbcState.bbd.dataSwapMode == 0x04 || memory->mbcState.bbd.dataSwapMode == 0x00)) {
1436 mLOG(GB_MBC, STUB, "Bitswap mode unsupported: %X", memory->mbcState.bbd.dataSwapMode);
1437 }
1438 break;
1439 case 0x2080:
1440 memory->mbcState.bbd.bankSwapMode = value & 0x07;
1441 if (!(memory->mbcState.bbd.bankSwapMode == 0x03 || memory->mbcState.bbd.bankSwapMode == 0x05 || memory->mbcState.bbd.bankSwapMode == 0x00)) {
1442 mLOG(GB_MBC, STUB, "Bankswap mode unsupported: %X", memory->mbcState.bbd.dataSwapMode);
1443 }
1444 break;
1445 }
1446 _GBMBC5(gb, address, value);
1447}
1448
1449uint8_t _GBBBDRead(struct GBMemory* memory, uint16_t address) {
1450 switch (address >> 14) {
1451 case 0:
1452 default:
1453 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
1454 case 1:
1455 return _reorderBits(memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)], _bbdDataReordering[memory->mbcState.bbd.dataSwapMode]);
1456 }
1457}
1458
1459static const uint8_t _hitekDataReordering[8][8] = {
1460 { 0, 1, 2, 3, 4, 5, 6, 7 },
1461 { 0, 6, 5, 3, 4, 1, 2, 7 },
1462 { 0, 5, 6, 3, 4, 2, 1, 7 },
1463 { 0, 6, 2, 3, 4, 5, 1, 7 },
1464 { 0, 6, 1, 3, 4, 5, 2, 7 },
1465 { 0, 1, 6, 3, 4, 5, 2, 7 },
1466 { 0, 2, 6, 3, 4, 1, 5, 7 },
1467 { 0, 6, 2, 3, 4, 1, 5, 7 },
1468};
1469
1470static const uint8_t _hitekBankReordering[8][8] = {
1471 { 0, 1, 2, 3, 4, 5, 6, 7 },
1472 { 3, 2, 1, 0, 4, 5, 6, 7 },
1473 { 2, 1, 0, 3, 4, 5, 6, 7 },
1474 { 1, 0, 3, 2, 4, 5, 6, 7 },
1475 { 0, 3, 2, 1, 4, 5, 6, 7 },
1476 { 2, 3, 0, 1, 4, 5, 6, 7 },
1477 { 3, 0, 1, 2, 4, 5, 6, 7 },
1478 { 2, 0, 3, 1, 4, 5, 6, 7 },
1479};
1480
1481void _GBHitek(struct GB* gb, uint16_t address, uint8_t value) {
1482 struct GBMemory* memory = &gb->memory;
1483 switch (address & 0xF0FF) {
1484 case 0x2000:
1485 value = _reorderBits(value, _hitekBankReordering[memory->mbcState.bbd.bankSwapMode]);
1486 break;
1487 case 0x2001:
1488 memory->mbcState.bbd.dataSwapMode = value & 0x07;
1489 break;
1490 case 0x2080:
1491 memory->mbcState.bbd.bankSwapMode = value & 0x07;
1492 break;
1493 case 0x300:
1494 // See hhugboy src/memory/mbc/MbcUnlHitek.cpp for commentary on this return
1495 return;
1496 }
1497 _GBMBC5(gb, address, value);
1498}
1499
1500uint8_t _GBHitekRead(struct GBMemory* memory, uint16_t address) {
1501 switch (address >> 14) {
1502 case 0:
1503 default:
1504 return memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)];
1505 case 1:
1506 return _reorderBits(memory->romBank[address & (GB_SIZE_CART_BANK0 - 1)], _hitekDataReordering[memory->mbcState.bbd.dataSwapMode]);
1507 }
1508}
1509
1510void GBMBCRTCRead(struct GB* gb) {
1511 struct GBMBCRTCSaveBuffer rtcBuffer;
1512 struct VFile* vf = gb->sramVf;
1513 if (!vf) {
1514 return;
1515 }
1516 vf->seek(vf, gb->sramSize, SEEK_SET);
1517 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1518 return;
1519 }
1520
1521 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1522 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1523 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1524 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1525 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1526 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1527}
1528
1529void GBMBCRTCWrite(struct GB* gb) {
1530 struct VFile* vf = gb->sramVf;
1531 if (!vf) {
1532 return;
1533 }
1534
1535 uint8_t rtcRegs[5];
1536 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1537 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1538 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1539
1540 struct GBMBCRTCSaveBuffer rtcBuffer;
1541 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1542 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1543 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1544 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1545 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1546 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1547 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1548 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1549 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1550 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1551 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1552
1553 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1554 // Writing past the end of the file can invalidate the file mapping
1555 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1556 gb->memory.sram = NULL;
1557 }
1558 vf->seek(vf, gb->sramSize, SEEK_SET);
1559 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1560 if (!gb->memory.sram) {
1561 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1562 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1563 }
1564}