1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "core/log.h"
 12
 13#include "lr35902/lr35902.h"
 14
 15mLOG_DECLARE_CATEGORY(GB_MBC);
 16mLOG_DECLARE_CATEGORY(GB_MEM);
 17
 18struct GB;
 19
 20enum {
 21	GB_BASE_CART_BANK0 = 0x0000,
 22	GB_BASE_CART_BANK1 = 0x4000,
 23	GB_BASE_VRAM = 0x8000,
 24	GB_BASE_EXTERNAL_RAM = 0xA000,
 25	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 26	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 27	GB_BASE_OAM = 0xFE00,
 28	GB_BASE_UNUSABLE = 0xFEA0,
 29	GB_BASE_IO = 0xFF00,
 30	GB_BASE_HRAM = 0xFF80,
 31	GB_BASE_IE = 0xFFFF
 32};
 33
 34enum {
 35	GB_REGION_CART_BANK0 = 0x0,
 36	GB_REGION_CART_BANK1 = 0x4,
 37	GB_REGION_VRAM = 0x8,
 38	GB_REGION_EXTERNAL_RAM = 0xA,
 39	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 40	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 41	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 42	GB_REGION_OTHER = 0xF,
 43};
 44
 45enum {
 46	GB_SIZE_CART_BANK0 = 0x4000,
 47	GB_SIZE_VRAM = 0x2000,
 48	GB_SIZE_EXTERNAL_RAM = 0x2000,
 49	GB_SIZE_WORKING_RAM = 0x8000,
 50	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 51	GB_SIZE_OAM = 0xA0,
 52	GB_SIZE_IO = 0x80,
 53	GB_SIZE_HRAM = 0x7F,
 54};
 55
 56enum GBMemoryBankControllerType {
 57	GB_MBC_NONE = 0,
 58	GB_MBC1 = 1,
 59	GB_MBC2 = 2,
 60	GB_MBC3 = 3,
 61	GB_MBC5 = 5,
 62	GB_MBC6 = 6,
 63	GB_MBC7 = 7,
 64	GB_MMM01 = 0x10,
 65	GB_HuC1 = 0x11,
 66	GB_HuC3 = 0x12,
 67};
 68
 69struct GBMemory;
 70typedef void (*GBMemoryBankController)(struct GBMemory*, uint16_t address, uint8_t value);
 71
 72struct GBMemory {
 73	uint8_t* rom;
 74	uint8_t* romBank;
 75	enum GBMemoryBankControllerType mbcType;
 76	GBMemoryBankController mbc;
 77	int currentBank;
 78
 79	uint8_t* wram;
 80	uint8_t* wramBank;
 81
 82	bool sramAccess;
 83	uint8_t* sram;
 84	uint8_t* sramBank;
 85	int sramCurrentBank;
 86
 87	uint8_t io[GB_SIZE_IO];
 88	bool ime;
 89	uint8_t ie;
 90
 91	uint8_t hram[GB_SIZE_HRAM];
 92
 93	int32_t dmaNext;
 94	uint16_t dmaSource;
 95	uint16_t dmaDest;
 96	int dmaRemaining;
 97
 98	size_t romSize;
 99
100	bool rtcAccess;
101	int activeRtcReg;
102	int rtcLatched;
103	uint8_t rtcRegs[5];
104	struct mRTCSource* rtc;
105};
106
107void GBMemoryInit(struct GB* gb);
108void GBMemoryDeinit(struct GB* gb);
109
110void GBMemoryReset(struct GB* gb);
111
112uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
113void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
114
115int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles);
116void GBMemoryDMA(struct GB* gb, uint16_t base);
117
118uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
119void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
120
121uint16_t GBView16(struct LR35902Core* cpu, uint16_t address);
122uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
123
124void GBPatch16(struct LR35902Core* cpu, uint16_t address, int16_t value, int16_t* old);
125void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
126
127#endif