src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = cpu->cpsr.c;
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = cpu->cpsr.c;
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = cpu->cpsr.c;
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = cpu->cpsr.c;
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = cpu->cpsr.c;
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = cpu->cpsr.c;
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
189 cpu->cpsr.n = ARM_SIGN(d);
190 cpu->cpsr.z = !d;
191 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
192 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
193}
194
195ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
196 cpu->cpsr.n = ARM_SIGN(d);
197 cpu->cpsr.z = !d;
198 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
199 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
200}
201
202ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
203 cpu->cpsr.n = ARM_SIGN(d);
204 cpu->cpsr.z = !d; \
205 cpu->cpsr.c = cpu->shifterCarryOut; \
206}
207
208#define ARM_ADDITION_S(M, N, D) \
209 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
210 cpu->cpsr = cpu->spsr; \
211 _ARMReadCPSR(cpu); \
212 } else { \
213 _additionS(cpu, M, N, D); \
214 }
215
216#define ARM_SUBTRACTION_S(M, N, D) \
217 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
218 cpu->cpsr = cpu->spsr; \
219 _ARMReadCPSR(cpu); \
220 } else { \
221 _subtractionS(cpu, M, N, D); \
222 }
223
224#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
225 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
226 cpu->cpsr = cpu->spsr; \
227 _ARMReadCPSR(cpu); \
228 } else { \
229 cpu->cpsr.n = ARM_SIGN(D); \
230 cpu->cpsr.z = !(D); \
231 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
232 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
233 }
234
235#define ARM_NEUTRAL_S(M, N, D) \
236 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
237 cpu->cpsr = cpu->spsr; \
238 _ARMReadCPSR(cpu); \
239 } else { \
240 _neutralS(cpu, D); \
241 }
242
243#define ARM_NEUTRAL_HI_S(DLO, DHI) \
244 cpu->cpsr.n = ARM_SIGN(DHI); \
245 cpu->cpsr.z = !((DHI) | (DLO));
246
247#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
248#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
249#define ADDR_MODE_2_ADDRESS (address)
250#define ADDR_MODE_2_RN (cpu->gprs[rn])
251#define ADDR_MODE_2_RM (cpu->gprs[rm])
252#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
253#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
254#define ADDR_MODE_2_WRITEBACK(ADDR) \
255 cpu->gprs[rn] = ADDR; \
256 if (UNLIKELY(rn == ARM_PC)) { \
257 currentCycles += ARMWritePC(cpu); \
258 }
259
260#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
261#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
262#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
263#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
264
265#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
266#define ADDR_MODE_3_RN ADDR_MODE_2_RN
267#define ADDR_MODE_3_RM ADDR_MODE_2_RM
268#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
269#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
270#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
271#define ADDR_MODE_3_WRITEBACK_64(ADDR) ADDR_MODE_2_WRITEBACK(ADDR + 4)
272
273#define ADDR_MODE_4_WRITEBACK_LDM \
274 if (!((1 << rn) & rs)) { \
275 cpu->gprs[rn] = address; \
276 }
277
278#define ADDR_MODE_4_WRITEBACK_LDMv5 \
279 if (!((1 << rn) & rs) || !(((1 << rn) - 1) & rs)) { \
280 cpu->gprs[rn] = address; \
281 }
282
283#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
284
285#define ARM_LOAD_POST_BODY \
286 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
287 if (rd == ARM_PC) { \
288 currentCycles += ARMWritePC(cpu); \
289 }
290
291#define ARM_LOAD_POST_BODY_v5 \
292 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
293 if (rd == ARM_PC) { \
294 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001); \
295 cpu->gprs[ARM_PC] &= 0xFFFFFFFE; \
296 if (cpu->executionMode == MODE_THUMB) { \
297 currentCycles += ThumbWritePC(cpu); \
298 } else { \
299 currentCycles += ARMWritePC(cpu); \
300 } \
301 }
302
303#define ARM_STORE_POST_BODY \
304 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
305
306#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
307 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
308 int currentCycles = ARM_PREFETCH_CYCLES; \
309 BODY; \
310 cpu->cycles += currentCycles; \
311 }
312
313#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
314 DEFINE_INSTRUCTION_ARM(NAME, \
315 int rd = (opcode >> 12) & 0xF; \
316 int rn = (opcode >> 16) & 0xF; \
317 UNUSED(rn); \
318 SHIFTER(cpu, opcode); \
319 BODY; \
320 S_BODY; \
321 if (rd == ARM_PC) { \
322 if (cpu->executionMode == MODE_ARM) { \
323 currentCycles += ARMWritePC(cpu); \
324 } else { \
325 currentCycles += ThumbWritePC(cpu); \
326 } \
327 })
328
329#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
331 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
332 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
334 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
335 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
336 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
337 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
338 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
339 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
340
341#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
342 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
343 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
344 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
345 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
346 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
347
348#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
349 DEFINE_INSTRUCTION_ARM(NAME, \
350 int rd = (opcode >> 16) & 0xF; \
351 int rs = (opcode >> 8) & 0xF; \
352 int rm = opcode & 0xF; \
353 if (rd == ARM_PC) { \
354 return; \
355 } \
356 ARM_WAIT_MUL(cpu->gprs[rs]); \
357 BODY; \
358 S_BODY; \
359 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
360
361#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
362 DEFINE_INSTRUCTION_ARM(NAME, \
363 int rd = (opcode >> 12) & 0xF; \
364 int rdHi = (opcode >> 16) & 0xF; \
365 int rs = (opcode >> 8) & 0xF; \
366 int rm = opcode & 0xF; \
367 if (rdHi == ARM_PC || rd == ARM_PC) { \
368 return; \
369 } \
370 currentCycles += cpu->memory.stall(cpu, WAIT); \
371 BODY; \
372 S_BODY; \
373 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
374
375#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
376 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
377 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
378
379#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
380 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
381 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
382
383#define DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME, BODY) \
384 DEFINE_INSTRUCTION_ARM(NAME, \
385 int rd = (opcode >> 16) & 0xF; \
386 int rs = (opcode >> 8) & 0xF; \
387 int rn = (opcode >> 12) & 0xF; \
388 int rm = opcode & 0xF; \
389 UNUSED(rn); \
390 if (rd == ARM_PC) { \
391 return; \
392 } \
393 /* TODO: Timing */ \
394 int32_t x; \
395 int32_t y; \
396 BODY; \
397 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
398
399#define DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(NAME, BODY) \
400 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BB, \
401 x = ARM_SXT_16(cpu->gprs[rm]); \
402 y = ARM_SXT_16(cpu->gprs[rs]); \
403 BODY) \
404 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## BT, \
405 x = ARM_SXT_16(cpu->gprs[rm]); \
406 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
407 BODY) \
408 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TB, \
409 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
410 y = ARM_SXT_16(cpu->gprs[rs]); \
411 BODY) \
412 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## TT, \
413 x = ARM_SXT_16(cpu->gprs[rm] >> 16); \
414 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
415 BODY)
416
417#define DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(NAME, BODY) \
418 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## B, \
419 UNUSED(x); \
420 y = ARM_SXT_16(cpu->gprs[rs]); \
421 BODY) \
422 DEFINE_MULTIPLY_INSTRUCTION_3_ARM(NAME ## T, \
423 UNUSED(x); \
424 y = ARM_SXT_16(cpu->gprs[rs] >> 16); \
425 BODY) \
426
427#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
428 DEFINE_INSTRUCTION_ARM(NAME, \
429 uint32_t address; \
430 int rn = (opcode >> 16) & 0xF; \
431 int rd = (opcode >> 12) & 0xF; \
432 int rm = opcode & 0xF; \
433 UNUSED(rm); \
434 address = ADDRESS; \
435 WRITEBACK; \
436 BODY;)
437
438#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
439 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
440 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
441 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
442 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
443 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
444 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
445
446#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
447 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
448 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
449 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
450 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
451 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
456 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
457
458#define DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, WRITEBACK) \
459 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
460 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
461 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
462 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
463 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
465 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
466 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
467 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
468 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
469 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
470 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
471
472#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, ADDR_MODE_3_WRITEBACK)
473#define DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(NAME, BODY) DEFINE_LOAD_STORE_MODE_3_WRITEBACK_WIDTH_INSTRUCTION_ARM(NAME, BODY, ADDR_MODE_3_WRITEBACK_64)
474
475#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
476 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
477 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
478
479#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
480 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
481 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
482 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
483 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
484 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
485 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
486
487#define ARM_MS_PRE \
488 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
489 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
490
491#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
492
493#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
494 DEFINE_INSTRUCTION_ARM(NAME, \
495 int rn = (opcode >> 16) & 0xF; \
496 int rs = opcode & 0x0000FFFF; \
497 uint32_t address = cpu->gprs[rn]; \
498 S_PRE; \
499 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
500 S_POST; \
501 POST_BODY; \
502 WRITEBACK;)
503
504
505#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
506 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
507 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
508 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
509 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
510 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
511 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
512 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
513 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
514
515#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
516 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
517 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
518 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
519 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
520 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
521 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
522 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
523 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
524 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
525
526// Begin ALU definitions
527
528DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
529 int32_t n = cpu->gprs[rn];
530 cpu->gprs[rd] = n + cpu->shifterOperand;)
531
532DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
533 int32_t n = cpu->gprs[rn];
534 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
535
536DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
537 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
538
539DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
540 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
541
542DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
543 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
544
545DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
546 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
547
548DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
549 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
550
551DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
552 cpu->gprs[rd] = cpu->shifterOperand;)
553
554DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
555 cpu->gprs[rd] = ~cpu->shifterOperand;)
556
557DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
558 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
559
560DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
561 int32_t n = cpu->gprs[rn];
562 cpu->gprs[rd] = cpu->shifterOperand - n;)
563
564DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
565 int32_t n = cpu->gprs[rn];
566 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
567
568DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
569 int32_t n = cpu->gprs[rn];
570 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
571
572DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
573 int32_t n = cpu->gprs[rn];
574 cpu->gprs[rd] = n - cpu->shifterOperand;)
575
576DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
577 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
578
579DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
580 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
581
582// End ALU definitions
583
584// Begin multiply definitions
585
586DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
587DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
588
589DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
590 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
591 int32_t dm = cpu->gprs[rd];
592 int32_t dn = d;
593 cpu->gprs[rd] = dm + dn;
594 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
595 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
596
597DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMLA,
598 int32_t dn = cpu->gprs[rn]; \
599 int32_t d = x * y; \
600 cpu->gprs[rd] = d + dn; \
601 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
602
603DEFINE_MULTIPLY_INSTRUCTION_XY_ARM(SMUL, cpu->gprs[rd] = x * y;)
604
605DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMLAW,
606 int32_t dn = cpu->gprs[rn]; \
607 int32_t d = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16; \
608 cpu->gprs[rd] = d + dn; \
609 cpu->cpsr.q = cpu->cpsr.q || ARM_V_ADDITION(d, dn, cpu->gprs[rd]);)
610
611DEFINE_MULTIPLY_INSTRUCTION_WY_ARM(SMULW, cpu->gprs[rd] = (((int64_t) cpu->gprs[rm]) * ((int64_t) y)) >> 16;)
612
613DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
614 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
615 cpu->gprs[rd] = d;
616 cpu->gprs[rdHi] = d >> 32;,
617 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
618
619DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
620 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
621 int32_t dm = cpu->gprs[rd];
622 int32_t dn = d;
623 cpu->gprs[rd] = dm + dn;
624 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
625 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
626
627DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
628 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
629 cpu->gprs[rd] = d;
630 cpu->gprs[rdHi] = d >> 32;,
631 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
632
633// End multiply definitions
634
635// Begin load/store definitions
636
637DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
638DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRv5, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY_v5;)
639DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
640DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(LDRD, cpu->gprs[rd & ~1] = cpu->memory.load32(cpu, address, ¤tCycles); cpu->gprs[rd | 1] = cpu->memory.load32(cpu, address + 4, ¤tCycles); ARM_LOAD_POST_BODY;)
641DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
642DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
643DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
644DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
645DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
646DEFINE_LOAD_STORE_MODE_3_DOUBLE_INSTRUCTION_ARM(STRD, cpu->memory.store32(cpu, address, cpu->gprs[rd & ~1], ¤tCycles); cpu->memory.store32(cpu, address + 4, cpu->gprs[rd | 1], ¤tCycles); ARM_STORE_POST_BODY;)
647DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
648
649DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
650 enum PrivilegeMode priv = cpu->privilegeMode;
651 ARMSetPrivilegeMode(cpu, MODE_USER);
652 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
653 ARMSetPrivilegeMode(cpu, priv);
654 cpu->gprs[rd] = r;
655 ARM_LOAD_POST_BODY;)
656
657DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
658 enum PrivilegeMode priv = cpu->privilegeMode;
659 ARMSetPrivilegeMode(cpu, MODE_USER);
660 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
661 ARMSetPrivilegeMode(cpu, priv);
662 cpu->gprs[rd] = r;
663 ARM_LOAD_POST_BODY;)
664
665DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
666 enum PrivilegeMode priv = cpu->privilegeMode;
667 int32_t r = cpu->gprs[rd];
668 ARMSetPrivilegeMode(cpu, MODE_USER);
669 cpu->memory.store8(cpu, address, r, ¤tCycles);
670 ARMSetPrivilegeMode(cpu, priv);
671 ARM_STORE_POST_BODY;)
672
673DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
674 enum PrivilegeMode priv = cpu->privilegeMode;
675 int32_t r = cpu->gprs[rd];
676 ARMSetPrivilegeMode(cpu, MODE_USER);
677 cpu->memory.store32(cpu, address, r, ¤tCycles);
678 ARMSetPrivilegeMode(cpu, priv);
679 ARM_STORE_POST_BODY;)
680
681DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
682 load,
683 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
684 if (rs & 0x8000) {
685 currentCycles += ARMWritePC(cpu);
686 })
687
688DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
689 load,
690 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
691 if (rs & 0x8000) {
692 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
693 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
694 if (cpu->executionMode == MODE_THUMB) {
695 currentCycles += ThumbWritePC(cpu);
696 } else {
697 currentCycles += ARMWritePC(cpu);
698
699 }
700 })
701
702DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
703 store,
704 ARM_STORE_POST_BODY;)
705
706DEFINE_INSTRUCTION_ARM(SWP,
707 int rm = opcode & 0xF;
708 int rd = (opcode >> 12) & 0xF;
709 int rn = (opcode >> 16) & 0xF;
710 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
711 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
712 cpu->gprs[rd] = d;)
713
714DEFINE_INSTRUCTION_ARM(SWPB,
715 int rm = opcode & 0xF;
716 int rd = (opcode >> 12) & 0xF;
717 int rn = (opcode >> 16) & 0xF;
718 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
719 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
720 cpu->gprs[rd] = d;)
721
722// End load/store definitions
723
724// Begin branch definitions
725
726DEFINE_INSTRUCTION_ARM(B,
727 int32_t offset = opcode << 8;
728 offset >>= 6;
729 cpu->gprs[ARM_PC] += offset;
730 currentCycles += ARMWritePC(cpu);)
731
732DEFINE_INSTRUCTION_ARM(BL,
733 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
734 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
735 cpu->gprs[ARM_PC] += immediate >> 6;
736 currentCycles += ARMWritePC(cpu);)
737
738DEFINE_INSTRUCTION_ARM(BX,
739 int rm = opcode & 0x0000000F;
740 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
741 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
742 if (cpu->executionMode == MODE_THUMB) {
743 currentCycles += ThumbWritePC(cpu);
744 } else {
745 currentCycles += ARMWritePC(cpu);
746
747 })
748
749DEFINE_INSTRUCTION_ARM(BLX,
750 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
751 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
752 cpu->gprs[ARM_PC] += (immediate >> 6) + ((opcode >> 23) & 2);
753 _ARMSetMode(cpu, MODE_THUMB);
754 currentCycles += ThumbWritePC(cpu);)
755
756DEFINE_INSTRUCTION_ARM(BLX2,
757 int rm = opcode & 0x0000000F;
758 int address = cpu->gprs[rm];
759 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
760 _ARMSetMode(cpu, address & 0x00000001);
761 cpu->gprs[ARM_PC] = address & 0xFFFFFFFE;
762 if (cpu->executionMode == MODE_THUMB) {
763 currentCycles += ThumbWritePC(cpu);
764 } else {
765 currentCycles += ARMWritePC(cpu);
766 })
767
768// End branch definitions
769
770// Begin coprocessor definitions
771
772#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
773 DEFINE_INSTRUCTION_ARM(NAME, \
774 int op1 = (opcode >> 21) & 7; \
775 int op2 = (opcode >> 5) & 7; \
776 int rd = (opcode >> 12) & 0xF; \
777 int cp = (opcode >> 8) & 0xF; \
778 int crn = (opcode >> 16) & 0xF; \
779 int crm = opcode & 0xF; \
780 UNUSED(op1); \
781 UNUSED(op2); \
782 UNUSED(rd); \
783 UNUSED(crn); \
784 UNUSED(crm); \
785 BODY;)
786
787DEFINE_COPROCESSOR_INSTRUCTION(MRC,
788 if (cp == 15 && cpu->irqh.readCP15) {
789 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
790 } else {
791 ARM_STUB;
792 })
793
794DEFINE_COPROCESSOR_INSTRUCTION(MCR,
795 if (cp == 15 && cpu->irqh.writeCP15) {
796 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
797 } else {
798 ARM_STUB;
799 })
800
801DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
802DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
803DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
804
805// Begin miscellaneous definitions
806
807DEFINE_INSTRUCTION_ARM(CLZ,
808 int rm = opcode & 0xF;
809 int rd = (opcode >> 12) & 0xF;
810 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
811
812DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
813DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
814
815DEFINE_INSTRUCTION_ARM(MSR,
816 int c = opcode & 0x00010000;
817 int f = opcode & 0x00080000;
818 int32_t operand = cpu->gprs[opcode & 0x0000000F];
819 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
820 if (mask & PSR_USER_MASK) {
821 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
822 }
823 if (mask & PSR_STATE_MASK) {
824 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
825 }
826 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
827 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
828 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
829 }
830 _ARMReadCPSR(cpu);
831 if (cpu->executionMode == MODE_THUMB) {
832 cpu->prefetch[0] = 0x46C0; // nop
833 cpu->prefetch[1] &= 0xFFFF;
834 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
835 } else {
836 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
837 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
838 })
839
840DEFINE_INSTRUCTION_ARM(MSRR,
841 int c = opcode & 0x00010000;
842 int f = opcode & 0x00080000;
843 int32_t operand = cpu->gprs[opcode & 0x0000000F];
844 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
845 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
846 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
847
848DEFINE_INSTRUCTION_ARM(MRS, \
849 int rd = (opcode >> 12) & 0xF; \
850 cpu->gprs[rd] = cpu->cpsr.packed;)
851
852DEFINE_INSTRUCTION_ARM(MRSR, \
853 int rd = (opcode >> 12) & 0xF; \
854 cpu->gprs[rd] = cpu->spsr.packed;)
855
856DEFINE_INSTRUCTION_ARM(MSRI,
857 int c = opcode & 0x00010000;
858 int f = opcode & 0x00080000;
859 int rotate = (opcode & 0x00000F00) >> 7;
860 int32_t operand = ROR(opcode & 0x000000FF, rotate);
861 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
862 if (mask & PSR_USER_MASK) {
863 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
864 }
865 if (mask & PSR_STATE_MASK) {
866 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
867 }
868 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
869 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
870 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
871 }
872 _ARMReadCPSR(cpu);
873 if (cpu->executionMode == MODE_THUMB) {
874 cpu->prefetch[0] = 0x46C0; // nop
875 cpu->prefetch[1] &= 0xFFFF;
876 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
877 } else {
878 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
879 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
880 })
881
882DEFINE_INSTRUCTION_ARM(MSRRI,
883 int c = opcode & 0x00010000;
884 int f = opcode & 0x00080000;
885 int rotate = (opcode & 0x00000F00) >> 7;
886 int32_t operand = ROR(opcode & 0x000000FF, rotate);
887 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
888 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
889 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
890
891DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
892
893const ARMInstruction _armv4Table[0x1000] = {
894 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
895};
896
897const ARMInstruction _armv5Table[0x1000] = {
898 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
899};
900
901const ARMInstruction _armv4FTable[0x1000] = {
902 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 4)
903};
904
905const ARMInstruction _armv5FTable[0x1000] = {
906 DECLARE_ARM_F_EMITTER_BLOCK(_ARMInstruction, 5)
907};