src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba-util/math.h>
12
13#define PSR_USER_MASK 0xF0000000
14#define PSR_PRIV_MASK 0x000000CF
15#define PSR_STATE_MASK 0x00000020
16
17// Addressing mode 1
18static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
19 int rm = opcode & 0x0000000F;
20 if (opcode & 0x00000010) {
21 int rs = (opcode >> 8) & 0x0000000F;
22 ++cpu->cycles;
23 int shift = cpu->gprs[rs];
24 if (rs == ARM_PC) {
25 shift += 4;
26 }
27 shift &= 0xFF;
28 int32_t shiftVal = cpu->gprs[rm];
29 if (rm == ARM_PC) {
30 shiftVal += 4;
31 }
32 if (!shift) {
33 cpu->shifterOperand = shiftVal;
34 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
35 } else if (shift < 32) {
36 cpu->shifterOperand = shiftVal << shift;
37 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
38 } else if (shift == 32) {
39 cpu->shifterOperand = 0;
40 cpu->shifterCarryOut = shiftVal & 1;
41 } else {
42 cpu->shifterOperand = 0;
43 cpu->shifterCarryOut = 0;
44 }
45 } else {
46 int immediate = (opcode & 0x00000F80) >> 7;
47 if (!immediate) {
48 cpu->shifterOperand = cpu->gprs[rm];
49 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
50 } else {
51 cpu->shifterOperand = cpu->gprs[rm] << immediate;
52 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
53 }
54 }
55}
56
57static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
58 int rm = opcode & 0x0000000F;
59 if (opcode & 0x00000010) {
60 int rs = (opcode >> 8) & 0x0000000F;
61 ++cpu->cycles;
62 int shift = cpu->gprs[rs];
63 if (rs == ARM_PC) {
64 shift += 4;
65 }
66 shift &= 0xFF;
67 uint32_t shiftVal = cpu->gprs[rm];
68 if (rm == ARM_PC) {
69 shiftVal += 4;
70 }
71 if (!shift) {
72 cpu->shifterOperand = shiftVal;
73 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
74 } else if (shift < 32) {
75 cpu->shifterOperand = shiftVal >> shift;
76 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
77 } else if (shift == 32) {
78 cpu->shifterOperand = 0;
79 cpu->shifterCarryOut = shiftVal >> 31;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = 0;
83 }
84 } else {
85 int immediate = (opcode & 0x00000F80) >> 7;
86 if (immediate) {
87 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
88 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
89 } else {
90 cpu->shifterOperand = 0;
91 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
92 }
93 }
94}
95
96static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
97 int rm = opcode & 0x0000000F;
98 if (opcode & 0x00000010) {
99 int rs = (opcode >> 8) & 0x0000000F;
100 ++cpu->cycles;
101 int shift = cpu->gprs[rs];
102 if (rs == ARM_PC) {
103 shift += 4;
104 }
105 shift &= 0xFF;
106 int shiftVal = cpu->gprs[rm];
107 if (rm == ARM_PC) {
108 shiftVal += 4;
109 }
110 if (!shift) {
111 cpu->shifterOperand = shiftVal;
112 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
113 } else if (shift < 32) {
114 cpu->shifterOperand = shiftVal >> shift;
115 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
116 } else if (cpu->gprs[rm] >> 31) {
117 cpu->shifterOperand = 0xFFFFFFFF;
118 cpu->shifterCarryOut = 1;
119 } else {
120 cpu->shifterOperand = 0;
121 cpu->shifterCarryOut = 0;
122 }
123 } else {
124 int immediate = (opcode & 0x00000F80) >> 7;
125 if (immediate) {
126 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
127 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
128 } else {
129 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
130 cpu->shifterOperand = cpu->shifterCarryOut;
131 }
132 }
133}
134
135static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
136 int rm = opcode & 0x0000000F;
137 if (opcode & 0x00000010) {
138 int rs = (opcode >> 8) & 0x0000000F;
139 ++cpu->cycles;
140 int shift = cpu->gprs[rs];
141 if (rs == ARM_PC) {
142 shift += 4;
143 }
144 shift &= 0xFF;
145 int shiftVal = cpu->gprs[rm];
146 if (rm == ARM_PC) {
147 shiftVal += 4;
148 }
149 int rotate = shift & 0x1F;
150 if (!shift) {
151 cpu->shifterOperand = shiftVal;
152 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
153 } else if (rotate) {
154 cpu->shifterOperand = ROR(shiftVal, rotate);
155 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
156 } else {
157 cpu->shifterOperand = shiftVal;
158 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
159 }
160 } else {
161 int immediate = (opcode & 0x00000F80) >> 7;
162 if (immediate) {
163 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
164 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
165 } else {
166 // RRX
167 cpu->shifterOperand = (ARMPSRGetC(cpu->cpsr) << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
168 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
169 }
170 }
171}
172
173static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
174 int rotate = (opcode & 0x00000F00) >> 7;
175 int immediate = opcode & 0x000000FF;
176 if (!rotate) {
177 cpu->shifterOperand = immediate;
178 cpu->shifterCarryOut = ARMPSRGetC(cpu->cpsr);
179 } else {
180 cpu->shifterOperand = ROR(immediate, rotate);
181 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
182 }
183}
184
185// Instruction definitions
186// Beware pre-processor antics
187
188#define ARM_ADDITION_S(M, N, D) \
189 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
190 cpu->cpsr = cpu->spsr; \
191 _ARMReadCPSR(cpu); \
192 } else { \
193 ARMPSR cpsr = 0; \
194 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
195 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
196 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM(M, N, D)); \
197 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
198 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
199 }
200
201#define ARM_ADDITION_CARRY_S(M, N, D, C) \
202 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
203 cpu->cpsr = cpu->spsr; \
204 _ARMReadCPSR(cpu); \
205 } else { \
206 ARMPSR cpsr = 0; \
207 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
208 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
209 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM_CARRY(M, N, D, C)); \
210 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
211 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
212 }
213
214#define ARM_SUBTRACTION_S(M, N, D) \
215 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
216 cpu->cpsr = cpu->spsr; \
217 _ARMReadCPSR(cpu); \
218 } else { \
219 ARMPSR cpsr = 0; \
220 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
221 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
222 cpsr = ARMPSROrUnsafeC(cpsr, ARM_BORROW_FROM(M, N, D)); \
223 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_SUBTRACTION(M, N, D)); \
224 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
225 }
226
227#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
228 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
229 cpu->cpsr = cpu->spsr; \
230 _ARMReadCPSR(cpu); \
231 } else { \
232 ARMPSR cpsr = 0; \
233 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
234 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
235 cpsr = ARMPSROrUnsafeC(cpsr, ARM_BORROW_FROM_CARRY(M, N, D, C)); \
236 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_SUBTRACTION(M, N, D)); \
237 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
238 }
239
240#define ARM_NEUTRAL_S(M, N, D) \
241 if (rd == ARM_PC && _ARMModeHasSPSR(ARMPSRGetPriv(cpu->cpsr))) { \
242 cpu->cpsr = cpu->spsr; \
243 _ARMReadCPSR(cpu); \
244 } else { \
245 ARMPSR cpsr = 0; \
246 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
247 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
248 cpsr = ARMPSROrUnsafeC(cpsr, cpu->shifterCarryOut); \
249 cpu->cpsr = (cpu->cpsr & (0x1FFFFFFF)) | cpsr; \
250 }
251
252#define ARM_NEUTRAL_HI_S(DLO, DHI) \
253 { \
254 ARMPSR cpsr = 0; \
255 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(DHI)); \
256 cpsr = ARMPSROrUnsafeZ(cpsr, !((DHI) | (DLO))); \
257 cpu->cpsr = (cpu->cpsr & (0x3FFFFFFF)) | cpsr; \
258 }
259
260#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
261#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
262#define ADDR_MODE_2_ADDRESS (address)
263#define ADDR_MODE_2_RN (cpu->gprs[rn])
264#define ADDR_MODE_2_RM (cpu->gprs[rm])
265#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
266#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
267#define ADDR_MODE_2_WRITEBACK(ADDR) \
268 cpu->gprs[rn] = ADDR; \
269 if (UNLIKELY(rn == ARM_PC)) { \
270 ARM_WRITE_PC; \
271 }
272
273#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
274#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
275#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
276#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (ARMPSRGetC(cpu->cpsr) << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
277
278#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
279#define ADDR_MODE_3_RN ADDR_MODE_2_RN
280#define ADDR_MODE_3_RM ADDR_MODE_2_RM
281#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
282#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
283#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
284
285#define ADDR_MODE_4_WRITEBACK_LDM \
286 if (!((1 << rn) & rs)) { \
287 cpu->gprs[rn] = address; \
288 }
289
290#define ADDR_MODE_4_WRITEBACK_LDMv5 ADDR_MODE_4_WRITEBACK_LDM
291
292#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
293
294#define ARM_LOAD_POST_BODY \
295 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
296 if (rd == ARM_PC) { \
297 ARM_WRITE_PC; \
298 }
299
300#define ARM_STORE_POST_BODY \
301 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
302
303#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
304 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
305 int currentCycles = ARM_PREFETCH_CYCLES; \
306 BODY; \
307 cpu->cycles += currentCycles; \
308 }
309
310#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
311 DEFINE_INSTRUCTION_ARM(NAME, \
312 int rd = (opcode >> 12) & 0xF; \
313 int rn = (opcode >> 16) & 0xF; \
314 UNUSED(rn); \
315 SHIFTER(cpu, opcode); \
316 BODY; \
317 S_BODY; \
318 if (rd == ARM_PC) { \
319 if (cpu->executionMode == MODE_ARM) { \
320 ARM_WRITE_PC; \
321 } else { \
322 THUMB_WRITE_PC; \
323 } \
324 })
325
326#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
328 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
329 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
331 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
332 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
334 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
335 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
336 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
337
338#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
339 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
340 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
341 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
342 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
343 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
344
345#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
346 DEFINE_INSTRUCTION_ARM(NAME, \
347 int rd = (opcode >> 16) & 0xF; \
348 int rs = (opcode >> 8) & 0xF; \
349 int rm = opcode & 0xF; \
350 if (rd == ARM_PC) { \
351 return; \
352 } \
353 ARM_WAIT_MUL(cpu->gprs[rs]); \
354 BODY; \
355 S_BODY; \
356 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
357
358#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
359 DEFINE_INSTRUCTION_ARM(NAME, \
360 int rd = (opcode >> 12) & 0xF; \
361 int rdHi = (opcode >> 16) & 0xF; \
362 int rs = (opcode >> 8) & 0xF; \
363 int rm = opcode & 0xF; \
364 if (rdHi == ARM_PC || rd == ARM_PC) { \
365 return; \
366 } \
367 currentCycles += cpu->memory.stall(cpu, WAIT); \
368 BODY; \
369 S_BODY; \
370 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
371
372#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
373 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
374 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
375
376#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
377 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
378 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
379
380#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
381 DEFINE_INSTRUCTION_ARM(NAME, \
382 uint32_t address; \
383 int rn = (opcode >> 16) & 0xF; \
384 int rd = (opcode >> 12) & 0xF; \
385 int rm = opcode & 0xF; \
386 UNUSED(rm); \
387 address = ADDRESS; \
388 WRITEBACK; \
389 BODY;)
390
391#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
398
399#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
408 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
409 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
410
411#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
412 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
413 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
414 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
416 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
417 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
420 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
421 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
422 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
423 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
424
425#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
426 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
427 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
428
429#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
430 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
431 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
432 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
433 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
434 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
435 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
436
437#define ARM_MS_PRE \
438 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
439 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
440
441#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
442
443#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
444 DEFINE_INSTRUCTION_ARM(NAME, \
445 int rn = (opcode >> 16) & 0xF; \
446 int rs = opcode & 0x0000FFFF; \
447 uint32_t address = cpu->gprs[rn]; \
448 S_PRE; \
449 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
450 S_POST; \
451 POST_BODY; \
452 WRITEBACK;)
453
454
455#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
458 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
459 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
460 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
461 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
462 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
463 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
464
465#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
466 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(NAME, LS, POST_BODY) \
467 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
468 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DA, POST_BODY) \
469 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
470 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, DB, POST_BODY) \
471 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
472 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IA, POST_BODY) \
473 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY) \
474 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE, ARM_MS_POST, IB, POST_BODY)
475
476// Begin ALU definitions
477
478DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
479 int32_t n = cpu->gprs[rn];
480 cpu->gprs[rd] = n + cpu->shifterOperand;)
481
482DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], ARMPSRGetC(cpu->cpsr)),
483 int32_t n = cpu->gprs[rn];
484 cpu->gprs[rd] = n + cpu->shifterOperand + ARMPSRGetC(cpu->cpsr);)
485
486DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
487 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
488
489DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
490 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
491
492DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
493 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
494
495DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
496 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
497
498DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
499 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
500
501DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
502 cpu->gprs[rd] = cpu->shifterOperand;)
503
504DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
505 cpu->gprs[rd] = ~cpu->shifterOperand;)
506
507DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
508 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
509
510DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
511 int32_t n = cpu->gprs[rn];
512 cpu->gprs[rd] = cpu->shifterOperand - n;)
513
514DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !ARMPSRIsC(cpu->cpsr)),
515 int32_t n = cpu->gprs[rn];
516 cpu->gprs[rd] = cpu->shifterOperand - n - !ARMPSRIsC(cpu->cpsr);)
517
518DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !ARMPSRIsC(cpu->cpsr)),
519 int32_t n = cpu->gprs[rn];
520 cpu->gprs[rd] = n - cpu->shifterOperand - !ARMPSRIsC(cpu->cpsr);)
521
522DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
523 int32_t n = cpu->gprs[rn];
524 cpu->gprs[rd] = n - cpu->shifterOperand;)
525
526DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
527 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
528
529DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
530 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
531
532// End ALU definitions
533
534// Begin multiply definitions
535
536DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
537DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
538
539DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
540 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
541 int32_t dm = cpu->gprs[rd];
542 int32_t dn = d;
543 cpu->gprs[rd] = dm + dn;
544 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
545 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
546
547DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
548 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
549 cpu->gprs[rd] = d;
550 cpu->gprs[rdHi] = d >> 32;,
551 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
552
553DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
554 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
555 int32_t dm = cpu->gprs[rd];
556 int32_t dn = d;
557 cpu->gprs[rd] = dm + dn;
558 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
559 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
560
561DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
562 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
563 cpu->gprs[rd] = d;
564 cpu->gprs[rdHi] = d >> 32;,
565 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
566
567// End multiply definitions
568
569// Begin load/store definitions
570
571DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
572DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
573DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
574DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
575DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
576DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
577DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
578DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
579
580DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
581 enum PrivilegeMode priv = cpu->privilegeMode;
582 ARMSetPrivilegeMode(cpu, MODE_USER);
583 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
584 ARMSetPrivilegeMode(cpu, priv);
585 cpu->gprs[rd] = r;
586 ARM_LOAD_POST_BODY;)
587
588DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
589 enum PrivilegeMode priv = cpu->privilegeMode;
590 ARMSetPrivilegeMode(cpu, MODE_USER);
591 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
592 ARMSetPrivilegeMode(cpu, priv);
593 cpu->gprs[rd] = r;
594 ARM_LOAD_POST_BODY;)
595
596DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
597 enum PrivilegeMode priv = cpu->privilegeMode;
598 int32_t r = cpu->gprs[rd];
599 ARMSetPrivilegeMode(cpu, MODE_USER);
600 cpu->memory.store8(cpu, address, r, ¤tCycles);
601 ARMSetPrivilegeMode(cpu, priv);
602 ARM_STORE_POST_BODY;)
603
604DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
605 enum PrivilegeMode priv = cpu->privilegeMode;
606 int32_t r = cpu->gprs[rd];
607 ARMSetPrivilegeMode(cpu, MODE_USER);
608 cpu->memory.store32(cpu, address, r, ¤tCycles);
609 ARMSetPrivilegeMode(cpu, priv);
610 ARM_STORE_POST_BODY;)
611
612DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
613 load,
614 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
615 if (rs & 0x8000) {
616 ARM_WRITE_PC;
617 })
618
619DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM_NO_S(LDMv5,
620 load,
621 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
622 if (rs & 0x8000) {
623 _ARMSetMode(cpu, cpu->gprs[ARM_PC] & 0x00000001);
624 cpu->gprs[ARM_PC] &= 0xFFFFFFFE;
625 if (cpu->executionMode == MODE_THUMB) {
626 THUMB_WRITE_PC;
627 } else {
628 ARM_WRITE_PC;
629
630 }
631 })
632
633DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
634 store,
635 ARM_STORE_POST_BODY;)
636
637DEFINE_INSTRUCTION_ARM(SWP,
638 int rm = opcode & 0xF;
639 int rd = (opcode >> 12) & 0xF;
640 int rn = (opcode >> 16) & 0xF;
641 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
642 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
643 cpu->gprs[rd] = d;)
644
645DEFINE_INSTRUCTION_ARM(SWPB,
646 int rm = opcode & 0xF;
647 int rd = (opcode >> 12) & 0xF;
648 int rn = (opcode >> 16) & 0xF;
649 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
650 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
651 cpu->gprs[rd] = d;)
652
653// End load/store definitions
654
655// Begin branch definitions
656
657DEFINE_INSTRUCTION_ARM(B,
658 int32_t offset = opcode << 8;
659 offset >>= 6;
660 cpu->gprs[ARM_PC] += offset;
661 ARM_WRITE_PC;)
662
663DEFINE_INSTRUCTION_ARM(BL,
664 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
665 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
666 cpu->gprs[ARM_PC] += immediate >> 6;
667 ARM_WRITE_PC;)
668
669DEFINE_INSTRUCTION_ARM(BX,
670 int rm = opcode & 0x0000000F;
671 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
672 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
673 if (cpu->executionMode == MODE_THUMB) {
674 THUMB_WRITE_PC;
675 } else {
676 ARM_WRITE_PC;
677
678 })
679DEFINE_INSTRUCTION_ARM(BLX2,
680 int rm = opcode & 0x0000000F;
681 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
682 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
683 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
684 if (cpu->executionMode == MODE_THUMB) {
685 THUMB_WRITE_PC;
686 } else {
687 ARM_WRITE_PC;
688 })
689
690// End branch definitions
691
692// Begin coprocessor definitions
693
694#define DEFINE_COPROCESSOR_INSTRUCTION(NAME, BODY) \
695 DEFINE_INSTRUCTION_ARM(NAME, \
696 int op1 = (opcode >> 21) & 7; \
697 int op2 = (opcode >> 5) & 7; \
698 int rd = (opcode >> 12) & 0xF; \
699 int cp = (opcode >> 8) & 0xF; \
700 int crn = (opcode >> 16) & 0xF; \
701 int crm = opcode & 0xF; \
702 UNUSED(op1); \
703 UNUSED(op2); \
704 UNUSED(rd); \
705 UNUSED(crn); \
706 UNUSED(crm); \
707 BODY;)
708
709DEFINE_COPROCESSOR_INSTRUCTION(MRC,
710 if (cp == 15 && cpu->irqh.readCP15) {
711 cpu->gprs[rd] = cpu->irqh.readCP15(cpu, crn, crm, op1, op2);
712 } else {
713 ARM_STUB;
714 })
715
716DEFINE_COPROCESSOR_INSTRUCTION(MCR,
717 if (cp == 15 && cpu->irqh.writeCP15) {
718 cpu->irqh.writeCP15(cpu, crn, crm, op1, op2, cpu->gprs[rd]);
719 } else {
720 ARM_STUB;
721 })
722
723DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
724DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
725DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
726
727// Begin miscellaneous definitions
728
729DEFINE_INSTRUCTION_ARM(CLZ,
730 int rm = opcode & 0xF;
731 int rd = (opcode >> 12) & 0xF;
732 cpu->gprs[rd] = clz32(cpu->gprs[rm]);)
733
734DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
735DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
736
737DEFINE_INSTRUCTION_ARM(MSR,
738 int c = opcode & 0x00010000;
739 int f = opcode & 0x00080000;
740 int32_t operand = cpu->gprs[opcode & 0x0000000F];
741 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
742 if (mask & PSR_USER_MASK) {
743 cpu->cpsr = (cpu->cpsr & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
744 }
745 if (mask & PSR_STATE_MASK) {
746 cpu->cpsr = (cpu->cpsr & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
747 }
748 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
749 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
750 cpu->cpsr = (cpu->cpsr & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
751 }
752 _ARMReadCPSR(cpu);
753 if (cpu->executionMode == MODE_THUMB) {
754 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
755 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
756 } else {
757 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
758 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
759 })
760
761DEFINE_INSTRUCTION_ARM(MSRR,
762 int c = opcode & 0x00010000;
763 int f = opcode & 0x00080000;
764 int32_t operand = cpu->gprs[opcode & 0x0000000F];
765 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
766 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
767 cpu->spsr = (cpu->spsr & ~mask) | (operand & mask) | 0x00000010;)
768
769DEFINE_INSTRUCTION_ARM(MRS, \
770 int rd = (opcode >> 12) & 0xF; \
771 cpu->gprs[rd] = cpu->cpsr;)
772
773DEFINE_INSTRUCTION_ARM(MRSR, \
774 int rd = (opcode >> 12) & 0xF; \
775 cpu->gprs[rd] = cpu->spsr;)
776
777DEFINE_INSTRUCTION_ARM(MSRI,
778 int c = opcode & 0x00010000;
779 int f = opcode & 0x00080000;
780 int rotate = (opcode & 0x00000F00) >> 7;
781 int32_t operand = ROR(opcode & 0x000000FF, rotate);
782 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
783 if (mask & PSR_USER_MASK) {
784 cpu->cpsr = (cpu->cpsr & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
785 }
786 if (mask & PSR_STATE_MASK) {
787 cpu->cpsr = (cpu->cpsr & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
788 }
789 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
790 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
791 cpu->cpsr = (cpu->cpsr & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
792 }
793 _ARMReadCPSR(cpu);
794 if (cpu->executionMode == MODE_THUMB) {
795 LOAD_16(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_THUMB) & cpu->memory.activeMask, cpu->memory.activeRegion);
796 LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
797 } else {
798 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
799 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
800 })
801
802DEFINE_INSTRUCTION_ARM(MSRRI,
803 int c = opcode & 0x00010000;
804 int f = opcode & 0x00080000;
805 int rotate = (opcode & 0x00000F00) >> 7;
806 int32_t operand = ROR(opcode & 0x000000FF, rotate);
807 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
808 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
809 cpu->spsr = (cpu->spsr & ~mask) | (operand & mask) | 0x00000010;)
810
811DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
812
813const ARMInstruction _armv4Table[0x1000] = {
814 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 4)
815};
816
817const ARMInstruction _armv5Table[0x1000] = {
818 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction, 5)
819};