src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "ds.h"
7
8#include "arm/decoder.h"
9#include "arm/debugger/debugger.h"
10#include "arm/isa-inlines.h"
11#include "ds/bios.h"
12
13#include "util/crc32.h"
14#include "util/memory.h"
15#include "util/math.h"
16#include "util/vfs.h"
17
18mLOG_DEFINE_CATEGORY(DS, "DS");
19
20const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
21const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
22const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
23
24static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
25static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
26
27enum {
28 DS7_SP_BASE = 0x380FD80,
29 DS7_SP_BASE_IRQ = 0x380FF80,
30 DS7_SP_BASE_SVC = 0x380FFC0,
31
32 DS9_SP_BASE = 0x3002F7C,
33 DS9_SP_BASE_IRQ = 0x3003F80,
34 DS9_SP_BASE_SVC = 0x3003FC0,
35};
36
37static void DSInit(void* cpu, struct mCPUComponent* component);
38
39static void DS7Reset(struct ARMCore* cpu);
40static void DS7TestIRQ(struct ARMCore* cpu);
41static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
42
43static void DS9Reset(struct ARMCore* cpu);
44static void DS9TestIRQ(struct ARMCore* cpu);
45static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
46static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
47
48static void DSProcessEvents(struct ARMCore* cpu);
49static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
50static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
51static void DSBreakpoint(struct ARMCore* cpu, int immediate);
52
53void DSCreate(struct DS* ds) {
54 ds->d.id = DS_COMPONENT_MAGIC;
55 ds->d.init = DSInit;
56 ds->d.deinit = NULL;
57 ds->arm7 = NULL;
58 ds->arm9 = NULL;
59}
60
61static void DSInit(void* cpu, struct mCPUComponent* component) {
62 struct DS* ds = (struct DS*) component;
63 struct ARMCore* core = cpu;
64 if (!ds->arm7) {
65 // The ARM7 must get initialized first
66 ds->arm7 = core;
67 ds->debugger = 0;
68 ds->sync = 0;
69 return;
70 }
71 ds->arm9 = cpu;
72
73 ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
74
75 DS7InterruptHandlerInit(&ds->arm7->irqh);
76 DS9InterruptHandlerInit(&ds->arm9->irqh);
77 DSMemoryInit(ds);
78
79 ds->video.p = ds;
80
81 ds->springIRQ7 = 0;
82 ds->springIRQ9 = 0;
83 ds->timersEnabled7 = 0;
84 ds->timersEnabled9 = 0;
85 memset(ds->timers7, 0, sizeof(ds->timers7));
86 memset(ds->timers9, 0, sizeof(ds->timers9));
87 ds->keySource = NULL;
88 ds->rtcSource = NULL;
89 ds->rumble = NULL;
90
91 ds->romVf = NULL;
92
93 ds->keyCallback = NULL;
94}
95
96void DSUnloadROM(struct DS* ds) {
97 if (ds->romVf) {
98 ds->romVf->close(ds->romVf);
99 ds->romVf = NULL;
100 }
101}
102
103void DSDestroy(struct DS* ds) {
104 DSUnloadROM(ds);
105 DSMemoryDeinit(ds);
106}
107
108void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
109 irqh->reset = DS7Reset;
110 irqh->processEvents = DSProcessEvents;
111 irqh->swi16 = DS7Swi16;
112 irqh->swi32 = DS7Swi32;
113 irqh->hitIllegal = DSIllegal;
114 irqh->readCPSR = DS7TestIRQ;
115 irqh->writeCP15 = NULL;
116 irqh->hitStub = DSHitStub;
117 irqh->bkpt16 = DSBreakpoint;
118 irqh->bkpt32 = DSBreakpoint;
119}
120
121void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
122 irqh->reset = DS9Reset;
123 irqh->processEvents = DSProcessEvents;
124 irqh->swi16 = NULL;
125 irqh->swi32 = NULL;
126 irqh->hitIllegal = DSIllegal;
127 irqh->readCPSR = DS9TestIRQ;
128 irqh->writeCP15 = DS9WriteCP15;
129 irqh->hitStub = DSHitStub;
130 irqh->bkpt16 = DSBreakpoint;
131 irqh->bkpt32 = DSBreakpoint;
132}
133
134void DS7Reset(struct ARMCore* cpu) {
135 ARMSetPrivilegeMode(cpu, MODE_IRQ);
136 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
137 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
138 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
139 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
140 cpu->gprs[ARM_SP] = DS7_SP_BASE;
141
142 struct DS* ds = (struct DS*) cpu->master;
143 DSMemoryReset(ds);
144 DS7IOInit(ds);
145
146 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
147 if (header) {
148 // TODO: Error check
149 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
150 uint32_t base = header->arm7Base - DS_BASE_RAM;
151 uint32_t* basePointer = &ds->memory.ram[base >> 2];
152 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
153 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
154 }
155 cpu->gprs[12] = header->arm7Entry;
156 cpu->gprs[ARM_LR] = header->arm7Entry;
157 cpu->gprs[ARM_PC] = header->arm7Entry;
158 int currentCycles = 0;
159 ARM_WRITE_PC;
160
161 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
162 }
163}
164
165void DS9Reset(struct ARMCore* cpu) {
166 ARMSetPrivilegeMode(cpu, MODE_IRQ);
167 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
168 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
169 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
170 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
171 cpu->gprs[ARM_SP] = DS9_SP_BASE;
172
173 struct DS* ds = (struct DS*) cpu->master;
174 DS9IOInit(ds);
175
176 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
177 if (header) {
178 // TODO: Error check
179 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
180 uint32_t base = header->arm9Base - DS_BASE_RAM;
181 uint32_t* basePointer = &ds->memory.ram[base >> 2];
182 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
183 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
184 }
185 cpu->gprs[12] = header->arm9Entry;
186 cpu->gprs[ARM_LR] = header->arm9Entry;
187 cpu->gprs[ARM_PC] = header->arm9Entry;
188 int currentCycles = 0;
189 ARM_WRITE_PC;
190
191 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
192 }
193}
194
195static void DSProcessEvents(struct ARMCore* cpu) {
196 struct DS* ds = (struct DS*) cpu->master;
197
198 if (ds->springIRQ7) {
199 ARMRaiseIRQ(cpu);
200 ds->springIRQ7 = 0;
201 }
202
203 int32_t cycles = cpu->nextEvent;
204 int32_t nextEvent = INT_MAX;
205 int32_t testEvent;
206#ifndef NDEBUG
207 if (cycles < 0) {
208 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
209 }
210#endif
211
212 testEvent = DSTimersProcessEvents(ds, cycles);
213 if (testEvent < nextEvent) {
214 nextEvent = testEvent;
215 }
216
217 cpu->cycles -= cycles;
218 cpu->nextEvent = nextEvent;
219
220 if (cpu->halted) {
221 cpu->cycles = cpu->nextEvent;
222 }
223}
224
225void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
226 ds->debugger = (struct ARMDebugger*) debugger->platform;
227 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
228 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
229 ARMHotplugAttach(ds->arm7, CPU_COMPONENT_DEBUGGER);
230 ARMHotplugAttach(ds->arm9, CPU_COMPONENT_DEBUGGER);
231}
232
233void DSDetachDebugger(struct DS* ds) {
234 ds->debugger = NULL;
235 ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
236 ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
237 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
238 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
239}
240
241bool DSLoadROM(struct DS* ds, struct VFile* vf) {
242 DSUnloadROM(ds);
243 ds->romVf = vf;
244 // TODO: error check
245 return true;
246}
247
248bool DSIsROM(struct VFile* vf) {
249 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
250 return false;
251 }
252 uint8_t signature[sizeof(DS_ROM_MAGIC)];
253 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
254 return false;
255 }
256 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
257}
258
259bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
260 size_t size = vf->size(vf);
261 void* data = NULL;
262 uint32_t crc;
263 if (size == DS7_SIZE_BIOS) {
264 data = vf->map(vf, size, MAP_READ);
265 } else if (size == 0x1000) {
266 data = vf->map(vf, size, MAP_READ);
267 }
268 if (!data) {
269 return false;
270 }
271 crc = doCrc32(data, size);
272 if (crc == DS7_BIOS_CHECKSUM) {
273 ds->bios7Vf = vf;
274 ds->memory.bios7 = data;
275 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
276 } else if (crc == DS9_BIOS_CHECKSUM) {
277 ds->bios9Vf = vf;
278 ds->memory.bios9 = data;
279 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
280 } else {
281 mLOG(DS, WARN, "BIOS checksum incorrect");
282 vf->unmap(vf, data, size);
283 return false;
284 }
285 return true;
286}
287
288void DSGetGameCode(struct DS* ds, char* out) {
289 memset(out, 0, 8);
290 if (!ds->romVf) {
291 return;
292 }
293
294 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
295 memcpy(out, "NTR-", 4);
296 memcpy(&out[4], &cart->id, 4);
297 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
298}
299
300void DSGetGameTitle(struct DS* ds, char* out) {
301 memset(out, 0, 12);
302 if (!ds->romVf) {
303 return;
304 }
305
306 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
307 memcpy(out, &cart->title, 4);
308 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
309}
310
311void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
312 struct DS* ds = (struct DS*) cpu->master;
313 if (ds->debugger) {
314 struct mDebuggerEntryInfo info = {
315 .address = _ARMPCAddress(cpu),
316 .opcode = opcode
317 };
318 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
319 }
320 // TODO: More sensible category?
321 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
322}
323
324void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
325 struct DS* ds = (struct DS*) cpu->master;
326 if (ds->debugger) {
327 struct mDebuggerEntryInfo info = {
328 .address = _ARMPCAddress(cpu),
329 .opcode = opcode
330 };
331 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
332 } else {
333 ARMRaiseUndefined(cpu);
334 }
335}
336
337void DSBreakpoint(struct ARMCore* cpu, int immediate) {
338 struct DS* ds = (struct DS*) cpu->master;
339 if (immediate >= CPU_COMPONENT_MAX) {
340 return;
341 }
342 switch (immediate) {
343 case CPU_COMPONENT_DEBUGGER:
344 if (ds->debugger) {
345 struct mDebuggerEntryInfo info = {
346 .address = _ARMPCAddress(cpu)
347 };
348 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
349 }
350 break;
351 default:
352 break;
353 }
354}
355
356void DS7TestIRQ(struct ARMCore* cpu) {
357 struct DS* ds = (struct DS*) cpu->master;
358 if (0) {
359 ds->springIRQ7 = 1;
360 cpu->nextEvent = cpu->cycles;
361 }
362}
363
364void DS9TestIRQ(struct ARMCore* cpu) {
365 struct DS* ds = (struct DS*) cpu->master;
366 if (0) {
367 ds->springIRQ9 = 1;
368 cpu->nextEvent = cpu->cycles;
369 }
370}
371
372static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
373 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
374}
375
376static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
377 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
378 switch (opcode2) {
379 case 0:
380 cpu->cp15.r2.d = value;
381 break;
382 case 1:
383 cpu->cp15.r2.i = value;
384 break;
385 default:
386 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
387 break;
388 }
389}
390
391static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
392 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
393 switch (opcode2) {
394 case 0:
395 cpu->cp15.r3.d = value;
396 break;
397 default:
398 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
399 break;
400 }
401}
402
403static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
404 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
405}
406
407static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
408 cpu->cp15.r6.region[crm] = value;
409 uint32_t base = ARMProtectionGetBase(value) << 12;
410 uint32_t size = 2 << ARMProtectionGetSize(value);
411 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
412}
413
414static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
415 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
416}
417
418static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
419 uint32_t base = ARMTCMControlGetBase(value) << 12;
420 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
421 mLOG(DS, STUB, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
422 switch (opcode2) {
423 case 0:
424 cpu->cp15.r9.d = value;
425 break;
426 case 1:
427 cpu->cp15.r9.i = value;
428 break;
429 default:
430 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
431 break;
432 }
433}
434
435void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
436 switch (crn) {
437 default:
438 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
439 break;
440 case 0:
441 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
442 ARMRaiseUndefined(cpu);
443 break;
444 case 1:
445 _writeSysControl(cpu, crm, opcode2, value);
446 break;
447 case 2:
448 _writeCacheControl(cpu, crm, opcode2, value);
449 break;
450 case 3:
451 _writeWriteBufferControl(cpu, crm, opcode2, value);
452 break;
453 case 5:
454 _writeAccessControl(cpu, crm, opcode2, value);
455 break;
456 case 6:
457 _writeRegionConfiguration(cpu, crm, opcode2, value);
458 break;
459 case 7:
460 _writeCache(cpu, crm, opcode2, value);
461 break;
462 case 9:
463 _writeTCMControl(cpu, crm, opcode2, value);
464 break;
465 }
466}
467
468void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
469 if (io[DS7_REG_IME >> 1] && (value & io[DS7_REG_IF_LO >> 1] || (value >> 16) & io[DS7_REG_IF_HI >> 1])) {
470 ARMRaiseIRQ(cpu);
471 }
472}
473void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
474 if (value && (io[DS7_REG_IE_LO >> 1] & io[DS7_REG_IF_LO >> 1] || io[DS7_REG_IE_HI >> 1] & io[DS7_REG_IF_HI >> 1])) {
475 ARMRaiseIRQ(cpu);
476 }
477}
478
479void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
480 if (irq < 16) {
481 io[DS7_REG_IF_LO >> 1] |= 1 << irq;
482 } else {
483 io[DS7_REG_IF_HI >> 1] |= 1 << (irq - 16);
484 }
485 cpu->halted = 0;
486
487 if (!io[DS7_REG_IME >> 1]) {
488 return;
489 }
490 if (irq < 16 && (io[DS7_REG_IE_LO >> 1] & 1 << irq)) {
491 ARMRaiseIRQ(cpu);
492 } else if (io[DS7_REG_IE_HI >> 1] & 1 << (irq - 16)) {
493 ARMRaiseIRQ(cpu);
494 }
495}