1#ifndef ISA_INLINES_H
 2#define ISA_INLINES_H
 3
 4#include "macros.h"
 5
 6#include "arm.h"
 7
 8#define ARM_COND_EQ (cpu->cpsr.z)
 9#define ARM_COND_NE (!cpu->cpsr.z)
10#define ARM_COND_CS (cpu->cpsr.c)
11#define ARM_COND_CC (!cpu->cpsr.c)
12#define ARM_COND_MI (cpu->cpsr.n)
13#define ARM_COND_PL (!cpu->cpsr.n)
14#define ARM_COND_VS (cpu->cpsr.v)
15#define ARM_COND_VC (!cpu->cpsr.v)
16#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
17#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
18#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
19#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
20#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
21#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
22#define ARM_COND_AL 1
23
24#define ARM_SIGN(I) ((I) >> 31)
25#define ARM_ROR(I, ROTATE) ((((uint32_t) (I)) >> ROTATE) | ((uint32_t) (I) << ((-ROTATE) & 31)))
26
27
28#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
29#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
30#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
31#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
32
33#define ARM_WAIT_MUL(R) \
34	if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
35		currentCycles += 1; \
36	} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
37		currentCycles += 2; \
38	} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
39		currentCycles += 3; \
40	} else { \
41		currentCycles += 4; \
42	}
43
44#define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
45#define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
46
47#define ARM_WRITE_PC \
48	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM); \
49	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]); \
50	LOAD_32(cpu->prefetch, cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
51	cpu->gprs[ARM_PC] += WORD_SIZE_ARM; \
52	currentCycles += 2 + cpu->memory.activeUncachedCycles32 + cpu->memory.activeSeqCycles32;
53
54#define THUMB_WRITE_PC \
55	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB); \
56	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]); \
57	LOAD_16(cpu->prefetch, cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
58	cpu->gprs[ARM_PC] += WORD_SIZE_THUMB; \
59	currentCycles += 2 + cpu->memory.activeUncachedCycles16 + cpu->memory.activeSeqCycles16;
60
61static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
62	return mode != MODE_SYSTEM && mode != MODE_USER;
63}
64
65static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
66	if (executionMode == cpu->executionMode) {
67		return;
68	}
69
70	cpu->executionMode = executionMode;
71	switch (executionMode) {
72	case MODE_ARM:
73		cpu->cpsr.t = 0;
74		break;
75	case MODE_THUMB:
76		cpu->cpsr.t = 1;
77	}
78	cpu->nextEvent = 0;
79}
80
81static inline void _ARMReadCPSR(struct ARMCore* cpu) {
82	_ARMSetMode(cpu, cpu->cpsr.t);
83	ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
84	cpu->irqh.readCPSR(cpu);
85}
86
87#endif