src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/io.h>
7
8#include <mgba/internal/gb/gb.h>
9#include <mgba/internal/gb/sio.h>
10#include <mgba/internal/gb/serialize.h>
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
13
14const char* const GBIORegisterNames[] = {
15 [REG_JOYP] = "JOYP",
16 [REG_SB] = "SB",
17 [REG_SC] = "SC",
18 [REG_DIV] = "DIV",
19 [REG_TIMA] = "TIMA",
20 [REG_TMA] = "TMA",
21 [REG_TAC] = "TAC",
22 [REG_IF] = "IF",
23 [REG_NR10] = "NR10",
24 [REG_NR11] = "NR11",
25 [REG_NR12] = "NR12",
26 [REG_NR13] = "NR13",
27 [REG_NR14] = "NR14",
28 [REG_NR21] = "NR21",
29 [REG_NR22] = "NR22",
30 [REG_NR23] = "NR23",
31 [REG_NR24] = "NR24",
32 [REG_NR30] = "NR30",
33 [REG_NR31] = "NR31",
34 [REG_NR32] = "NR32",
35 [REG_NR33] = "NR33",
36 [REG_NR34] = "NR34",
37 [REG_NR41] = "NR41",
38 [REG_NR42] = "NR42",
39 [REG_NR43] = "NR43",
40 [REG_NR44] = "NR44",
41 [REG_NR50] = "NR50",
42 [REG_NR51] = "NR51",
43 [REG_NR52] = "NR52",
44 [REG_LCDC] = "LCDC",
45 [REG_STAT] = "STAT",
46 [REG_SCY] = "SCY",
47 [REG_SCX] = "SCX",
48 [REG_LY] = "LY",
49 [REG_LYC] = "LYC",
50 [REG_DMA] = "DMA",
51 [REG_BGP] = "BGP",
52 [REG_OBP0] = "OBP0",
53 [REG_OBP1] = "OBP1",
54 [REG_WY] = "WY",
55 [REG_WX] = "WX",
56 [REG_KEY1] = "KEY1",
57 [REG_VBK] = "VBK",
58 [REG_HDMA1] = "HDMA1",
59 [REG_HDMA2] = "HDMA2",
60 [REG_HDMA3] = "HDMA3",
61 [REG_HDMA4] = "HDMA4",
62 [REG_HDMA5] = "HDMA5",
63 [REG_RP] = "RP",
64 [REG_BCPS] = "BCPS",
65 [REG_BCPD] = "BCPD",
66 [REG_OCPS] = "OCPS",
67 [REG_OCPD] = "OCPD",
68 [REG_SVBK] = "SVBK",
69 [REG_IE] = "IE",
70};
71
72static const uint8_t _registerMask[] = {
73 [REG_SC] = 0x7E, // TODO: GBC differences
74 [REG_IF] = 0xE0,
75 [REG_TAC] = 0xF8,
76 [REG_NR10] = 0x80,
77 [REG_NR11] = 0x3F,
78 [REG_NR12] = 0x00,
79 [REG_NR13] = 0xFF,
80 [REG_NR14] = 0xBF,
81 [REG_NR21] = 0x3F,
82 [REG_NR22] = 0x00,
83 [REG_NR23] = 0xFF,
84 [REG_NR24] = 0xBF,
85 [REG_NR30] = 0x7F,
86 [REG_NR31] = 0xFF,
87 [REG_NR32] = 0x9F,
88 [REG_NR33] = 0xFF,
89 [REG_NR34] = 0xBF,
90 [REG_NR41] = 0xFF,
91 [REG_NR42] = 0x00,
92 [REG_NR43] = 0x00,
93 [REG_NR44] = 0xBF,
94 [REG_NR50] = 0x00,
95 [REG_NR51] = 0x00,
96 [REG_NR52] = 0x70,
97 [REG_STAT] = 0x80,
98 [REG_KEY1] = 0x7E,
99 [REG_VBK] = 0xFE,
100 [REG_OCPS] = 0x40,
101 [REG_BCPS] = 0x40,
102 [REG_UNK6C] = 0xFE,
103 [REG_SVBK] = 0xF8,
104 [REG_IE] = 0xE0,
105};
106
107static uint8_t _readKeys(struct GB* gb);
108
109static void _writeSGBBits(struct GB* gb, int bits) {
110 if (!bits) {
111 gb->sgbBit = -1;
112 memset(gb->sgbPacket, 0, sizeof(gb->sgbPacket));
113 }
114 if (bits == gb->currentSgbBits) {
115 return;
116 }
117 gb->currentSgbBits = bits;
118 if (gb->sgbBit > 128) {
119 switch (bits) {
120 case 1:
121 gb->sgbBit |= 2;
122 break;
123 case 2:
124 gb->sgbBit |= 4;
125 break;
126 case 3:
127 if (gb->sgbBit == 135) {
128 gb->sgbBit &= ~6;
129 gb->sgbCurrentController = (gb->sgbCurrentController + 1) & gb->sgbControllers;
130 }
131 break;
132 }
133 }
134 if (gb->sgbBit == 128 && bits == 2) {
135 GBVideoWriteSGBPacket(&gb->video, gb->sgbPacket);
136 ++gb->sgbBit;
137 }
138 if (gb->sgbBit >= 128) {
139 return;
140 }
141 switch (bits) {
142 case 1:
143 if (gb->sgbBit < 0) {
144 return;
145 }
146 gb->sgbPacket[gb->sgbBit >> 3] |= 1 << (gb->sgbBit & 7);
147 break;
148 case 3:
149 ++gb->sgbBit;
150 default:
151 break;
152 }
153}
154
155void GBIOInit(struct GB* gb) {
156 memset(gb->memory.io, 0, sizeof(gb->memory.io));
157}
158
159void GBIOReset(struct GB* gb) {
160 memset(gb->memory.io, 0, sizeof(gb->memory.io));
161
162 GBIOWrite(gb, REG_TIMA, 0);
163 GBIOWrite(gb, REG_TMA, 0);
164 GBIOWrite(gb, REG_TAC, 0);
165 GBIOWrite(gb, REG_IF, 1);
166 GBIOWrite(gb, REG_NR52, 0xF1);
167 GBIOWrite(gb, REG_NR14, 0x3F);
168 GBIOWrite(gb, REG_NR10, 0x80);
169 GBIOWrite(gb, REG_NR11, 0xBF);
170 GBIOWrite(gb, REG_NR12, 0xF3);
171 GBIOWrite(gb, REG_NR13, 0xF3);
172 GBIOWrite(gb, REG_NR24, 0x3F);
173 GBIOWrite(gb, REG_NR21, 0x3F);
174 GBIOWrite(gb, REG_NR22, 0x00);
175 GBIOWrite(gb, REG_NR34, 0x3F);
176 GBIOWrite(gb, REG_NR30, 0x7F);
177 GBIOWrite(gb, REG_NR31, 0xFF);
178 GBIOWrite(gb, REG_NR32, 0x9F);
179 GBIOWrite(gb, REG_NR44, 0x3F);
180 GBIOWrite(gb, REG_NR41, 0xFF);
181 GBIOWrite(gb, REG_NR42, 0x00);
182 GBIOWrite(gb, REG_NR43, 0x00);
183 GBIOWrite(gb, REG_NR50, 0x77);
184 GBIOWrite(gb, REG_NR51, 0xF3);
185 GBIOWrite(gb, REG_LCDC, 0x91);
186 GBIOWrite(gb, REG_SCY, 0x00);
187 GBIOWrite(gb, REG_SCX, 0x00);
188 GBIOWrite(gb, REG_LYC, 0x00);
189 GBIOWrite(gb, REG_BGP, 0xFC);
190 if (gb->model < GB_MODEL_CGB) {
191 GBIOWrite(gb, REG_OBP0, 0xFF);
192 GBIOWrite(gb, REG_OBP1, 0xFF);
193 }
194 GBIOWrite(gb, REG_WY, 0x00);
195 GBIOWrite(gb, REG_WX, 0x00);
196 if (gb->model >= GB_MODEL_CGB) {
197 GBIOWrite(gb, REG_UNK4C, 0);
198 GBIOWrite(gb, REG_JOYP, 0xFF);
199 GBIOWrite(gb, REG_VBK, 0);
200 GBIOWrite(gb, REG_BCPS, 0);
201 GBIOWrite(gb, REG_OCPS, 0);
202 GBIOWrite(gb, REG_SVBK, 1);
203 GBIOWrite(gb, REG_HDMA1, 0xFF);
204 GBIOWrite(gb, REG_HDMA2, 0xFF);
205 GBIOWrite(gb, REG_HDMA3, 0xFF);
206 GBIOWrite(gb, REG_HDMA4, 0xFF);
207 gb->memory.io[REG_HDMA5] = 0xFF;
208 } else if (gb->model == GB_MODEL_SGB) {
209 GBIOWrite(gb, REG_JOYP, 0xFF);
210 }
211 GBIOWrite(gb, REG_IE, 0x00);
212}
213
214void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
215 switch (address) {
216 case REG_SB:
217 GBSIOWriteSB(&gb->sio, value);
218 break;
219 case REG_SC:
220 GBSIOWriteSC(&gb->sio, value);
221 break;
222 case REG_DIV:
223 GBTimerDivReset(&gb->timer);
224 return;
225 case REG_NR10:
226 if (gb->audio.enable) {
227 GBAudioWriteNR10(&gb->audio, value);
228 } else {
229 value = 0;
230 }
231 break;
232 case REG_NR11:
233 if (gb->audio.enable) {
234 GBAudioWriteNR11(&gb->audio, value);
235 } else {
236 if (gb->audio.style == GB_AUDIO_DMG) {
237 GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
238 }
239 value = 0;
240 }
241 break;
242 case REG_NR12:
243 if (gb->audio.enable) {
244 GBAudioWriteNR12(&gb->audio, value);
245 } else {
246 value = 0;
247 }
248 break;
249 case REG_NR13:
250 if (gb->audio.enable) {
251 GBAudioWriteNR13(&gb->audio, value);
252 } else {
253 value = 0;
254 }
255 break;
256 case REG_NR14:
257 if (gb->audio.enable) {
258 GBAudioWriteNR14(&gb->audio, value);
259 } else {
260 value = 0;
261 }
262 break;
263 case REG_NR21:
264 if (gb->audio.enable) {
265 GBAudioWriteNR21(&gb->audio, value);
266 } else {
267 if (gb->audio.style == GB_AUDIO_DMG) {
268 GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
269 }
270 value = 0;
271 }
272 break;
273 case REG_NR22:
274 if (gb->audio.enable) {
275 GBAudioWriteNR22(&gb->audio, value);
276 } else {
277 value = 0;
278 }
279 break;
280 case REG_NR23:
281 if (gb->audio.enable) {
282 GBAudioWriteNR23(&gb->audio, value);
283 } else {
284 value = 0;
285 }
286 break;
287 case REG_NR24:
288 if (gb->audio.enable) {
289 GBAudioWriteNR24(&gb->audio, value);
290 } else {
291 value = 0;
292 }
293 break;
294 case REG_NR30:
295 if (gb->audio.enable) {
296 GBAudioWriteNR30(&gb->audio, value);
297 } else {
298 value = 0;
299 }
300 break;
301 case REG_NR31:
302 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
303 GBAudioWriteNR31(&gb->audio, value);
304 } else {
305 value = 0;
306 }
307 break;
308 case REG_NR32:
309 if (gb->audio.enable) {
310 GBAudioWriteNR32(&gb->audio, value);
311 } else {
312 value = 0;
313 }
314 break;
315 case REG_NR33:
316 if (gb->audio.enable) {
317 GBAudioWriteNR33(&gb->audio, value);
318 } else {
319 value = 0;
320 }
321 break;
322 case REG_NR34:
323 if (gb->audio.enable) {
324 GBAudioWriteNR34(&gb->audio, value);
325 } else {
326 value = 0;
327 }
328 break;
329 case REG_NR41:
330 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
331 GBAudioWriteNR41(&gb->audio, value);
332 } else {
333 value = 0;
334 }
335 break;
336 case REG_NR42:
337 if (gb->audio.enable) {
338 GBAudioWriteNR42(&gb->audio, value);
339 } else {
340 value = 0;
341 }
342 break;
343 case REG_NR43:
344 if (gb->audio.enable) {
345 GBAudioWriteNR43(&gb->audio, value);
346 } else {
347 value = 0;
348 }
349 break;
350 case REG_NR44:
351 if (gb->audio.enable) {
352 GBAudioWriteNR44(&gb->audio, value);
353 } else {
354 value = 0;
355 }
356 break;
357 case REG_NR50:
358 if (gb->audio.enable) {
359 GBAudioWriteNR50(&gb->audio, value);
360 } else {
361 value = 0;
362 }
363 break;
364 case REG_NR51:
365 if (gb->audio.enable) {
366 GBAudioWriteNR51(&gb->audio, value);
367 } else {
368 value = 0;
369 }
370 break;
371 case REG_NR52:
372 GBAudioWriteNR52(&gb->audio, value);
373 value &= 0x80;
374 value |= gb->memory.io[REG_NR52] & 0x0F;
375 break;
376 case REG_WAVE_0:
377 case REG_WAVE_1:
378 case REG_WAVE_2:
379 case REG_WAVE_3:
380 case REG_WAVE_4:
381 case REG_WAVE_5:
382 case REG_WAVE_6:
383 case REG_WAVE_7:
384 case REG_WAVE_8:
385 case REG_WAVE_9:
386 case REG_WAVE_A:
387 case REG_WAVE_B:
388 case REG_WAVE_C:
389 case REG_WAVE_D:
390 case REG_WAVE_E:
391 case REG_WAVE_F:
392 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
393 gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
394 } else if(gb->audio.ch3.readable) {
395 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
396 }
397 break;
398 case REG_JOYP:
399 gb->memory.io[REG_JOYP] = value | 0x0F;
400 _readKeys(gb);
401 if (gb->model == GB_MODEL_SGB) {
402 _writeSGBBits(gb, (value >> 4) & 3);
403 }
404 return;
405 case REG_TIMA:
406 if (value && mTimingUntil(&gb->timing, &gb->timer.irq) > 1) {
407 mTimingDeschedule(&gb->timing, &gb->timer.irq);
408 }
409 if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
410 return;
411 }
412 break;
413 case REG_TMA:
414 if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
415 gb->memory.io[REG_TIMA] = value;
416 }
417 break;
418 case REG_TAC:
419 value = GBTimerUpdateTAC(&gb->timer, value);
420 break;
421 case REG_IF:
422 gb->memory.io[REG_IF] = value | 0xE0;
423 GBUpdateIRQs(gb);
424 return;
425 case REG_LCDC:
426 // TODO: handle GBC differences
427 GBVideoProcessDots(&gb->video, 0);
428 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
429 GBVideoWriteLCDC(&gb->video, value);
430 break;
431 case REG_LYC:
432 GBVideoWriteLYC(&gb->video, value);
433 break;
434 case REG_DMA:
435 GBMemoryDMA(gb, value << 8);
436 break;
437 case REG_SCY:
438 case REG_SCX:
439 case REG_WY:
440 case REG_WX:
441 GBVideoProcessDots(&gb->video, 0);
442 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
443 break;
444 case REG_BGP:
445 case REG_OBP0:
446 case REG_OBP1:
447 GBVideoProcessDots(&gb->video, 0);
448 GBVideoWritePalette(&gb->video, address, value);
449 break;
450 case REG_STAT:
451 GBVideoWriteSTAT(&gb->video, value);
452 value = gb->video.stat;
453 break;
454 case 0x50:
455 GBUnmapBIOS(gb);
456 if (gb->model >= GB_MODEL_CGB && gb->memory.io[REG_UNK4C] < 0x80) {
457 gb->model = GB_MODEL_DMG;
458 GBVideoDisableCGB(&gb->video);
459 }
460 break;
461 case REG_IE:
462 gb->memory.ie = value;
463 GBUpdateIRQs(gb);
464 return;
465 default:
466 if (gb->model >= GB_MODEL_CGB) {
467 switch (address) {
468 case REG_UNK4C:
469 break;
470 case REG_KEY1:
471 value &= 0x1;
472 value |= gb->memory.io[address] & 0x80;
473 break;
474 case REG_VBK:
475 GBVideoSwitchBank(&gb->video, value);
476 break;
477 case REG_HDMA1:
478 case REG_HDMA2:
479 case REG_HDMA3:
480 case REG_HDMA4:
481 // Handled transparently by the registers
482 break;
483 case REG_HDMA5:
484 value = GBMemoryWriteHDMA5(gb, value);
485 break;
486 case REG_BCPS:
487 gb->video.bcpIndex = value & 0x3F;
488 gb->video.bcpIncrement = value & 0x80;
489 gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
490 break;
491 case REG_BCPD:
492 if (gb->video.mode != 3) {
493 GBVideoProcessDots(&gb->video, 0);
494 GBVideoWritePalette(&gb->video, address, value);
495 }
496 return;
497 case REG_OCPS:
498 gb->video.ocpIndex = value & 0x3F;
499 gb->video.ocpIncrement = value & 0x80;
500 gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
501 break;
502 case REG_OCPD:
503 if (gb->video.mode != 3) {
504 GBVideoProcessDots(&gb->video, 0);
505 GBVideoWritePalette(&gb->video, address, value);
506 }
507 return;
508 case REG_SVBK:
509 GBMemorySwitchWramBank(&gb->memory, value);
510 value = gb->memory.wramCurrentBank;
511 break;
512 default:
513 goto failed;
514 }
515 goto success;
516 }
517 failed:
518 mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
519 if (address >= GB_SIZE_IO) {
520 return;
521 }
522 break;
523 }
524 success:
525 gb->memory.io[address] = value;
526}
527
528static uint8_t _readKeys(struct GB* gb) {
529 uint8_t keys = *gb->keySource;
530 if (gb->sgbCurrentController != 0) {
531 keys = 0;
532 }
533 uint8_t joyp = gb->memory.io[REG_JOYP];
534 switch (joyp & 0x30) {
535 case 0x30:
536 keys = gb->sgbCurrentController;
537 break;
538 case 0x20:
539 keys >>= 4;
540 break;
541 case 0x10:
542 break;
543 case 0x00:
544 keys |= keys >> 4;
545 break;
546 }
547 gb->memory.io[REG_JOYP] = (0xCF | joyp) ^ (keys & 0xF);
548 if (joyp & ~gb->memory.io[REG_JOYP] & 0xF) {
549 gb->memory.io[REG_IF] |= (1 << GB_IRQ_KEYPAD);
550 GBUpdateIRQs(gb);
551 }
552 return gb->memory.io[REG_JOYP];
553}
554
555uint8_t GBIORead(struct GB* gb, unsigned address) {
556 switch (address) {
557 case REG_JOYP:
558 return _readKeys(gb);
559 case REG_IE:
560 return gb->memory.ie;
561 case REG_WAVE_0:
562 case REG_WAVE_1:
563 case REG_WAVE_2:
564 case REG_WAVE_3:
565 case REG_WAVE_4:
566 case REG_WAVE_5:
567 case REG_WAVE_6:
568 case REG_WAVE_7:
569 case REG_WAVE_8:
570 case REG_WAVE_9:
571 case REG_WAVE_A:
572 case REG_WAVE_B:
573 case REG_WAVE_C:
574 case REG_WAVE_D:
575 case REG_WAVE_E:
576 case REG_WAVE_F:
577 if (gb->audio.playingCh3) {
578 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
579 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
580 } else {
581 return 0xFF;
582 }
583 } else {
584 return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
585 }
586 break;
587 case REG_SB:
588 case REG_SC:
589 case REG_IF:
590 case REG_NR10:
591 case REG_NR11:
592 case REG_NR12:
593 case REG_NR14:
594 case REG_NR21:
595 case REG_NR22:
596 case REG_NR24:
597 case REG_NR30:
598 case REG_NR32:
599 case REG_NR34:
600 case REG_NR41:
601 case REG_NR42:
602 case REG_NR43:
603 case REG_NR44:
604 case REG_NR50:
605 case REG_NR51:
606 case REG_NR52:
607 case REG_DIV:
608 case REG_TIMA:
609 case REG_TMA:
610 case REG_TAC:
611 case REG_STAT:
612 case REG_LCDC:
613 case REG_SCY:
614 case REG_SCX:
615 case REG_LY:
616 case REG_LYC:
617 case REG_BGP:
618 case REG_OBP0:
619 case REG_OBP1:
620 case REG_WY:
621 case REG_WX:
622 // Handled transparently by the registers
623 break;
624 default:
625 if (gb->model >= GB_MODEL_CGB) {
626 switch (address) {
627 case REG_KEY1:
628 case REG_VBK:
629 case REG_HDMA1:
630 case REG_HDMA2:
631 case REG_HDMA3:
632 case REG_HDMA4:
633 case REG_HDMA5:
634 case REG_BCPS:
635 case REG_BCPD:
636 case REG_OCPS:
637 case REG_OCPD:
638 case REG_SVBK:
639 // Handled transparently by the registers
640 goto success;
641 case REG_DMA:
642 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
643 return 0;
644 default:
645 break;
646 }
647 }
648 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
649 return 0xFF;
650 }
651 success:
652 return gb->memory.io[address] | _registerMask[address];
653}
654
655void GBTestKeypadIRQ(struct GB* gb) {
656 _readKeys(gb);
657}
658
659struct GBSerializedState;
660void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
661 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
662 state->ie = gb->memory.ie;
663}
664
665void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
666 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
667 gb->memory.ie = state->ie;
668
669 if (GBAudioEnableGetEnable(*gb->audio.nr52)) {
670 GBIOWrite(gb, REG_NR10, gb->memory.io[REG_NR10]);
671 GBIOWrite(gb, REG_NR11, gb->memory.io[REG_NR11]);
672 GBIOWrite(gb, REG_NR12, gb->memory.io[REG_NR12]);
673 GBIOWrite(gb, REG_NR13, gb->memory.io[REG_NR13]);
674 gb->audio.ch1.control.frequency &= 0xFF;
675 gb->audio.ch1.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR14] << 8);
676 gb->audio.ch1.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR14] << 8);
677 GBIOWrite(gb, REG_NR21, gb->memory.io[REG_NR21]);
678 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR22]);
679 GBIOWrite(gb, REG_NR22, gb->memory.io[REG_NR23]);
680 gb->audio.ch2.control.frequency &= 0xFF;
681 gb->audio.ch2.control.frequency |= GBAudioRegisterControlGetFrequency(gb->memory.io[REG_NR24] << 8);
682 gb->audio.ch2.control.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR24] << 8);
683 GBIOWrite(gb, REG_NR30, gb->memory.io[REG_NR30]);
684 GBIOWrite(gb, REG_NR31, gb->memory.io[REG_NR31]);
685 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR32]);
686 GBIOWrite(gb, REG_NR32, gb->memory.io[REG_NR33]);
687 gb->audio.ch3.rate &= 0xFF;
688 gb->audio.ch3.rate |= GBAudioRegisterControlGetRate(gb->memory.io[REG_NR34] << 8);
689 gb->audio.ch3.stop = GBAudioRegisterControlGetStop(gb->memory.io[REG_NR34] << 8);
690 GBIOWrite(gb, REG_NR41, gb->memory.io[REG_NR41]);
691 GBIOWrite(gb, REG_NR42, gb->memory.io[REG_NR42]);
692 GBIOWrite(gb, REG_NR43, gb->memory.io[REG_NR43]);
693 gb->audio.ch4.stop = GBAudioRegisterNoiseControlGetStop(gb->memory.io[REG_NR44]);
694 GBIOWrite(gb, REG_NR50, gb->memory.io[REG_NR50]);
695 GBIOWrite(gb, REG_NR51, gb->memory.io[REG_NR51]);
696 }
697
698 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
699 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
700 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
701 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
702 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
703 if (gb->model == GB_MODEL_SGB) {
704 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_BGP, state->io[REG_BGP]);
705 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP0, state->io[REG_OBP0]);
706 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_OBP1, state->io[REG_OBP1]);
707 }
708 gb->video.stat = state->io[REG_STAT];
709}