1/* Copyright (c) 2013-2015 Jeffrey Pfau
   2 *
   3 * This Source Code Form is subject to the terms of the Mozilla Public
   4 * License, v. 2.0. If a copy of the MPL was not distributed with this
   5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
   6#include "memory.h"
   7
   8#include "macros.h"
   9
  10#include "decoder.h"
  11#include "gba/hardware.h"
  12#include "gba/io.h"
  13#include "gba/serialize.h"
  14#include "gba/hle-bios.h"
  15#include "util/memory.h"
  16
  17#define IDLE_LOOP_THRESHOLD 10000
  18
  19static uint32_t _popcount32(unsigned bits);
  20static void _pristineCow(struct GBA* gba);
  21static uint32_t _deadbeef[2] = { 0xDEADBEEF, 0xFEEDFACE };
  22
  23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
  24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
  25
  26static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
  27static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
  28static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
  29static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
  30static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
  31static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
  32static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
  33
  34void GBAMemoryInit(struct GBA* gba) {
  35	struct ARMCore* cpu = gba->cpu;
  36	cpu->memory.load32 = GBALoad32;
  37	cpu->memory.load16 = GBALoad16;
  38	cpu->memory.load8 = GBALoad8;
  39	cpu->memory.loadMultiple = GBALoadMultiple;
  40	cpu->memory.store32 = GBAStore32;
  41	cpu->memory.store16 = GBAStore16;
  42	cpu->memory.store8 = GBAStore8;
  43	cpu->memory.storeMultiple = GBAStoreMultiple;
  44
  45	gba->memory.bios = (uint32_t*) hleBios;
  46	gba->memory.fullBios = 0;
  47	gba->memory.wram = 0;
  48	gba->memory.iwram = 0;
  49	gba->memory.rom = 0;
  50	gba->memory.hw.p = gba;
  51
  52	int i;
  53	for (i = 0; i < 16; ++i) {
  54		gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
  55		gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
  56		gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
  57		gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
  58		gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
  59		gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
  60		gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
  61		gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
  62	}
  63	for (; i < 256; ++i) {
  64		gba->memory.waitstatesNonseq16[i] = 0;
  65		gba->memory.waitstatesSeq16[i] = 0;
  66		gba->memory.waitstatesNonseq32[i] = 0;
  67		gba->memory.waitstatesSeq32[i] = 0;
  68	}
  69
  70	gba->memory.activeRegion = -1;
  71	cpu->memory.activeRegion = 0;
  72	cpu->memory.activeMask = 0;
  73	cpu->memory.setActiveRegion = GBASetActiveRegion;
  74	cpu->memory.activeSeqCycles32 = 0;
  75	cpu->memory.activeSeqCycles16 = 0;
  76	cpu->memory.activeNonseqCycles32 = 0;
  77	cpu->memory.activeNonseqCycles16 = 0;
  78	cpu->memory.activeUncachedCycles32 = 0;
  79	cpu->memory.activeUncachedCycles16 = 0;
  80	gba->memory.biosPrefetch = 0;
  81}
  82
  83void GBAMemoryDeinit(struct GBA* gba) {
  84	mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
  85	mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
  86	if (gba->memory.rom) {
  87		mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
  88	}
  89	GBASavedataDeinit(&gba->memory.savedata);
  90}
  91
  92void GBAMemoryReset(struct GBA* gba) {
  93	if (gba->memory.wram) {
  94		mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
  95	}
  96	gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
  97
  98	if (gba->memory.iwram) {
  99		mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
 100	}
 101	gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
 102
 103	memset(gba->memory.io, 0, sizeof(gba->memory.io));
 104	memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
 105	int i;
 106	for (i = 0; i < 4; ++i) {
 107		gba->memory.dma[i].count = 0x4000;
 108		gba->memory.dma[i].nextEvent = INT_MAX;
 109	}
 110	gba->memory.dma[3].count = 0x10000;
 111	gba->memory.activeDMA = -1;
 112	gba->memory.nextDMA = INT_MAX;
 113	gba->memory.eventDiff = 0;
 114
 115	if (!gba->memory.wram || !gba->memory.iwram) {
 116		GBAMemoryDeinit(gba);
 117		GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
 118	}
 119}
 120
 121static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
 122	struct ARMInstructionInfo info;
 123	uint32_t nextAddress = address;
 124	memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
 125	if (cpu->executionMode == MODE_THUMB) {
 126		while (true) {
 127			uint16_t opcode;
 128			LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
 129			ARMDecodeThumb(opcode, &info);
 130			switch (info.branchType) {
 131			case ARM_BRANCH_NONE:
 132				if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
 133					if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
 134						gba->idleDetectionStep = -1;
 135						return;
 136					}
 137					uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
 138					uint32_t offset = 0;
 139					if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
 140						offset = info.memory.offset.immediate;
 141					} else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
 142						int reg = info.memory.offset.reg;
 143						if (gba->cachedRegisters[reg]) {
 144							gba->idleDetectionStep = -1;
 145							return;
 146						}
 147						offset = gba->cachedRegisters[reg];
 148					}
 149					if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
 150						loadAddress -= offset;
 151					} else {
 152						loadAddress += offset;
 153					}
 154					if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
 155						gba->idleDetectionStep = -1;
 156						return;
 157					}
 158					if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
 159						gba->taintedRegisters[info.op1.reg] = true;
 160					} else {
 161						switch (info.memory.width) {
 162						case 1:
 163							gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
 164							break;
 165						case 2:
 166							gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
 167							break;
 168						case 4:
 169							gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
 170							break;
 171						}
 172					}
 173				} else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
 174					gba->taintedRegisters[info.op1.reg] = true;
 175				}
 176				nextAddress += WORD_SIZE_THUMB;
 177				break;
 178			case ARM_BRANCH:
 179				if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
 180					gba->idleLoop = address;
 181					gba->idleOptimization = IDLE_LOOP_REMOVE;
 182				}
 183				gba->idleDetectionStep = -1;
 184				return;
 185			default:
 186				gba->idleDetectionStep = -1;
 187				return;
 188			}
 189		}
 190	} else {
 191		gba->idleDetectionStep = -1;
 192	}
 193}
 194
 195static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
 196	struct GBA* gba = (struct GBA*) cpu->master;
 197	struct GBAMemory* memory = &gba->memory;
 198
 199	int newRegion = address >> BASE_OFFSET;
 200	if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
 201		if (address == gba->idleLoop) {
 202			if (gba->haltPending) {
 203				gba->haltPending = false;
 204				GBAHalt(gba);
 205			} else {
 206				gba->haltPending = true;
 207			}
 208		} else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
 209			if (address == gba->lastJump) {
 210				switch (gba->idleDetectionStep) {
 211				case 0:
 212					memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
 213					++gba->idleDetectionStep;
 214					break;
 215				case 1:
 216					if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
 217						gba->idleDetectionStep = -1;
 218						++gba->idleDetectionFailures;
 219						if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
 220							gba->idleOptimization = IDLE_LOOP_IGNORE;
 221						}
 222						break;
 223					}
 224					_analyzeForIdleLoop(gba, cpu, address);
 225					break;
 226				}
 227			} else {
 228				gba->idleDetectionStep = 0;
 229			}
 230		}
 231	}
 232
 233	gba->lastJump = address;
 234	if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
 235		return;
 236	}
 237
 238	if (memory->activeRegion == REGION_BIOS) {
 239		memory->biosPrefetch = cpu->prefetch[1];
 240	}
 241	memory->activeRegion = newRegion;
 242	switch (newRegion) {
 243	case REGION_BIOS:
 244		cpu->memory.activeRegion = memory->bios;
 245		cpu->memory.activeMask = SIZE_BIOS - 1;
 246		break;
 247	case REGION_WORKING_RAM:
 248		cpu->memory.activeRegion = memory->wram;
 249		cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
 250		break;
 251	case REGION_WORKING_IRAM:
 252		cpu->memory.activeRegion = memory->iwram;
 253		cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
 254		break;
 255	case REGION_VRAM:
 256		cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
 257		cpu->memory.activeMask = 0x0000FFFF;
 258		break;
 259	case REGION_CART0:
 260	case REGION_CART0_EX:
 261	case REGION_CART1:
 262	case REGION_CART1_EX:
 263	case REGION_CART2:
 264	case REGION_CART2_EX:
 265		cpu->memory.activeRegion = memory->rom;
 266		cpu->memory.activeMask = SIZE_CART0 - 1;
 267		if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 268			break;
 269		}
 270		// Fall through
 271	default:
 272		memory->activeRegion = 0;
 273		cpu->memory.activeRegion = _deadbeef;
 274		cpu->memory.activeMask = 0;
 275		GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
 276		break;
 277	}
 278	cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
 279	cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
 280	cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
 281	cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
 282	cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
 283	cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
 284}
 285
 286#define LOAD_BAD \
 287	if (gba->performingDMA) { \
 288		value = gba->bus; \
 289	} else { \
 290		value = cpu->prefetch[1]; \
 291		if (cpu->executionMode == MODE_THUMB) { \
 292			/* http://ngemu.com/threads/gba-open-bus.170809/ */ \
 293			switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
 294			case REGION_BIOS: \
 295			case REGION_OAM: \
 296				/* This isn't right half the time, but we don't have $+6 handy */ \
 297				value <<= 16; \
 298				value |= cpu->prefetch[0]; \
 299				break; \
 300			case REGION_WORKING_IRAM: \
 301				/* This doesn't handle prefetch clobbering */ \
 302				if (cpu->gprs[ARM_PC] & 2) { \
 303					value |= cpu->prefetch[0] << 16; \
 304				} else { \
 305					value <<= 16; \
 306					value |= cpu->prefetch[0]; \
 307				} \
 308			default: \
 309				value |= value << 16; \
 310			} \
 311		} \
 312	}
 313
 314#define LOAD_BIOS \
 315	if (address < SIZE_BIOS) { \
 316		if (memory->activeRegion == REGION_BIOS) { \
 317			LOAD_32(value, address, memory->bios); \
 318		} else { \
 319			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
 320			value = memory->biosPrefetch; \
 321		} \
 322	} else { \
 323		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
 324		LOAD_BAD; \
 325	}
 326
 327#define LOAD_WORKING_RAM \
 328	LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
 329	wait += waitstatesRegion[REGION_WORKING_RAM];
 330
 331#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 332#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
 333
 334#define LOAD_PALETTE_RAM \
 335	LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
 336	++wait;
 337
 338#define LOAD_VRAM \
 339	if ((address & 0x0001FFFF) < SIZE_VRAM) { \
 340		LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
 341	} else { \
 342		LOAD_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
 343	} \
 344	++wait;
 345
 346#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 347
 348#define LOAD_CART \
 349	wait += waitstatesRegion[address >> BASE_OFFSET]; \
 350	if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
 351		LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom); \
 352	} else { \
 353		GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
 354		value = (address >> 1) & 0xFFFF; \
 355		value |= ((address + 2) >> 1) << 16; \
 356	}
 357
 358#define LOAD_SRAM \
 359	wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
 360	value = GBALoad8(cpu, address, 0); \
 361	value |= value << 8; \
 362	value |= value << 16;
 363
 364uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 365	struct GBA* gba = (struct GBA*) cpu->master;
 366	struct GBAMemory* memory = &gba->memory;
 367	uint32_t value = 0;
 368	int wait = 0;
 369	char* waitstatesRegion = memory->waitstatesNonseq32;
 370
 371	switch (address >> BASE_OFFSET) {
 372	case REGION_BIOS:
 373		LOAD_BIOS;
 374		break;
 375	case REGION_WORKING_RAM:
 376		LOAD_WORKING_RAM;
 377		break;
 378	case REGION_WORKING_IRAM:
 379		LOAD_WORKING_IRAM;
 380		break;
 381	case REGION_IO:
 382		LOAD_IO;
 383		break;
 384	case REGION_PALETTE_RAM:
 385		LOAD_PALETTE_RAM;
 386		break;
 387	case REGION_VRAM:
 388		LOAD_VRAM;
 389		break;
 390	case REGION_OAM:
 391		LOAD_OAM;
 392		break;
 393	case REGION_CART0:
 394	case REGION_CART0_EX:
 395	case REGION_CART1:
 396	case REGION_CART1_EX:
 397	case REGION_CART2:
 398	case REGION_CART2_EX:
 399		LOAD_CART;
 400		break;
 401	case REGION_CART_SRAM:
 402	case REGION_CART_SRAM_MIRROR:
 403		LOAD_SRAM;
 404		break;
 405	default:
 406		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
 407		LOAD_BAD;
 408		break;
 409	}
 410
 411	if (cycleCounter) {
 412		*cycleCounter += 1 + wait;
 413	}
 414	// Unaligned 32-bit loads are "rotated" so they make some semblance of sense
 415	int rotate = (address & 3) << 3;
 416	return ROR(value, rotate);
 417}
 418
 419uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 420	struct GBA* gba = (struct GBA*) cpu->master;
 421	struct GBAMemory* memory = &gba->memory;
 422	uint32_t value = 0;
 423	int wait = 0;
 424
 425	switch (address >> BASE_OFFSET) {
 426	case REGION_BIOS:
 427		if (address < SIZE_BIOS) {
 428			if (memory->activeRegion == REGION_BIOS) {
 429				LOAD_16(value, address, memory->bios);
 430			} else {
 431				GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
 432				LOAD_16(value, address & 2, &memory->biosPrefetch);
 433			}
 434		} else {
 435			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
 436			LOAD_BAD;
 437			uint32_t v2 = value;
 438			LOAD_16(value, address & 2, &v2);
 439		}
 440		break;
 441	case REGION_WORKING_RAM:
 442		LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 443		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 444		break;
 445	case REGION_WORKING_IRAM:
 446		LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 447		break;
 448	case REGION_IO:
 449		value = GBAIORead(gba, address & (SIZE_IO - 1));
 450		break;
 451	case REGION_PALETTE_RAM:
 452		LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 453		break;
 454	case REGION_VRAM:
 455		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 456			LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 457		} else {
 458			LOAD_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 459		}
 460		break;
 461	case REGION_OAM:
 462		LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 463		break;
 464	case REGION_CART0:
 465	case REGION_CART0_EX:
 466	case REGION_CART1:
 467	case REGION_CART1_EX:
 468	case REGION_CART2:
 469		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 470		if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 471			LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
 472		} else {
 473			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
 474			value = (address >> 1) & 0xFFFF; \
 475		}
 476		break;
 477	case REGION_CART2_EX:
 478		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 479		if (memory->savedata.type == SAVEDATA_EEPROM) {
 480			value = GBASavedataReadEEPROM(&memory->savedata);
 481		} else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 482			LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
 483		} else {
 484			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
 485			value = (address >> 1) & 0xFFFF; \
 486		}
 487		break;
 488	case REGION_CART_SRAM:
 489	case REGION_CART_SRAM_MIRROR:
 490		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 491		value = GBALoad8(cpu, address, 0);
 492		value |= value << 8;
 493		break;
 494	default:
 495		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
 496		LOAD_BAD;
 497		uint32_t v2 = value;
 498		LOAD_16(value, address & 2, &v2);
 499		break;
 500	}
 501
 502	if (cycleCounter) {
 503		*cycleCounter += 1 + wait;
 504	}
 505	// Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
 506	int rotate = (address & 1) << 3;
 507	return ROR(value, rotate);
 508}
 509
 510uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 511	struct GBA* gba = (struct GBA*) cpu->master;
 512	struct GBAMemory* memory = &gba->memory;
 513	uint32_t value = 0;
 514	int wait = 0;
 515
 516	switch (address >> BASE_OFFSET) {
 517	case REGION_BIOS:
 518		if (address < SIZE_BIOS) {
 519			if (memory->activeRegion == REGION_BIOS) {
 520				value = ((uint8_t*) memory->bios)[address];
 521			} else {
 522				GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
 523				value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
 524			}
 525		} else {
 526			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
 527			LOAD_BAD;
 528			value = ((uint8_t*) &value)[address & 3];
 529		}
 530		break;
 531	case REGION_WORKING_RAM:
 532		value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
 533		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 534		break;
 535	case REGION_WORKING_IRAM:
 536		value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
 537		break;
 538	case REGION_IO:
 539		value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
 540		break;
 541	case REGION_PALETTE_RAM:
 542		value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
 543		break;
 544	case REGION_VRAM:
 545		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 546			value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
 547		} else {
 548			value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
 549		}
 550		break;
 551	case REGION_OAM:
 552		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
 553		break;
 554	case REGION_CART0:
 555	case REGION_CART0_EX:
 556	case REGION_CART1:
 557	case REGION_CART1_EX:
 558	case REGION_CART2:
 559	case REGION_CART2_EX:
 560		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 561		if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 562			value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
 563		} else {
 564			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
 565			value = (address >> 1) & 0xFF; \
 566		}
 567		break;
 568	case REGION_CART_SRAM:
 569	case REGION_CART_SRAM_MIRROR:
 570		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 571		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 572			GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
 573			GBASavedataInitSRAM(&memory->savedata);
 574		}
 575		if (memory->savedata.type == SAVEDATA_SRAM) {
 576			value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
 577		} else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
 578			value = GBASavedataReadFlash(&memory->savedata, address);
 579		} else if (memory->hw.devices & HW_TILT) {
 580			value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
 581		} else {
 582			GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
 583			value = 0xFF;
 584		}
 585		value &= 0xFF;
 586		break;
 587	default:
 588		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
 589		LOAD_BAD;
 590		value = ((uint8_t*) &value)[address & 3];
 591		break;
 592	}
 593
 594	if (cycleCounter) {
 595		*cycleCounter += 1 + wait;
 596	}
 597	return value;
 598}
 599
 600#define STORE_WORKING_RAM \
 601	STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
 602	wait += waitstatesRegion[REGION_WORKING_RAM];
 603
 604#define STORE_WORKING_IRAM \
 605	STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 606
 607#define STORE_IO \
 608	GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
 609
 610#define STORE_PALETTE_RAM \
 611	STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
 612	gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16); \
 613	++wait; \
 614	gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 615
 616#define STORE_VRAM \
 617	if ((address & 0x0001FFFF) < SIZE_VRAM) { \
 618		STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
 619	} else { \
 620		STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
 621	} \
 622	++wait;
 623
 624#define STORE_OAM \
 625	STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw); \
 626	gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
 627	gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
 628
 629#define STORE_CART \
 630	wait += waitstatesRegion[address >> BASE_OFFSET]; \
 631	GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
 632
 633#define STORE_SRAM \
 634	GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
 635
 636#define STORE_BAD \
 637	GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
 638
 639void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
 640	struct GBA* gba = (struct GBA*) cpu->master;
 641	struct GBAMemory* memory = &gba->memory;
 642	int wait = 0;
 643	char* waitstatesRegion = memory->waitstatesNonseq32;
 644
 645	switch (address >> BASE_OFFSET) {
 646	case REGION_WORKING_RAM:
 647		STORE_WORKING_RAM;
 648		break;
 649	case REGION_WORKING_IRAM:
 650		STORE_WORKING_IRAM
 651		break;
 652	case REGION_IO:
 653		STORE_IO;
 654		break;
 655	case REGION_PALETTE_RAM:
 656		STORE_PALETTE_RAM;
 657		break;
 658	case REGION_VRAM:
 659		STORE_VRAM;
 660		break;
 661	case REGION_OAM:
 662		STORE_OAM;
 663		break;
 664	case REGION_CART0:
 665	case REGION_CART0_EX:
 666	case REGION_CART1:
 667	case REGION_CART1_EX:
 668	case REGION_CART2:
 669	case REGION_CART2_EX:
 670		STORE_CART;
 671		break;
 672	case REGION_CART_SRAM:
 673	case REGION_CART_SRAM_MIRROR:
 674		STORE_SRAM;
 675		break;
 676	default:
 677		STORE_BAD;
 678		break;
 679	}
 680
 681	if (cycleCounter) {
 682		*cycleCounter += 1 + wait;
 683	}
 684}
 685
 686void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
 687	struct GBA* gba = (struct GBA*) cpu->master;
 688	struct GBAMemory* memory = &gba->memory;
 689	int wait = 0;
 690
 691	switch (address >> BASE_OFFSET) {
 692	case REGION_WORKING_RAM:
 693		STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 694		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 695		break;
 696	case REGION_WORKING_IRAM:
 697		STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 698		break;
 699	case REGION_IO:
 700		GBAIOWrite(gba, address & (SIZE_IO - 1), value);
 701		break;
 702	case REGION_PALETTE_RAM:
 703		STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 704		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 705		break;
 706	case REGION_VRAM:
 707		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 708			STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 709		} else {
 710			STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 711		}
 712		break;
 713	case REGION_OAM:
 714		STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 715		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 716		break;
 717	case REGION_CART0:
 718		if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFF)) {
 719			uint32_t reg = address & 0xFFFFFF;
 720			GBAHardwareGPIOWrite(&memory->hw, reg, value);
 721		} else {
 722			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
 723		}
 724		break;
 725	case REGION_CART2_EX:
 726		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 727			GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
 728			GBASavedataInitEEPROM(&memory->savedata);
 729		}
 730		GBASavedataWriteEEPROM(&memory->savedata, value, 1);
 731		break;
 732	case REGION_CART_SRAM:
 733	case REGION_CART_SRAM_MIRROR:
 734		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
 735		break;
 736	default:
 737		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
 738		break;
 739	}
 740
 741	if (cycleCounter) {
 742		*cycleCounter += 1 + wait;
 743	}
 744}
 745
 746void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
 747	struct GBA* gba = (struct GBA*) cpu->master;
 748	struct GBAMemory* memory = &gba->memory;
 749	int wait = 0;
 750
 751	switch (address >> BASE_OFFSET) {
 752	case REGION_WORKING_RAM:
 753		((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
 754		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 755		break;
 756	case REGION_WORKING_IRAM:
 757		((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
 758		break;
 759	case REGION_IO:
 760		GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
 761		break;
 762	case REGION_PALETTE_RAM:
 763		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
 764		break;
 765	case REGION_VRAM:
 766		if (address >= 0x06018000) {
 767			// TODO: check BG mode
 768			GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
 769			break;
 770		}
 771		((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
 772		((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
 773		break;
 774	case REGION_OAM:
 775		GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
 776		break;
 777	case REGION_CART0:
 778		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
 779		break;
 780	case REGION_CART_SRAM:
 781	case REGION_CART_SRAM_MIRROR:
 782		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 783			if (address == SAVEDATA_FLASH_BASE) {
 784				GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
 785				GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
 786			} else {
 787				GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
 788				GBASavedataInitSRAM(&memory->savedata);
 789			}
 790		}
 791		if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
 792			GBASavedataWriteFlash(&memory->savedata, address, value);
 793		} else if (memory->savedata.type == SAVEDATA_SRAM) {
 794			memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
 795		} else if (memory->hw.devices & HW_TILT) {
 796			GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
 797		} else {
 798			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 799		}
 800		wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
 801		break;
 802	default:
 803		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
 804		break;
 805	}
 806
 807	if (cycleCounter) {
 808		*cycleCounter += 1 + wait;
 809	}
 810}
 811
 812void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
 813	struct GBA* gba = (struct GBA*) cpu->master;
 814	struct GBAMemory* memory = &gba->memory;
 815	int32_t oldValue = -1;
 816
 817	switch (address >> BASE_OFFSET) {
 818	case REGION_WORKING_RAM:
 819		LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
 820		STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 821		break;
 822	case REGION_WORKING_IRAM:
 823		LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 824		STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 825		break;
 826	case REGION_IO:
 827		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
 828		break;
 829	case REGION_PALETTE_RAM:
 830		LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 831		STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 832		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 833		gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
 834		break;
 835	case REGION_VRAM:
 836		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 837			LOAD_32(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
 838			STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
 839		} else {
 840			LOAD_32(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
 841			STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
 842		}
 843		break;
 844	case REGION_OAM:
 845		LOAD_32(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
 846		STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 847		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 848		gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 1)) + 2) >> 1);
 849		break;
 850	case REGION_CART0:
 851	case REGION_CART0_EX:
 852	case REGION_CART1:
 853	case REGION_CART1_EX:
 854	case REGION_CART2:
 855	case REGION_CART2_EX:
 856		_pristineCow(gba);
 857		if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
 858			gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
 859		}
 860		LOAD_32(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
 861		STORE_32(value, address & (SIZE_CART0 - 1), gba->memory.rom);
 862		break;
 863	case REGION_CART_SRAM:
 864	case REGION_CART_SRAM_MIRROR:
 865		if (memory->savedata.type == SAVEDATA_SRAM) {
 866			LOAD_32(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 867			STORE_32(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 868		} else {
 869			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 870		}
 871		break;
 872	default:
 873		GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
 874		break;
 875	}
 876	if (old) {
 877		*old = oldValue;
 878	}
 879}
 880
 881void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
 882	struct GBA* gba = (struct GBA*) cpu->master;
 883	struct GBAMemory* memory = &gba->memory;
 884	int16_t oldValue = -1;
 885
 886	switch (address >> BASE_OFFSET) {
 887	case REGION_WORKING_RAM:
 888		LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
 889		STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 890		break;
 891	case REGION_WORKING_IRAM:
 892		LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 893		STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 894		break;
 895	case REGION_IO:
 896		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
 897		break;
 898	case REGION_PALETTE_RAM:
 899		LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 900		STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 901		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 902		break;
 903	case REGION_VRAM:
 904		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 905			LOAD_16(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
 906			STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 907		} else {
 908			LOAD_16(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
 909			STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 910		}
 911		break;
 912	case REGION_OAM:
 913		LOAD_16(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
 914		STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 915		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 916		break;
 917	case REGION_CART0:
 918	case REGION_CART0_EX:
 919	case REGION_CART1:
 920	case REGION_CART1_EX:
 921	case REGION_CART2:
 922	case REGION_CART2_EX:
 923		_pristineCow(gba);
 924		if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
 925			gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
 926		}
 927		LOAD_16(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
 928		STORE_16(value, address & (SIZE_CART0 - 1), gba->memory.rom);
 929		break;
 930	case REGION_CART_SRAM:
 931	case REGION_CART_SRAM_MIRROR:
 932		if (memory->savedata.type == SAVEDATA_SRAM) {
 933			LOAD_16(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 934			STORE_16(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 935		} else {
 936			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 937		}
 938		break;
 939	default:
 940		GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
 941		break;
 942	}
 943	if (old) {
 944		*old = oldValue;
 945	}
 946}
 947
 948void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
 949	struct GBA* gba = (struct GBA*) cpu->master;
 950	struct GBAMemory* memory = &gba->memory;
 951	int8_t oldValue = -1;
 952
 953	switch (address >> BASE_OFFSET) {
 954	case REGION_WORKING_RAM:
 955		oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
 956		((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
 957		break;
 958	case REGION_WORKING_IRAM:
 959		oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
 960		((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
 961		break;
 962	case REGION_IO:
 963		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
 964		break;
 965	case REGION_PALETTE_RAM:
 966		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
 967		break;
 968	case REGION_VRAM:
 969		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
 970		break;
 971	case REGION_OAM:
 972		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
 973		break;
 974	case REGION_CART0:
 975	case REGION_CART0_EX:
 976	case REGION_CART1:
 977	case REGION_CART1_EX:
 978	case REGION_CART2:
 979	case REGION_CART2_EX:
 980		_pristineCow(gba);
 981		if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
 982			gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
 983		}
 984		oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
 985		((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
 986		break;
 987	case REGION_CART_SRAM:
 988	case REGION_CART_SRAM_MIRROR:
 989		if (memory->savedata.type == SAVEDATA_SRAM) {
 990			oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
 991			((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
 992		} else {
 993			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 994		}
 995		break;
 996	default:
 997		GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
 998		break;
 999	}
1000	if (old) {
1001		*old = oldValue;
1002	}
1003}
1004
1005#define LDM_LOOP(LDM) \
1006	for (i = 0; i < 16; i += 4) { \
1007		if (UNLIKELY(mask & (1 << i))) { \
1008			LDM; \
1009			waitstatesRegion = memory->waitstatesSeq32; \
1010			cpu->gprs[i] = value; \
1011			++wait; \
1012			address += 4; \
1013		} \
1014		if (UNLIKELY(mask & (2 << i))) { \
1015			LDM; \
1016			waitstatesRegion = memory->waitstatesSeq32; \
1017			cpu->gprs[i + 1] = value; \
1018			++wait; \
1019			address += 4; \
1020		} \
1021		if (UNLIKELY(mask & (4 << i))) { \
1022			LDM; \
1023			waitstatesRegion = memory->waitstatesSeq32; \
1024			cpu->gprs[i + 2] = value; \
1025			++wait; \
1026			address += 4; \
1027		} \
1028		if (UNLIKELY(mask & (8 << i))) { \
1029			LDM; \
1030			waitstatesRegion = memory->waitstatesSeq32; \
1031			cpu->gprs[i + 3] = value; \
1032			++wait; \
1033			address += 4; \
1034		} \
1035	}
1036
1037uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1038	struct GBA* gba = (struct GBA*) cpu->master;
1039	struct GBAMemory* memory = &gba->memory;
1040	uint32_t value;
1041	int wait = 0;
1042	char* waitstatesRegion = memory->waitstatesNonseq32;
1043
1044	int i;
1045	int offset = 4;
1046	int popcount = 0;
1047	if (direction & LSM_D) {
1048		offset = -4;
1049		popcount = _popcount32(mask);
1050		address -= (popcount << 2) - 4;
1051	}
1052
1053	if (direction & LSM_B) {
1054		address += offset;
1055	}
1056
1057	uint32_t addressMisalign = address & 0x3;
1058	address &= 0xFFFFFFFC;
1059
1060	switch (address >> BASE_OFFSET) {
1061	case REGION_BIOS:
1062		LDM_LOOP(LOAD_BIOS);
1063		break;
1064	case REGION_WORKING_RAM:
1065		LDM_LOOP(LOAD_WORKING_RAM);
1066		break;
1067	case REGION_WORKING_IRAM:
1068		LDM_LOOP(LOAD_WORKING_IRAM);
1069		break;
1070	case REGION_IO:
1071		LDM_LOOP(LOAD_IO);
1072		break;
1073	case REGION_PALETTE_RAM:
1074		LDM_LOOP(LOAD_PALETTE_RAM);
1075		break;
1076	case REGION_VRAM:
1077		LDM_LOOP(LOAD_VRAM);
1078		break;
1079	case REGION_OAM:
1080		LDM_LOOP(LOAD_OAM);
1081		break;
1082	case REGION_CART0:
1083	case REGION_CART0_EX:
1084	case REGION_CART1:
1085	case REGION_CART1_EX:
1086	case REGION_CART2:
1087	case REGION_CART2_EX:
1088		LDM_LOOP(LOAD_CART);
1089		break;
1090	case REGION_CART_SRAM:
1091	case REGION_CART_SRAM_MIRROR:
1092		LDM_LOOP(LOAD_SRAM);
1093		break;
1094	default:
1095		LDM_LOOP(LOAD_BAD);
1096		break;
1097	}
1098
1099	if (cycleCounter) {
1100		*cycleCounter += wait;
1101	}
1102
1103	if (direction & LSM_B) {
1104		address -= offset;
1105	}
1106
1107	if (direction & LSM_D) {
1108		address -= (popcount << 2) + 4;
1109	}
1110
1111	return address | addressMisalign;
1112}
1113
1114#define STM_LOOP(STM) \
1115	for (i = 0; i < 16; i += 4) { \
1116		if (UNLIKELY(mask & (1 << i))) { \
1117			value = cpu->gprs[i]; \
1118			STM; \
1119			waitstatesRegion = memory->waitstatesSeq32; \
1120			++wait; \
1121			address += 4; \
1122		} \
1123		if (UNLIKELY(mask & (2 << i))) { \
1124			value = cpu->gprs[i + 1]; \
1125			STM; \
1126			waitstatesRegion = memory->waitstatesSeq32; \
1127			++wait; \
1128			address += 4; \
1129		} \
1130		if (UNLIKELY(mask & (4 << i))) { \
1131			value = cpu->gprs[i + 2]; \
1132			STM; \
1133			waitstatesRegion = memory->waitstatesSeq32; \
1134			++wait; \
1135			address += 4; \
1136		} \
1137		if (UNLIKELY(mask & (8 << i))) { \
1138			value = cpu->gprs[i + 3]; \
1139			STM; \
1140			waitstatesRegion = memory->waitstatesSeq32; \
1141			++wait; \
1142			address += 4; \
1143		} \
1144	}
1145
1146uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1147	struct GBA* gba = (struct GBA*) cpu->master;
1148	struct GBAMemory* memory = &gba->memory;
1149	uint32_t value;
1150	int wait = 0;
1151	char* waitstatesRegion = memory->waitstatesNonseq32;
1152
1153	int i;
1154	int offset = 4;
1155	int popcount = 0;
1156	if (direction & LSM_D) {
1157		offset = -4;
1158		popcount = _popcount32(mask);
1159		address -= (popcount << 2) - 4;
1160	}
1161
1162	if (direction & LSM_B) {
1163		address += offset;
1164	}
1165
1166	uint32_t addressMisalign = address & 0x3;
1167	address &= 0xFFFFFFFC;
1168
1169	switch (address >> BASE_OFFSET) {
1170	case REGION_WORKING_RAM:
1171		STM_LOOP(STORE_WORKING_RAM);
1172		break;
1173	case REGION_WORKING_IRAM:
1174		STM_LOOP(STORE_WORKING_IRAM);
1175		break;
1176	case REGION_IO:
1177		STM_LOOP(STORE_IO);
1178		break;
1179	case REGION_PALETTE_RAM:
1180		STM_LOOP(STORE_PALETTE_RAM);
1181		break;
1182	case REGION_VRAM:
1183		STM_LOOP(STORE_VRAM);
1184		break;
1185	case REGION_OAM:
1186		STM_LOOP(STORE_OAM);
1187		break;
1188	case REGION_CART0:
1189	case REGION_CART0_EX:
1190	case REGION_CART1:
1191	case REGION_CART1_EX:
1192	case REGION_CART2:
1193	case REGION_CART2_EX:
1194		STM_LOOP(STORE_CART);
1195		break;
1196	case REGION_CART_SRAM:
1197	case REGION_CART_SRAM_MIRROR:
1198		STM_LOOP(STORE_SRAM);
1199		break;
1200	default:
1201		STM_LOOP(STORE_BAD);
1202		break;
1203	}
1204
1205	if (cycleCounter) {
1206		*cycleCounter += wait;
1207	}
1208
1209	if (direction & LSM_B) {
1210		address -= offset;
1211	}
1212
1213	if (direction & LSM_D) {
1214		address -= (popcount << 2) + 4;
1215	}
1216
1217	return address | addressMisalign;
1218}
1219
1220void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1221	struct GBAMemory* memory = &gba->memory;
1222	struct ARMCore* cpu = gba->cpu;
1223	int sram = parameters & 0x0003;
1224	int ws0 = (parameters & 0x000C) >> 2;
1225	int ws0seq = (parameters & 0x0010) >> 4;
1226	int ws1 = (parameters & 0x0060) >> 5;
1227	int ws1seq = (parameters & 0x0080) >> 7;
1228	int ws2 = (parameters & 0x0300) >> 8;
1229	int ws2seq = (parameters & 0x0400) >> 10;
1230	int prefetch = parameters & 0x4000;
1231
1232	memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] =  GBA_ROM_WAITSTATES[sram];
1233	memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1234	memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1235	memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1236
1237	memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1238	memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1239	memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1240
1241	memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1242	memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1243	memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1244
1245	memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1246	memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1247	memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1248
1249	memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1250	memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1251	memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1252
1253	if (!prefetch) {
1254		memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
1255		memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
1256		memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
1257
1258		memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
1259		memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
1260		memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
1261
1262		memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
1263		memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
1264		memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
1265
1266		memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
1267		memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
1268		memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
1269	} else {
1270		memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
1271		memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
1272		memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
1273
1274		memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
1275		memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
1276		memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
1277
1278		memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
1279		memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
1280		memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
1281
1282		memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
1283		memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
1284		memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
1285	}
1286
1287	cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
1288	cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
1289
1290	cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
1291	cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
1292
1293	cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1294	cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1295}
1296
1297void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1298	struct GBAMemory* memory = &gba->memory;
1299	memory->dma[dma].source = address & 0x0FFFFFFE;
1300}
1301
1302void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1303	struct GBAMemory* memory = &gba->memory;
1304	memory->dma[dma].dest = address & 0x0FFFFFFE;
1305}
1306
1307void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1308	struct GBAMemory* memory = &gba->memory;
1309	memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1310}
1311
1312uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1313	struct GBAMemory* memory = &gba->memory;
1314	struct GBADMA* currentDma = &memory->dma[dma];
1315	int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1316	int oldTiming = GBADMARegisterGetTiming(currentDma->reg);
1317	int newTiming = GBADMARegisterGetTiming(control);
1318	// This is probably a huge hack...verify what this does on hardware
1319	if (oldTiming && oldTiming != DMA_TIMING_CUSTOM && oldTiming != newTiming) {
1320		wasEnabled = false;
1321	}
1322	currentDma->reg = control;
1323
1324	if (GBADMARegisterIsDRQ(currentDma->reg)) {
1325		GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1326	}
1327
1328	if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1329		currentDma->nextSource = currentDma->source;
1330		currentDma->nextDest = currentDma->dest;
1331		currentDma->nextCount = currentDma->count;
1332		GBAMemoryScheduleDMA(gba, dma, currentDma);
1333	}
1334	// If the DMA has already occurred, this value might have changed since the function started
1335	return currentDma->reg;
1336};
1337
1338void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1339	struct ARMCore* cpu = gba->cpu;
1340	switch (GBADMARegisterGetTiming(info->reg)) {
1341	case DMA_TIMING_NOW:
1342		info->nextEvent = cpu->cycles;
1343		GBAMemoryUpdateDMAs(gba, 0);
1344		break;
1345	case DMA_TIMING_HBLANK:
1346		// Handled implicitly
1347		info->nextEvent = INT_MAX;
1348		break;
1349	case DMA_TIMING_VBLANK:
1350		// Handled implicitly
1351		info->nextEvent = INT_MAX;
1352		break;
1353	case DMA_TIMING_CUSTOM:
1354		info->nextEvent = INT_MAX;
1355		switch (number) {
1356		case 0:
1357			GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1358			break;
1359		case 1:
1360		case 2:
1361			GBAAudioScheduleFifoDma(&gba->audio, number, info);
1362			break;
1363		case 3:
1364			// GBAVideoScheduleVCaptureDma(dma, info);
1365			break;
1366		}
1367	}
1368}
1369
1370void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1371	struct GBAMemory* memory = &gba->memory;
1372	struct GBADMA* dma;
1373	int i;
1374	for (i = 0; i < 4; ++i) {
1375		dma = &memory->dma[i];
1376		if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1377			dma->nextEvent = cycles;
1378		}
1379	}
1380	GBAMemoryUpdateDMAs(gba, 0);
1381}
1382
1383void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1384	struct GBAMemory* memory = &gba->memory;
1385	struct GBADMA* dma;
1386	int i;
1387	for (i = 0; i < 4; ++i) {
1388		dma = &memory->dma[i];
1389		if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1390			dma->nextEvent = cycles;
1391		}
1392	}
1393	GBAMemoryUpdateDMAs(gba, 0);
1394}
1395
1396int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1397	struct GBAMemory* memory = &gba->memory;
1398	if (memory->nextDMA == INT_MAX) {
1399		return INT_MAX;
1400	}
1401	memory->nextDMA -= cycles;
1402	memory->eventDiff += cycles;
1403	if (memory->nextDMA <= 0) {
1404		struct GBADMA* dma = &memory->dma[memory->activeDMA];
1405		GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1406		GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1407		memory->eventDiff = 0;
1408	}
1409	return memory->nextDMA;
1410}
1411
1412void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1413	int i;
1414	struct GBAMemory* memory = &gba->memory;
1415	struct ARMCore* cpu = gba->cpu;
1416	memory->activeDMA = -1;
1417	memory->nextDMA = INT_MAX;
1418	for (i = 3; i >= 0; --i) {
1419		struct GBADMA* dma = &memory->dma[i];
1420		if (dma->nextEvent != INT_MAX) {
1421			dma->nextEvent -= cycles;
1422			if (GBADMARegisterIsEnable(dma->reg)) {
1423				memory->activeDMA = i;
1424				memory->nextDMA = dma->nextEvent;
1425			}
1426		}
1427	}
1428	if (memory->nextDMA < cpu->nextEvent) {
1429		cpu->nextEvent = memory->nextDMA;
1430	}
1431}
1432
1433void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1434	struct GBAMemory* memory = &gba->memory;
1435	struct ARMCore* cpu = gba->cpu;
1436	uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1437	int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1438	int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1439	int32_t wordsRemaining = info->nextCount;
1440	uint32_t source = info->nextSource;
1441	uint32_t dest = info->nextDest;
1442	uint32_t sourceRegion = source >> BASE_OFFSET;
1443	uint32_t destRegion = dest >> BASE_OFFSET;
1444	int32_t cycles = 2;
1445
1446	if (source == info->source) {
1447		// TODO: support 4 cycles for ROM access
1448		cycles += 2;
1449		if (width == 4) {
1450			cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1451			source &= 0xFFFFFFFC;
1452			dest &= 0xFFFFFFFC;
1453		} else {
1454			cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1455		}
1456	} else {
1457		if (width == 4) {
1458			cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1459		} else {
1460			cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1461		}
1462	}
1463
1464	gba->performingDMA = true;
1465	int32_t word;
1466	if (width == 4) {
1467		word = cpu->memory.load32(cpu, source, 0);
1468		gba->bus = word;
1469		cpu->memory.store32(cpu, dest, word, 0);
1470		source += sourceOffset;
1471		dest += destOffset;
1472		--wordsRemaining;
1473	} else {
1474		if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1475			word = GBASavedataReadEEPROM(&memory->savedata);
1476			gba->bus = word | (word << 16);
1477			cpu->memory.store16(cpu, dest, word, 0);
1478			source += sourceOffset;
1479			dest += destOffset;
1480			--wordsRemaining;
1481		} else if (destRegion == REGION_CART2_EX) {
1482			if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1483				GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1484				GBASavedataInitEEPROM(&memory->savedata);
1485			}
1486			word = cpu->memory.load16(cpu, source, 0);
1487			gba->bus = word | (word << 16);
1488			GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1489			source += sourceOffset;
1490			dest += destOffset;
1491			--wordsRemaining;
1492		} else {
1493			word = cpu->memory.load16(cpu, source, 0);
1494			gba->bus = word | (word << 16);
1495			cpu->memory.store16(cpu, dest, word, 0);
1496			source += sourceOffset;
1497			dest += destOffset;
1498			--wordsRemaining;
1499		}
1500	}
1501	gba->performingDMA = false;
1502
1503	if (!wordsRemaining) {
1504		if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1505			info->reg = GBADMARegisterClearEnable(info->reg);
1506			info->nextEvent = INT_MAX;
1507
1508			// Clear the enable bit in memory
1509			memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1510		} else {
1511			info->nextCount = info->count;
1512			if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1513				info->nextDest = info->dest;
1514			}
1515			GBAMemoryScheduleDMA(gba, number, info);
1516		}
1517		if (GBADMARegisterIsDoIRQ(info->reg)) {
1518			GBARaiseIRQ(gba, IRQ_DMA0 + number);
1519		}
1520	} else {
1521		info->nextDest = dest;
1522		info->nextCount = wordsRemaining;
1523	}
1524	info->nextSource = source;
1525
1526	if (info->nextEvent != INT_MAX) {
1527		info->nextEvent += cycles;
1528	}
1529	cpu->cycles += cycles;
1530}
1531
1532void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1533	memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1534	memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1535}
1536
1537void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1538	memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1539	memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1540}
1541
1542uint32_t _popcount32(unsigned bits) {
1543	bits = bits - ((bits >> 1) & 0x55555555);
1544	bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1545	return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1546}
1547
1548void _pristineCow(struct GBA* gba) {
1549	if (gba->memory.rom != gba->pristineRom) {
1550		return;
1551	}
1552	gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1553	memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1554	memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1555}