1#ifndef ARM_DECODER_H
  2#define ARM_DECODER_H
  3
  4#include "arm.h"
  5
  6// Bit 0: a register is involved with this operand
  7// Bit 1: an immediate is invovled with this operand
  8// Bit 2: a memory access is invovled with this operand
  9// Bit 3: the destination of this operand is affected by this opcode
 10// Bit 4: this operand is shifted by a register
 11// Bit 5: this operand is shifted by an immediate
 12enum ARMOperandFormat {
 13	ARM_OPERAND_NONE =               0x00000000,
 14	ARM_OPERAND_REGISTER_1 =         0x00000001,
 15	ARM_OPERAND_IMMEDIATE_1 =        0x00000002,
 16	ARM_OPERAND_MEMORY_1 =           0x00000004,
 17	ARM_OPERAND_AFFECTED_1 =         0x00000008,
 18	ARM_OPERAND_SHIFT_REGISTER_1 =   0x00000010,
 19	ARM_OPERAND_SHIFT_IMMEDIATE_1 =  0x00000020,
 20	ARM_OPERAND_1 =                  0x000000FF,
 21
 22	ARM_OPERAND_REGISTER_2 =         0x00000100,
 23	ARM_OPERAND_IMMEDIATE_2 =        0x00000200,
 24	ARM_OPERAND_MEMORY_2 =           0x00000400,
 25	ARM_OPERAND_AFFECTED_2 =         0x00000800,
 26	ARM_OPERAND_SHIFT_REGISTER_2 =   0x00001000,
 27	ARM_OPERAND_SHIFT_IMMEDIATE_2 =  0x00002000,
 28	ARM_OPERAND_2 =                  0x0000FF00,
 29
 30	ARM_OPERAND_REGISTER_3 =         0x00010000,
 31	ARM_OPERAND_IMMEDIATE_3 =        0x00020000,
 32	ARM_OPERAND_MEMORY_3 =           0x00040000,
 33	ARM_OPERAND_AFFECTED_3 =         0x00080000,
 34	ARM_OPERAND_SHIFT_REGISTER_3 =   0x00100000,
 35	ARM_OPERAND_SHIFT_IMMEDIATE_3 =  0x00200000,
 36	ARM_OPERAND_3 =                  0x00FF0000,
 37
 38	ARM_OPERAND_REGISTER_4 =         0x01000000,
 39	ARM_OPERAND_IMMEDIATE_4 =        0x02000000,
 40	ARM_OPERAND_MEMORY_4 =           0x04000000,
 41	ARM_OPERAND_AFFECTED_4 =         0x08000000,
 42	ARM_OPERAND_SHIFT_REGISTER_4 =   0x10000000,
 43	ARM_OPERAND_SHIFT_IMMEDIATE_4 =  0x20000000,
 44	ARM_OPERAND_4 =                  0xFF000000
 45};
 46
 47enum ARMMemoryFormat {
 48	ARM_MEMORY_REGISTER_BASE =    0x0001,
 49	ARM_MEMORY_IMMEDIATE_OFFSET = 0x0002,
 50	ARM_MEMORY_REGISTER_OFFSET  = 0x0004,
 51	ARM_MEMORY_SHIFTED_OFFSET =   0x0008,
 52	ARM_MEMORY_PRE_INCREMENT =    0x0010,
 53	ARM_MEMORY_POST_INCREMENT =   0x0020,
 54	ARM_MEMORY_OFFSET_SUBTRACT =  0x0040,
 55	ARM_MEMORY_WRITEBACK =        0x0080,
 56	ARM_MEMORY_DECREMENT_AFTER =  0x0000,
 57	ARM_MEMORY_INCREMENT_AFTER =  0x0100,
 58	ARM_MEMORY_DECREMENT_BEFORE = 0x0200,
 59	ARM_MEMORY_INCREMENT_BEFORE = 0x0300,
 60};
 61
 62#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x7)
 63
 64enum ARMCondition {
 65	ARM_CONDITION_EQ = 0x0,
 66	ARM_CONDITION_NE = 0x1,
 67	ARM_CONDITION_CS = 0x2,
 68	ARM_CONDITION_CC = 0x3,
 69	ARM_CONDITION_MI = 0x4,
 70	ARM_CONDITION_PL = 0x5,
 71	ARM_CONDITION_VS = 0x6,
 72	ARM_CONDITION_VC = 0x7,
 73	ARM_CONDITION_HI = 0x8,
 74	ARM_CONDITION_LS = 0x9,
 75	ARM_CONDITION_GE = 0xA,
 76	ARM_CONDITION_LT = 0xB,
 77	ARM_CONDITION_GT = 0xC,
 78	ARM_CONDITION_LE = 0xD,
 79	ARM_CONDITION_AL = 0xE,
 80	ARM_CONDITION_NV = 0xF
 81};
 82
 83enum ARMShifterOperation {
 84	ARM_SHIFT_NONE = 0,
 85	ARM_SHIFT_LSL,
 86	ARM_SHIFT_LSR,
 87	ARM_SHIFT_ASR,
 88	ARM_SHIFT_ROR,
 89	ARM_SHIFT_RRX
 90};
 91
 92union ARMOperand {
 93	struct {
 94		uint8_t reg;
 95		enum ARMShifterOperation shifterOp;
 96		union {
 97			uint8_t shifterReg;
 98			uint8_t shifterImm;
 99		};
100	};
101	int32_t immediate;
102};
103
104enum ARMMemoryAccessType {
105	ARM_ACCESS_WORD = 4,
106	ARM_ACCESS_HALFWORD = 2,
107	ARM_ACCESS_SIGNED_HALFWORD = 10,
108	ARM_ACCESS_BYTE = 1,
109	ARM_ACCESS_SIGNED_BYTE = 9,
110	ARM_ACCESS_TRANSLATED_WORD = 20,
111	ARM_ACCESS_TRANSLATED_BYTE = 17
112};
113
114struct ARMMemoryAccess {
115	uint8_t baseReg;
116	uint16_t format;
117	union ARMOperand offset;
118	enum ARMMemoryAccessType width;
119};
120
121enum ARMMnemonic {
122	ARM_MN_ILL = 0,
123	ARM_MN_ADC,
124	ARM_MN_ADD,
125	ARM_MN_AND,
126	ARM_MN_ASR,
127	ARM_MN_B,
128	ARM_MN_BIC,
129	ARM_MN_BKPT,
130	ARM_MN_BL,
131	ARM_MN_BLH,
132	ARM_MN_BX,
133	ARM_MN_CMN,
134	ARM_MN_CMP,
135	ARM_MN_EOR,
136	ARM_MN_LDM,
137	ARM_MN_LDR,
138	ARM_MN_LSL,
139	ARM_MN_LSR,
140	ARM_MN_MLA,
141	ARM_MN_MOV,
142	ARM_MN_MRS,
143	ARM_MN_MSR,
144	ARM_MN_MUL,
145	ARM_MN_MVN,
146	ARM_MN_NEG,
147	ARM_MN_ORR,
148	ARM_MN_ROR,
149	ARM_MN_RSB,
150	ARM_MN_RSC,
151	ARM_MN_SBC,
152	ARM_MN_SMLAL,
153	ARM_MN_SMULL,
154	ARM_MN_STM,
155	ARM_MN_STR,
156	ARM_MN_SUB,
157	ARM_MN_SWI,
158	ARM_MN_SWP,
159	ARM_MN_TEQ,
160	ARM_MN_TST,
161	ARM_MN_UMLAL,
162	ARM_MN_UMULL,
163
164	ARM_MN_MAX
165};
166
167enum {
168	ARM_CPSR = 16,
169	ARM_SPSR = 17
170};
171
172struct ARMInstructionInfo {
173	enum ExecutionMode execMode;
174	uint32_t opcode;
175	enum ARMMnemonic mnemonic;
176	union ARMOperand op1;
177	union ARMOperand op2;
178	union ARMOperand op3;
179	union ARMOperand op4;
180	struct ARMMemoryAccess memory;
181	int operandFormat;
182	int branches;
183	int traps;
184	int affectsCPSR;
185	int condition;
186	int sDataCycles;
187	int nDataCycles;
188	int sInstructionCycles;
189	int nInstructionCycles;
190	int iCycles;
191	int cCycles;
192};
193
194void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
195void ARMDecodeThumb(uint16_t opcode, struct ARMInstructionInfo* info);
196int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, int blen);
197
198#endif