src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13
14static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
17static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
18static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
19
20void GBAMemoryInit(struct GBAMemory* memory) {
21 memory->d.load32 = GBALoad32;
22 memory->d.load16 = GBALoad16;
23 memory->d.loadU16 = GBALoadU16;
24 memory->d.load8 = GBALoad8;
25 memory->d.loadU8 = GBALoadU8;
26 memory->d.store32 = GBAStore32;
27 memory->d.store16 = GBAStore16;
28 memory->d.store8 = GBAStore8;
29
30 memory->bios = (uint32_t*) hleBios;
31 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
32 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
33 memory->rom = 0;
34 memset(memory->io, 0, sizeof(memory->io));
35 memset(memory->dma, 0, sizeof(memory->dma));
36
37 if (!memory->wram || !memory->iwram) {
38 GBAMemoryDeinit(memory);
39 memory->p->errno = GBA_OUT_OF_MEMORY;
40 memory->p->errstr = GBA_CANNOT_MMAP;
41 }
42
43 int i;
44 for (i = 0; i < 16; ++i) {
45 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
46 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
47 memory->waitstates32[i] = GBA_BASE_WAITSTATES[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
48 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
49 }
50 for (; i < 256; ++i) {
51 memory->waitstates16[i] = 0;
52 memory->waitstatesSeq16[i] = 0;
53 memory->waitstates32[i] = 0;
54 memory->waitstatesSeq32[i] = 0;
55 }
56
57 memory->activeRegion = 0;
58 memory->d.activeRegion = 0;
59 memory->d.activeMask = 0;
60 memory->d.setActiveRegion = GBASetActiveRegion;
61 memory->d.activePrefetchCycles32 = 0;
62 memory->d.activePrefetchCycles16 = 0;
63}
64
65void GBAMemoryDeinit(struct GBAMemory* memory) {
66 munmap(memory->wram, SIZE_WORKING_RAM);
67 munmap(memory->iwram, SIZE_WORKING_IRAM);
68}
69
70static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
71 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
72
73 memory->activePrefetchCycles32 = gbaMemory->waitstates32[address >> BASE_OFFSET];
74 memory->activePrefetchCycles16 = gbaMemory->waitstates16[address >> BASE_OFFSET];
75 gbaMemory->activeRegion = address >> BASE_OFFSET;
76 switch (address & ~OFFSET_MASK) {
77 case BASE_BIOS:
78 memory->activeRegion = gbaMemory->bios;
79 memory->activeMask = SIZE_BIOS - 1;
80 break;
81 case BASE_WORKING_RAM:
82 memory->activeRegion = gbaMemory->wram;
83 memory->activeMask = SIZE_WORKING_RAM - 1;
84 break;
85 case BASE_WORKING_IRAM:
86 memory->activeRegion = gbaMemory->iwram;
87 memory->activeMask = SIZE_WORKING_IRAM - 1;
88 break;
89 case BASE_CART0:
90 case BASE_CART0_EX:
91 case BASE_CART1:
92 case BASE_CART1_EX:
93 case BASE_CART2:
94 case BASE_CART2_EX:
95 memory->activeRegion = gbaMemory->rom;
96 memory->activeMask = SIZE_CART0 - 1;
97 break;
98 default:
99 memory->activeRegion = 0;
100 memory->activeMask = 0;
101 break;
102 }
103}
104
105int32_t GBALoad32(struct ARMMemory* memory, uint32_t address) {
106 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
107
108 switch (address & ~OFFSET_MASK) {
109 case BASE_BIOS:
110 break;
111 case BASE_WORKING_RAM:
112 return gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
113 case BASE_WORKING_IRAM:
114 return gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
115 case BASE_IO:
116 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1)) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
117 case BASE_PALETTE_RAM:
118 return ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2];
119 case BASE_VRAM:
120 return ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2];
121 case BASE_OAM:
122 break;
123 case BASE_CART0:
124 case BASE_CART0_EX:
125 case BASE_CART1:
126 case BASE_CART1_EX:
127 case BASE_CART2:
128 case BASE_CART2_EX:
129 return gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
130 case BASE_CART_SRAM:
131 break;
132 default:
133 break;
134 }
135
136 return 0;
137}
138
139int16_t GBALoad16(struct ARMMemory* memory, uint32_t address) {
140 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
141
142 switch (address & ~OFFSET_MASK) {
143 case BASE_BIOS:
144 break;
145 case BASE_WORKING_RAM:
146 return ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
147 case BASE_WORKING_IRAM:
148 return ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
149 case BASE_IO:
150 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
151 case BASE_PALETTE_RAM:
152 return gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
153 case BASE_VRAM:
154 return gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
155 case BASE_OAM:
156 break;
157 case BASE_CART0:
158 case BASE_CART0_EX:
159 case BASE_CART1:
160 case BASE_CART1_EX:
161 case BASE_CART2:
162 case BASE_CART2_EX:
163 return ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
164 case BASE_CART_SRAM:
165 break;
166 default:
167 break;
168 }
169
170 return 0;
171}
172
173uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address) {
174 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
175
176 switch (address & ~OFFSET_MASK) {
177 case BASE_BIOS:
178 break;
179 case BASE_WORKING_RAM:
180 return ((uint16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
181 case BASE_WORKING_IRAM:
182 return ((uint16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
183 case BASE_IO:
184 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
185 case BASE_PALETTE_RAM:
186 return gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
187 case BASE_VRAM:
188 return gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
189 case BASE_OAM:
190 break;
191 case BASE_CART0:
192 case BASE_CART0_EX:
193 case BASE_CART1:
194 case BASE_CART1_EX:
195 case BASE_CART2:
196 case BASE_CART2_EX:
197 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
198 case BASE_CART_SRAM:
199 break;
200 default:
201 break;
202 }
203
204 return 0;
205}
206
207int8_t GBALoad8(struct ARMMemory* memory, uint32_t address) {
208 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
209
210 switch (address & ~OFFSET_MASK) {
211 case BASE_BIOS:
212 break;
213 case BASE_WORKING_RAM:
214 return ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
215 case BASE_WORKING_IRAM:
216 return ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
217 case BASE_IO:
218 break;
219 case BASE_PALETTE_RAM:
220 break;
221 case BASE_VRAM:
222 break;
223 case BASE_OAM:
224 break;
225 case BASE_CART0:
226 case BASE_CART0_EX:
227 case BASE_CART1:
228 case BASE_CART1_EX:
229 case BASE_CART2:
230 case BASE_CART2_EX:
231 return ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
232 case BASE_CART_SRAM:
233 break;
234 default:
235 break;
236 }
237
238 return 0;
239}
240
241uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address) {
242 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
243
244 switch (address & ~OFFSET_MASK) {
245 case BASE_BIOS:
246 break;
247 case BASE_WORKING_RAM:
248 return ((uint8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
249 break;
250 case BASE_WORKING_IRAM:
251 return ((uint8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
252 break;
253 case BASE_IO:
254 return (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
255 case BASE_PALETTE_RAM:
256 break;
257 case BASE_VRAM:
258 break;
259 case BASE_OAM:
260 break;
261 case BASE_CART0:
262 case BASE_CART0_EX:
263 case BASE_CART1:
264 case BASE_CART1_EX:
265 case BASE_CART2:
266 case BASE_CART2_EX:
267 return ((uint8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
268 case BASE_CART_SRAM:
269 break;
270 default:
271 break;
272 }
273
274 return 0;
275}
276
277void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value) {
278 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
279
280 switch (address & ~OFFSET_MASK) {
281 case BASE_WORKING_RAM:
282 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
283 break;
284 case BASE_WORKING_IRAM:
285 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
286 break;
287 case BASE_IO:
288 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
289 break;
290 case BASE_PALETTE_RAM:
291 ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2] = value;
292 break;
293 case BASE_VRAM:
294 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
295 ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2] = value;
296 }
297 break;
298 case BASE_OAM:
299 ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2] = value;
300 break;
301 case BASE_CART0:
302 break;
303 case BASE_CART2_EX:
304 break;
305 case BASE_CART_SRAM:
306 break;
307 default:
308 break;
309 }
310}
311
312void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value) {
313 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
314
315 switch (address & ~OFFSET_MASK) {
316 case BASE_WORKING_RAM:
317 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
318 break;
319 case BASE_WORKING_IRAM:
320 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
321 break;
322 case BASE_IO:
323 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
324 break;
325 case BASE_PALETTE_RAM:
326 gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1] = value;
327 break;
328 case BASE_VRAM:
329 if ((address & OFFSET_MASK) < SIZE_VRAM) {
330 gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1] = value;
331 }
332 break;
333 case BASE_OAM:
334 gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1] = value;
335 break;
336 case BASE_CART0:
337 break;
338 case BASE_CART2_EX:
339 break;
340 case BASE_CART_SRAM:
341 break;
342 default:
343 break;
344 }
345}
346
347void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value) {
348 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
349
350 switch (address & ~OFFSET_MASK) {
351 case BASE_WORKING_RAM:
352 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
353 break;
354 case BASE_WORKING_IRAM:
355 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
356 break;
357 case BASE_IO:
358 break;
359 case BASE_PALETTE_RAM:
360 break;
361 case BASE_VRAM:
362 break;
363 case BASE_OAM:
364 break;
365 case BASE_CART0:
366 break;
367 case BASE_CART2_EX:
368 break;
369 case BASE_CART_SRAM:
370 break;
371 default:
372 break;
373 }
374}
375
376void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
377 int sram = parameters & 0x0003;
378 int ws0 = (parameters & 0x000C) >> 2;
379 int ws0seq = (parameters & 0x0010) >> 4;
380 int ws1 = (parameters & 0x0060) >> 5;
381 int ws1seq = (parameters & 0x0080) >> 7;
382 int ws2 = (parameters & 0x0300) >> 8;
383 int ws2seq = (parameters & 0x0400) >> 10;
384 int prefetch = parameters & 0x4000;
385
386 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
387 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
388 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
389 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
390
391 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
392 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
393 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
394
395 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
396 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
397 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
398
399 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
400 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
401 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
402
403 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0 + 1] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
404 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1 + 1] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
405 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2 + 1] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
406
407 memory->d.activePrefetchCycles32 = memory->waitstates32[memory->activeRegion];
408 memory->d.activePrefetchCycles16 = memory->waitstates16[memory->activeRegion];
409}
410
411int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
412 struct GBADMA* dma;
413 int32_t test = INT_MAX;
414
415 dma = &memory->dma[0];
416 dma->nextIRQ -= cycles;
417 if (dma->enable && dma->doIrq && dma->nextIRQ) {
418 if (dma->nextIRQ <= 0) {
419 dma->nextIRQ = INT_MAX;
420 GBARaiseIRQ(memory->p, IRQ_DMA0);
421 } else if (dma->nextIRQ < test) {
422 test = dma->nextIRQ;
423 }
424 }
425
426 dma = &memory->dma[1];
427 dma->nextIRQ -= cycles;
428 if (dma->enable && dma->doIrq && dma->nextIRQ) {
429 if (dma->nextIRQ <= 0) {
430 dma->nextIRQ = INT_MAX;
431 GBARaiseIRQ(memory->p, IRQ_DMA1);
432 } else if (dma->nextIRQ < test) {
433 test = dma->nextIRQ;
434 }
435 }
436
437 dma = &memory->dma[2];
438 dma->nextIRQ -= cycles;
439 if (dma->enable && dma->doIrq && dma->nextIRQ) {
440 if (dma->nextIRQ <= 0) {
441 dma->nextIRQ = INT_MAX;
442 GBARaiseIRQ(memory->p, IRQ_DMA2);
443 } else if (dma->nextIRQ < test) {
444 test = dma->nextIRQ;
445 }
446 }
447
448 dma = &memory->dma[3];
449 dma->nextIRQ -= cycles;
450 if (dma->enable && dma->doIrq && dma->nextIRQ) {
451 if (dma->nextIRQ <= 0) {
452 dma->nextIRQ = INT_MAX;
453 GBARaiseIRQ(memory->p, IRQ_DMA3);
454 } else if (dma->nextIRQ < test) {
455 test = dma->nextIRQ;
456 }
457 }
458
459 return test;
460}
461
462void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
463 memory->dma[dma].source = address & 0xFFFFFFFE;
464}
465
466void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
467 memory->dma[dma].dest = address & 0xFFFFFFFE;
468}
469
470void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
471 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
472}
473
474uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
475 struct GBADMA* currentDma = &memory->dma[dma];
476 int wasEnabled = currentDma->enable;
477 currentDma->packed = control;
478 currentDma->nextIRQ = 0;
479
480 if (currentDma->drq) {
481 GBALog(GBA_LOG_STUB, "DRQ not implemented");
482 }
483
484 if (!wasEnabled && currentDma->enable) {
485 currentDma->nextSource = currentDma->source;
486 currentDma->nextDest = currentDma->dest;
487 currentDma->nextCount = currentDma->count;
488 GBAMemoryScheduleDMA(memory, dma, currentDma);
489 }
490 // If the DMA has already occurred, this value might have changed since the function started
491 return currentDma->packed;
492};
493
494void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
495 switch (info->timing) {
496 case DMA_TIMING_NOW:
497 GBAMemoryServiceDMA(memory, number, info);
498 break;
499 case DMA_TIMING_HBLANK:
500 // Handled implicitly
501 break;
502 case DMA_TIMING_VBLANK:
503 // Handled implicitly
504 break;
505 case DMA_TIMING_CUSTOM:
506 switch (number) {
507 case 0:
508 GBALog(GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
509 break;
510 case 1:
511 case 2:
512 //this.cpu.irq.audio.scheduleFIFODma(number, info);
513 break;
514 case 3:
515 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
516 break;
517 }
518 }
519}
520
521void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
522 struct GBADMA* dma;
523 int i;
524 for (i = 0; i < 4; ++i) {
525 dma = &memory->dma[i];
526 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
527 GBAMemoryServiceDMA(memory, i, dma);
528 }
529 }
530}
531
532void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
533 struct GBADMA* dma;
534 int i;
535 for (i = 0; i < 4; ++i) {
536 dma = &memory->dma[i];
537 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
538 GBAMemoryServiceDMA(memory, i, dma);
539 }
540 }
541}
542
543void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
544 if (!info->enable) {
545 // There was a DMA scheduled that got canceled
546 return;
547 }
548
549 uint32_t width = info->width ? 4 : 2;
550 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
551 int destOffset = DMA_OFFSET[info->dstControl] * width;
552 int32_t wordsRemaining = info->nextCount;
553 uint32_t source = info->nextSource;
554 uint32_t dest = info->nextDest;
555 uint32_t sourceRegion = source >> BASE_OFFSET;
556 uint32_t destRegion = dest >> BASE_OFFSET;
557
558 if (width == 4) {
559 int32_t word;
560 source &= 0xFFFFFFFC;
561 dest &= 0xFFFFFFFC;
562 while (wordsRemaining--) {
563 word = GBALoad32(&memory->d, source);
564 GBAStore32(&memory->d, dest, word);
565 source += sourceOffset;
566 dest += destOffset;
567 }
568 } else {
569 uint16_t word;
570 while (wordsRemaining--) {
571 word = GBALoadU16(&memory->d, source);
572 GBAStore16(&memory->d, dest, word);
573 source += sourceOffset;
574 dest += destOffset;
575 }
576 }
577
578 if (info->doIrq) {
579 info->nextIRQ = memory->p->cpu.cycles + 2;
580 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
581 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
582 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
583 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
584 }
585
586 info->nextSource = source;
587 info->nextDest = dest;
588 info->nextCount = wordsRemaining;
589
590 if (!info->repeat) {
591 info->enable = 0;
592
593 // Clear the enable bit in memory
594 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
595 } else {
596 info->nextCount = info->count;
597 if (info->dstControl == DMA_INCREMENT_RELOAD) {
598 info->nextDest = info->dest;
599 }
600 GBAMemoryScheduleDMA(memory, number, info);
601 }
602}