1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "lr35902/lr35902.h"
 12
 13struct GB;
 14
 15enum {
 16	GB_BASE_CART_BANK0 = 0x0000,
 17	GB_BASE_CART_BANK1 = 0x4000,
 18	GB_BASE_VRAM = 0x8000,
 19	GB_BASE_EXTERNAL_RAM = 0xA000,
 20	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 21	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 22	GB_BASE_OAM = 0xFE00,
 23	GB_BASE_UNUSABLE = 0xFEA0,
 24	GB_BASE_IO = 0xFF00,
 25	GB_BASE_HRAM = 0xFF80,
 26	GB_BASE_IE = 0xFFFF
 27};
 28
 29enum {
 30	GB_REGION_CART_BANK0 = 0x0,
 31	GB_REGION_CART_BANK1 = 0x4,
 32	GB_REGION_VRAM = 0x8,
 33	GB_REGION_EXTERNAL_RAM = 0xA,
 34	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 35	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 36	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 37	GB_REGION_OTHER = 0xF,
 38};
 39
 40enum {
 41	GB_SIZE_CART_BANK0 = 0x4000,
 42	GB_SIZE_VRAM = 0x2000,
 43	GB_SIZE_EXTERNAL_RAM = 0x2000,
 44	GB_SIZE_WORKING_RAM = 0x8000,
 45	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 46	GB_SIZE_OAM = 0xA0,
 47	GB_SIZE_IO = 0x80,
 48	GB_SIZE_HRAM = 0x7F,
 49};
 50
 51enum GBMemoryBankControllerType {
 52	GB_MBC_NONE = 0,
 53	GB_MBC1 = 1,
 54	GB_MBC2 = 2,
 55	GB_MBC3 = 3,
 56	GB_MBC4 = 4,
 57	GB_MBC5 = 5,
 58	GB_MBC7 = 7,
 59	GB_MMM01 = 0x10,
 60	GB_HuC1 = 0x11
 61};
 62
 63struct GBMemory;
 64typedef void (*GBMemoryBankController)(struct GBMemory*, uint16_t address, uint8_t value);
 65
 66struct GBMemory {
 67	uint8_t* rom;
 68	uint8_t* romBank;
 69	enum GBMemoryBankControllerType mbcType;
 70	GBMemoryBankController mbc;
 71	int currentBank;
 72
 73	uint8_t* wram;
 74	uint8_t* wramBank;
 75
 76	bool sramAccess;
 77	uint8_t* sram;
 78	uint8_t* sramBank;
 79	int sramCurrentBank;
 80
 81	uint8_t io[GB_SIZE_IO];
 82	bool ime;
 83	uint8_t ie;
 84
 85	uint8_t hram[GB_SIZE_HRAM];
 86
 87	int32_t dmaNext;
 88	uint16_t dmaSource;
 89	uint16_t dmaDest;
 90	int dmaRemaining;
 91
 92	size_t romSize;
 93};
 94
 95void GBMemoryInit(struct GB* gb);
 96void GBMemoryDeinit(struct GB* gb);
 97
 98void GBMemoryReset(struct GB* gb);
 99
100uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
101void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
102
103int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles);
104void GBMemoryDMA(struct GB* gb, uint16_t base);
105
106uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
107void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
108
109uint16_t GBView16(struct LR35902Core* cpu, uint16_t address);
110uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
111
112void GBPatch16(struct LR35902Core* cpu, uint16_t address, int16_t value, int16_t* old);
113void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
114
115#endif