1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ARM_H
  7#define ARM_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/cpu.h>
 14
 15enum {
 16	ARM_SP = 13,
 17	ARM_LR = 14,
 18	ARM_PC = 15
 19};
 20
 21enum ExecutionMode {
 22	MODE_ARM = 0,
 23	MODE_THUMB = 1
 24};
 25
 26enum PrivilegeMode {
 27	MODE_USER = 0x10,
 28	MODE_FIQ = 0x11,
 29	MODE_IRQ = 0x12,
 30	MODE_SUPERVISOR = 0x13,
 31	MODE_ABORT = 0x17,
 32	MODE_UNDEFINED = 0x1B,
 33	MODE_SYSTEM = 0x1F
 34};
 35
 36enum WordSize {
 37	WORD_SIZE_ARM = 4,
 38	WORD_SIZE_THUMB = 2
 39};
 40
 41enum ExecutionVector {
 42	BASE_RESET = 0x00000000,
 43	BASE_UNDEF = 0x00000004,
 44	BASE_SWI = 0x00000008,
 45	BASE_PABT = 0x0000000C,
 46	BASE_DABT = 0x00000010,
 47	BASE_IRQ = 0x00000018,
 48	BASE_FIQ = 0x0000001C
 49};
 50
 51enum RegisterBank {
 52	BANK_NONE = 0,
 53	BANK_FIQ = 1,
 54	BANK_IRQ = 2,
 55	BANK_SUPERVISOR = 3,
 56	BANK_ABORT = 4,
 57	BANK_UNDEFINED = 5
 58};
 59
 60enum LSMDirection {
 61	LSM_B = 1,
 62	LSM_D = 2,
 63	LSM_IA = 0,
 64	LSM_IB = 1,
 65	LSM_DA = 2,
 66	LSM_DB = 3
 67};
 68
 69struct ARMCore;
 70
 71union PSR {
 72	struct {
 73#if defined(__POWERPC__) || defined(__PPC__)
 74		unsigned n : 1;
 75		unsigned z : 1;
 76		unsigned c : 1;
 77		unsigned v : 1;
 78		unsigned q : 1;
 79		unsigned unused : 19;
 80		unsigned i : 1;
 81		unsigned f : 1;
 82		unsigned t : 1;
 83		unsigned priv : 5;
 84#else
 85		unsigned priv : 5;
 86		unsigned t : 1;
 87		unsigned f : 1;
 88		unsigned i : 1;
 89		unsigned unused : 19;
 90		unsigned q : 1;
 91		unsigned v : 1;
 92		unsigned c : 1;
 93		unsigned z : 1;
 94		unsigned n : 1;
 95#endif
 96	};
 97
 98	int32_t packed;
 99};
100
101struct ARMMemory {
102	uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
103	uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
104	uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
105
106	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
107	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
108	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
109
110	uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
111	                         int* cycleCounter);
112	uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
113	                          int* cycleCounter);
114
115	uint32_t* activeRegion;
116	uint32_t activeMask;
117	uint32_t activeSeqCycles32;
118	uint32_t activeSeqCycles16;
119	uint32_t activeNonseqCycles32;
120	uint32_t activeNonseqCycles16;
121	int32_t (*stall)(struct ARMCore*, int32_t wait);
122	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
123};
124
125struct ARMInterruptHandler {
126	void (*reset)(struct ARMCore* cpu);
127	void (*processEvents)(struct ARMCore* cpu);
128	void (*swi16)(struct ARMCore* cpu, int immediate);
129	void (*swi32)(struct ARMCore* cpu, int immediate);
130	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
131	void (*bkpt16)(struct ARMCore* cpu, int immediate);
132	void (*bkpt32)(struct ARMCore* cpu, int immediate);
133	void (*readCPSR)(struct ARMCore* cpu);
134	void (*writeCP15)(struct ARMCore*, int crn, int crm, int opcode1, int opcode2, uint32_t value);
135	uint32_t (*readCP15)(struct ARMCore*, int crn, int crm, int opcode1, int opcode2);
136
137	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
138};
139
140DECL_BITFIELD(ARMCPUID, uint32_t);
141DECL_BITFIELD(ARMCacheType, uint32_t);
142DECL_BITFIELD(ARMTCMType, uint32_t);
143DECL_BITFIELD(ARMTLBType, uint32_t);
144DECL_BITFIELD(ARMMPUType, uint32_t);
145
146DECL_BITFIELD(ARMControlReg, uint32_t);
147DECL_BIT(ARMControlReg, M, 0);
148DECL_BIT(ARMControlReg, A, 1);
149DECL_BIT(ARMControlReg, C, 2);
150DECL_BIT(ARMControlReg, W, 3);
151DECL_BIT(ARMControlReg, P, 4);
152DECL_BIT(ARMControlReg, D, 5);
153DECL_BIT(ARMControlReg, L, 6);
154DECL_BIT(ARMControlReg, B, 7);
155DECL_BIT(ARMControlReg, S, 8);
156DECL_BIT(ARMControlReg, R, 9);
157DECL_BIT(ARMControlReg, F, 10);
158DECL_BIT(ARMControlReg, Z, 11);
159DECL_BIT(ARMControlReg, I, 12);
160DECL_BIT(ARMControlReg, V, 13);
161DECL_BIT(ARMControlReg, RR, 14);
162DECL_BIT(ARMControlReg, L4, 15);
163DECL_BIT(ARMControlReg, FI, 21);
164DECL_BIT(ARMControlReg, U, 22);
165DECL_BIT(ARMControlReg, XP, 23);
166DECL_BIT(ARMControlReg, VE, 24);
167DECL_BIT(ARMControlReg, EE, 25);
168DECL_BIT(ARMControlReg, L2, 26);
169
170DECL_BITFIELD(ARMCoprocessorAccess, uint32_t);
171
172DECL_BITFIELD(ARMCacheability, uint32_t);
173DECL_BIT(ARMCacheability, 0, 0);
174DECL_BIT(ARMCacheability, 1, 1);
175DECL_BIT(ARMCacheability, 2, 2);
176DECL_BIT(ARMCacheability, 3, 3);
177DECL_BIT(ARMCacheability, 4, 4);
178DECL_BIT(ARMCacheability, 5, 5);
179DECL_BIT(ARMCacheability, 6, 6);
180DECL_BIT(ARMCacheability, 7, 7);
181
182DECL_BITFIELD(ARMProtection, uint32_t);
183DECL_BIT(ARMProtection, Enable, 0);
184DECL_BITS(ARMProtection, Size, 1, 5);
185DECL_BITS(ARMProtection, Base, 12, 20);
186
187DECL_BITFIELD(ARMTCMControl, uint32_t);
188DECL_BITS(ARMTCMControl, VirtualSize, 1, 5);
189DECL_BITS(ARMTCMControl, Base, 12, 20);
190
191struct ARMCP15 {
192	struct {
193		ARMCPUID cpuid;
194		ARMCacheType cachetype;
195		ARMTCMType tcmtype;
196		ARMTLBType tlbtype;
197		ARMMPUType mputype;
198	} r0;
199	struct {
200		ARMControlReg c0;
201		uint32_t c1;
202		ARMCoprocessorAccess cpAccess;
203	} r1;
204	struct {
205		ARMCacheability d;
206		ARMCacheability i;
207	} r2;
208	struct {
209		ARMCacheability d;
210	} r3;
211	struct {
212		ARMProtection region[8];
213	} r6;
214	struct {
215		ARMTCMControl d;
216		ARMTCMControl i;
217	} r9;
218};
219
220struct ARMCore {
221	int32_t gprs[16];
222	union PSR cpsr;
223	union PSR spsr;
224
225	int32_t cycles;
226	int32_t nextEvent;
227	int halted;
228
229	int32_t bankedRegisters[6][7];
230	int32_t bankedSPSRs[6];
231
232	int32_t shifterOperand;
233	int32_t shifterCarryOut;
234
235	uint32_t prefetch[2];
236	enum ExecutionMode executionMode;
237	enum PrivilegeMode privilegeMode;
238
239	struct ARMMemory memory;
240	struct ARMInterruptHandler irqh;
241	struct ARMCP15 cp15;
242
243	struct mCPUComponent* master;
244
245	size_t numComponents;
246	struct mCPUComponent** components;
247};
248
249void ARMInit(struct ARMCore* cpu);
250void ARMDeinit(struct ARMCore* cpu);
251void ARMSetComponents(struct ARMCore* cpu, struct mCPUComponent* master, int extra, struct mCPUComponent** extras);
252void ARMHotplugAttach(struct ARMCore* cpu, size_t slot);
253void ARMHotplugDetach(struct ARMCore* cpu, size_t slot);
254
255void ARMReset(struct ARMCore* cpu);
256void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
257void ARMRaiseIRQ(struct ARMCore*);
258void ARMRaiseSWI(struct ARMCore*);
259void ARMRaiseUndefined(struct ARMCore*);
260void ARMHalt(struct ARMCore*);
261
262void ARMv4Run(struct ARMCore* cpu);
263void ARMv4RunLoop(struct ARMCore* cpu);
264int32_t ARMv4RunCycles(struct ARMCore* cpu, int32_t cycles);
265void ARMv5Run(struct ARMCore* cpu);
266void ARMv5RunLoop(struct ARMCore* cpu);
267int32_t ARMv5RunCycles(struct ARMCore* cpu, int32_t cycles);
268void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
269
270CXX_GUARD_END
271
272#endif