src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
33
34static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
35static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
36
37static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
38
39static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
40static void _GBPocketCamCapture(struct GBMemory*);
41
42void GBMBCSwitchBank(struct GB* gb, int bank) {
43 size_t bankStart = bank * GB_SIZE_CART_BANK0;
44 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
45 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
46 bankStart &= (gb->memory.romSize - 1);
47 bank = bankStart / GB_SIZE_CART_BANK0;
48 if (!bank) {
49 ++bank;
50 }
51 }
52 gb->memory.romBank = &gb->memory.rom[bankStart];
53 gb->memory.currentBank = bank;
54 if (gb->cpu->pc < GB_BASE_VRAM) {
55 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
56 }
57}
58
59void GBMBCSwitchBank0(struct GB* gb, int bank) {
60 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
61 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
62 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
63 bankStart &= (gb->memory.romSize - 1);
64 }
65 gb->memory.romBase = &gb->memory.rom[bankStart];
66 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
67 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
68 }
69}
70
71void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
72 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
73 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
74 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
75 bankStart &= (gb->memory.romSize - 1);
76 bank = bankStart / GB_SIZE_CART_HALFBANK;
77 if (!bank) {
78 ++bank;
79 }
80 }
81 if (!half) {
82 gb->memory.romBank = &gb->memory.rom[bankStart];
83 gb->memory.currentBank = bank;
84 } else {
85 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
86 gb->memory.mbcState.mbc6.currentBank1 = bank;
87 }
88 if (gb->cpu->pc < GB_BASE_VRAM) {
89 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
90 }
91}
92
93static bool _isMulticart(const uint8_t* mem) {
94 bool success = true;
95 struct VFile* vf;
96
97 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
98 success = success && GBIsROM(vf);
99 vf->close(vf);
100
101 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
102 success = success && GBIsROM(vf);
103 vf->close(vf);
104
105 return success;
106}
107
108void GBMBCSwitchSramBank(struct GB* gb, int bank) {
109 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
110 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
111 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
112 bankStart &= (gb->sramSize - 1);
113 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
114 }
115 gb->memory.sramBank = &gb->memory.sram[bankStart];
116 gb->memory.sramCurrentBank = bank;
117}
118
119void GBMBCInit(struct GB* gb) {
120 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
121 if (gb->memory.rom) {
122 switch (cart->ramSize) {
123 case 0:
124 gb->sramSize = 0;
125 break;
126 case 1:
127 gb->sramSize = 0x800;
128 break;
129 default:
130 case 2:
131 gb->sramSize = 0x2000;
132 break;
133 case 3:
134 gb->sramSize = 0x8000;
135 break;
136 case 4:
137 gb->sramSize = 0x20000;
138 break;
139 case 5:
140 gb->sramSize = 0x10000;
141 break;
142 }
143
144 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
145 switch (cart->type) {
146 case 0:
147 case 8:
148 case 9:
149 gb->memory.mbcType = GB_MBC_NONE;
150 break;
151 case 1:
152 case 2:
153 case 3:
154 gb->memory.mbcType = GB_MBC1;
155 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
156 gb->memory.mbcState.mbc1.multicartStride = 4;
157 } else {
158 gb->memory.mbcState.mbc1.multicartStride = 5;
159 }
160 break;
161 case 5:
162 case 6:
163 gb->memory.mbcType = GB_MBC2;
164 break;
165 case 0x0F:
166 case 0x10:
167 gb->memory.mbcType = GB_MBC3_RTC;
168 break;
169 case 0x11:
170 case 0x12:
171 case 0x13:
172 gb->memory.mbcType = GB_MBC3;
173 break;
174 default:
175 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
176 // Fall through
177 case 0x19:
178 case 0x1A:
179 case 0x1B:
180 gb->memory.mbcType = GB_MBC5;
181 break;
182 case 0x1C:
183 case 0x1D:
184 case 0x1E:
185 gb->memory.mbcType = GB_MBC5_RUMBLE;
186 break;
187 case 0x20:
188 gb->memory.mbcType = GB_MBC6;
189 break;
190 case 0x22:
191 gb->memory.mbcType = GB_MBC7;
192 break;
193 case 0xFC:
194 gb->memory.mbcType = GB_POCKETCAM;
195 break;
196 case 0xFD:
197 gb->memory.mbcType = GB_TAMA5;
198 break;
199 case 0xFE:
200 gb->memory.mbcType = GB_HuC3;
201 break;
202 case 0xFF:
203 gb->memory.mbcType = GB_HuC1;
204 break;
205 }
206 }
207 } else {
208 gb->memory.mbcType = GB_MBC_NONE;
209 }
210 gb->memory.mbcRead = NULL;
211 switch (gb->memory.mbcType) {
212 case GB_MBC_NONE:
213 gb->memory.mbcWrite = _GBMBCNone;
214 break;
215 case GB_MBC1:
216 gb->memory.mbcWrite = _GBMBC1;
217 break;
218 case GB_MBC2:
219 gb->memory.mbcWrite = _GBMBC2;
220 gb->sramSize = 0x200;
221 break;
222 case GB_MBC3:
223 gb->memory.mbcWrite = _GBMBC3;
224 break;
225 default:
226 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
227 // Fall through
228 case GB_MBC5:
229 gb->memory.mbcWrite = _GBMBC5;
230 break;
231 case GB_MBC6:
232 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
233 gb->memory.mbcWrite = _GBMBC6;
234 break;
235 case GB_MBC7:
236 gb->memory.mbcWrite = _GBMBC7;
237 gb->memory.mbcRead = _GBMBC7Read;
238 gb->sramSize = 0x100;
239 break;
240 case GB_MMM01:
241 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
242 gb->memory.mbcWrite = _GBMBC1;
243 break;
244 case GB_HuC1:
245 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
246 gb->memory.mbcWrite = _GBMBC1;
247 break;
248 case GB_HuC3:
249 gb->memory.mbcWrite = _GBHuC3;
250 break;
251 case GB_TAMA5:
252 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
253 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
254 gb->memory.mbcWrite = _GBTAMA5;
255 gb->memory.mbcRead = _GBTAMA5Read;
256 gb->sramSize = 0x20;
257 break;
258 case GB_MBC3_RTC:
259 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
260 gb->memory.mbcWrite = _GBMBC3;
261 break;
262 case GB_MBC5_RUMBLE:
263 gb->memory.mbcWrite = _GBMBC5;
264 break;
265 case GB_POCKETCAM:
266 gb->memory.mbcWrite = _GBPocketCam;
267 gb->memory.mbcRead = _GBPocketCamRead;
268 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
269 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
270 }
271 break;
272 }
273
274 gb->memory.currentBank = 1;
275 gb->memory.sramCurrentBank = 0;
276 gb->memory.sramAccess = false;
277 gb->memory.rtcAccess = false;
278 gb->memory.activeRtcReg = 0;
279 gb->memory.rtcLatched = false;
280 gb->memory.rtcLastLatch = 0;
281 if (gb->memory.rtc) {
282 if (gb->memory.rtc->sample) {
283 gb->memory.rtc->sample(gb->memory.rtc);
284 }
285 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
286 } else {
287 gb->memory.rtcLastLatch = time(0);
288 }
289 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
290
291 GBResizeSram(gb, gb->sramSize);
292
293 if (gb->memory.mbcType == GB_MBC3_RTC) {
294 GBMBCRTCRead(gb);
295 }
296}
297
298static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
299 time_t t;
300 if (rtc) {
301 if (rtc->sample) {
302 rtc->sample(rtc);
303 }
304 t = rtc->unixTime(rtc);
305 } else {
306 t = time(0);
307 }
308 time_t currentLatch = t;
309 t -= *rtcLastLatch;
310 *rtcLastLatch = currentLatch;
311
312 int64_t diff;
313 diff = rtcRegs[0] + t % 60;
314 if (diff < 0) {
315 diff += 60;
316 t -= 60;
317 }
318 rtcRegs[0] = diff % 60;
319 t /= 60;
320 t += diff / 60;
321
322 diff = rtcRegs[1] + t % 60;
323 if (diff < 0) {
324 diff += 60;
325 t -= 60;
326 }
327 rtcRegs[1] = diff % 60;
328 t /= 60;
329 t += diff / 60;
330
331 diff = rtcRegs[2] + t % 24;
332 if (diff < 0) {
333 diff += 24;
334 t -= 24;
335 }
336 rtcRegs[2] = diff % 24;
337 t /= 24;
338 t += diff / 24;
339
340 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
341 rtcRegs[3] = diff;
342 rtcRegs[4] &= 0xFE;
343 rtcRegs[4] |= (diff >> 8) & 1;
344 if (diff & 0x200) {
345 rtcRegs[4] |= 0x80;
346 }
347}
348
349void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
350 struct GBMemory* memory = &gb->memory;
351 int bank = value & 0x1F;
352 int stride = 1 << memory->mbcState.mbc1.multicartStride;
353 switch (address >> 13) {
354 case 0x0:
355 switch (value) {
356 case 0:
357 memory->sramAccess = false;
358 break;
359 case 0xA:
360 memory->sramAccess = true;
361 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
362 break;
363 default:
364 // TODO
365 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
366 break;
367 }
368 break;
369 case 0x1:
370 if (!bank) {
371 ++bank;
372 }
373 bank &= stride - 1;
374 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
375 break;
376 case 0x2:
377 bank &= 3;
378 if (memory->mbcState.mbc1.mode) {
379 GBMBCSwitchBank0(gb, bank);
380 GBMBCSwitchSramBank(gb, bank);
381 }
382 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
383 break;
384 case 0x3:
385 memory->mbcState.mbc1.mode = value & 1;
386 if (memory->mbcState.mbc1.mode) {
387 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
388 } else {
389 GBMBCSwitchBank0(gb, 0);
390 GBMBCSwitchSramBank(gb, 0);
391 }
392 break;
393 default:
394 // TODO
395 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
396 break;
397 }
398}
399
400void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
401 struct GBMemory* memory = &gb->memory;
402 int bank = value & 0xF;
403 switch (address >> 13) {
404 case 0x0:
405 switch (value) {
406 case 0:
407 memory->sramAccess = false;
408 break;
409 case 0xA:
410 memory->sramAccess = true;
411 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
412 break;
413 default:
414 // TODO
415 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
416 break;
417 }
418 break;
419 case 0x1:
420 if (!bank) {
421 ++bank;
422 }
423 GBMBCSwitchBank(gb, bank);
424 break;
425 default:
426 // TODO
427 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
428 break;
429 }
430}
431
432void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
433 struct GBMemory* memory = &gb->memory;
434 int bank = value & 0x7F;
435 switch (address >> 13) {
436 case 0x0:
437 switch (value) {
438 case 0:
439 memory->sramAccess = false;
440 break;
441 case 0xA:
442 memory->sramAccess = true;
443 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
444 break;
445 default:
446 // TODO
447 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
448 break;
449 }
450 break;
451 case 0x1:
452 if (!bank) {
453 ++bank;
454 }
455 GBMBCSwitchBank(gb, bank);
456 break;
457 case 0x2:
458 if (value < 4) {
459 GBMBCSwitchSramBank(gb, value);
460 memory->rtcAccess = false;
461 } else if (value >= 8 && value <= 0xC) {
462 memory->activeRtcReg = value - 8;
463 memory->rtcAccess = true;
464 }
465 break;
466 case 0x3:
467 if (memory->rtcLatched && value == 0) {
468 memory->rtcLatched = false;
469 } else if (!memory->rtcLatched && value == 1) {
470 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
471 memory->rtcLatched = true;
472 }
473 break;
474 }
475}
476
477void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
478 struct GBMemory* memory = &gb->memory;
479 int bank;
480 switch (address >> 12) {
481 case 0x0:
482 case 0x1:
483 switch (value) {
484 case 0:
485 memory->sramAccess = false;
486 break;
487 case 0xA:
488 memory->sramAccess = true;
489 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
490 break;
491 default:
492 // TODO
493 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
494 break;
495 }
496 break;
497 case 0x2:
498 bank = (memory->currentBank & 0x100) | value;
499 GBMBCSwitchBank(gb, bank);
500 break;
501 case 0x3:
502 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
503 GBMBCSwitchBank(gb, bank);
504 break;
505 case 0x4:
506 case 0x5:
507 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
508 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
509 value &= ~8;
510 }
511 GBMBCSwitchSramBank(gb, value & 0xF);
512 break;
513 default:
514 // TODO
515 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
516 break;
517 }
518}
519
520void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
521 struct GBMemory* memory = &gb->memory;
522 int bank = value & 0x7F;
523 switch (address >> 10) {
524 case 0:
525 switch (value) {
526 case 0:
527 memory->sramAccess = false;
528 break;
529 case 0xA:
530 memory->sramAccess = true;
531 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
532 break;
533 default:
534 // TODO
535 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
536 break;
537 }
538 break;
539 case 0x9:
540 GBMBCSwitchHalfBank(gb, 0, bank);
541 break;
542 case 0xD:
543 GBMBCSwitchHalfBank(gb, 1, bank);
544 break;
545 default:
546 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
547 break;
548 }
549}
550
551void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
552 int bank = value & 0x7F;
553 switch (address >> 13) {
554 case 0x0:
555 switch (value) {
556 default:
557 case 0:
558 gb->memory.mbcState.mbc7.access = 0;
559 break;
560 case 0xA:
561 gb->memory.mbcState.mbc7.access |= 1;
562 break;
563 }
564 break;
565 case 0x1:
566 GBMBCSwitchBank(gb, bank);
567 break;
568 case 0x2:
569 if (value == 0x40) {
570 gb->memory.mbcState.mbc7.access |= 2;
571 } else {
572 gb->memory.mbcState.mbc7.access &= ~2;
573 }
574 break;
575 case 0x5:
576 _GBMBC7Write(&gb->memory, address, value);
577 default:
578 // TODO
579 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
580 break;
581 }
582}
583
584uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
585 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
586 if (mbc7->access != 3) {
587 return 0xFF;
588 }
589 switch (address & 0xF0) {
590 case 0x20:
591 if (memory->rotation && memory->rotation->readTiltX) {
592 int32_t x = -memory->rotation->readTiltX(memory->rotation);
593 x >>= 21;
594 x += 0x81D0;
595 return x;
596 }
597 return 0xFF;
598 case 0x30:
599 if (memory->rotation && memory->rotation->readTiltX) {
600 int32_t x = -memory->rotation->readTiltX(memory->rotation);
601 x >>= 21;
602 x += 0x81D0;
603 return x >> 8;
604 }
605 return 7;
606 case 0x40:
607 if (memory->rotation && memory->rotation->readTiltY) {
608 int32_t y = -memory->rotation->readTiltY(memory->rotation);
609 y >>= 21;
610 y += 0x81D0;
611 return y;
612 }
613 return 0xFF;
614 case 0x50:
615 if (memory->rotation && memory->rotation->readTiltY) {
616 int32_t y = -memory->rotation->readTiltY(memory->rotation);
617 y >>= 21;
618 y += 0x81D0;
619 return y >> 8;
620 }
621 return 7;
622 case 0x60:
623 return 0;
624 case 0x80:
625 return mbc7->eeprom;
626 default:
627 return 0xFF;
628 }
629}
630
631static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
632 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
633 if (mbc7->access != 3) {
634 return;
635 }
636 switch (address & 0xF0) {
637 case 0x00:
638 mbc7->latch = (value & 0x55) == 0x55;
639 return;
640 case 0x10:
641 mbc7->latch |= (value & 0xAA);
642 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
643 memory->rotation->sample(memory->rotation);
644 }
645 mbc7->latch = 0;
646 return;
647 default:
648 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
649 return;
650 case 0x80:
651 break;
652 }
653 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
654 value = GBMBC7FieldFillDO(value); // Hi-Z
655 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
656 mbc7->state = GBMBC7_STATE_IDLE;
657 }
658 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
659 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
660 mbc7->sr <<= 1;
661 mbc7->sr |= GBMBC7FieldGetDI(value);
662 ++mbc7->srBits;
663 }
664 switch (mbc7->state) {
665 case GBMBC7_STATE_IDLE:
666 if (GBMBC7FieldIsDI(value)) {
667 mbc7->state = GBMBC7_STATE_READ_COMMAND;
668 mbc7->srBits = 0;
669 mbc7->sr = 0;
670 }
671 break;
672 case GBMBC7_STATE_READ_COMMAND:
673 if (mbc7->srBits == 10) {
674 mbc7->state = 0x10 | (mbc7->sr >> 6);
675 if (mbc7->state & 0xC) {
676 mbc7->state &= ~0x3;
677 }
678 mbc7->srBits = 0;
679 mbc7->address = mbc7->sr & 0x7F;
680 }
681 break;
682 case GBMBC7_STATE_DO:
683 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
684 mbc7->sr <<= 1;
685 --mbc7->srBits;
686 if (!mbc7->srBits) {
687 mbc7->state = GBMBC7_STATE_IDLE;
688 }
689 break;
690 default:
691 break;
692 }
693 switch (mbc7->state) {
694 case GBMBC7_STATE_EEPROM_EWEN:
695 mbc7->writable = true;
696 mbc7->state = GBMBC7_STATE_IDLE;
697 break;
698 case GBMBC7_STATE_EEPROM_EWDS:
699 mbc7->writable = false;
700 mbc7->state = GBMBC7_STATE_IDLE;
701 break;
702 case GBMBC7_STATE_EEPROM_WRITE:
703 if (mbc7->srBits == 16) {
704 if (mbc7->writable) {
705 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
706 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
707 }
708 mbc7->state = GBMBC7_STATE_IDLE;
709 }
710 break;
711 case GBMBC7_STATE_EEPROM_ERASE:
712 if (mbc7->writable) {
713 memory->sram[mbc7->address * 2] = 0xFF;
714 memory->sram[mbc7->address * 2 + 1] = 0xFF;
715 }
716 mbc7->state = GBMBC7_STATE_IDLE;
717 break;
718 case GBMBC7_STATE_EEPROM_READ:
719 mbc7->srBits = 16;
720 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
721 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
722 mbc7->state = GBMBC7_STATE_DO;
723 value = GBMBC7FieldClearDO(value);
724 break;
725 case GBMBC7_STATE_EEPROM_WRAL:
726 if (mbc7->srBits == 16) {
727 if (mbc7->writable) {
728 int i;
729 for (i = 0; i < 128; ++i) {
730 memory->sram[i * 2] = mbc7->sr >> 8;
731 memory->sram[i * 2 + 1] = mbc7->sr;
732 }
733 }
734 mbc7->state = GBMBC7_STATE_IDLE;
735 }
736 break;
737 case GBMBC7_STATE_EEPROM_ERAL:
738 if (mbc7->writable) {
739 int i;
740 for (i = 0; i < 128; ++i) {
741 memory->sram[i * 2] = 0xFF;
742 memory->sram[i * 2 + 1] = 0xFF;
743 }
744 }
745 mbc7->state = GBMBC7_STATE_IDLE;
746 break;
747 default:
748 break;
749 }
750 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
751 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
752 }
753 mbc7->eeprom = value;
754}
755
756void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
757 struct GBMemory* memory = &gb->memory;
758 int bank = value & 0x3F;
759 if (address & 0x1FFF) {
760 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
761 }
762
763 switch (address >> 13) {
764 case 0x0:
765 switch (value) {
766 case 0xA:
767 memory->sramAccess = true;
768 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
769 break;
770 default:
771 memory->sramAccess = false;
772 break;
773 }
774 break;
775 case 0x1:
776 GBMBCSwitchBank(gb, bank);
777 break;
778 case 0x2:
779 GBMBCSwitchSramBank(gb, bank);
780 break;
781 default:
782 // TODO
783 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
784 break;
785 }
786}
787
788void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
789 struct GBMemory* memory = &gb->memory;
790 int bank = value & 0x3F;
791 switch (address >> 13) {
792 case 0x0:
793 switch (value) {
794 case 0:
795 memory->sramAccess = false;
796 break;
797 case 0xA:
798 memory->sramAccess = true;
799 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
800 break;
801 default:
802 // TODO
803 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
804 break;
805 }
806 break;
807 case 0x1:
808 GBMBCSwitchBank(gb, bank);
809 break;
810 case 0x2:
811 if (value < 0x10) {
812 GBMBCSwitchSramBank(gb, value);
813 memory->mbcState.pocketCam.registersActive = false;
814 } else {
815 memory->mbcState.pocketCam.registersActive = true;
816 }
817 break;
818 case 0x5:
819 address &= 0x7F;
820 if (address == 0 && value & 1) {
821 value &= 6; // TODO: Timing
822 _GBPocketCamCapture(memory);
823 }
824 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
825 memory->mbcState.pocketCam.registers[address] = value;
826 }
827 break;
828 default:
829 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
830 break;
831 }
832}
833
834uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
835 if (memory->mbcState.pocketCam.registersActive) {
836 if ((address & 0x7F) == 0) {
837 return memory->mbcState.pocketCam.registers[0];
838 }
839 return 0;
840 }
841 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
842}
843
844void _GBPocketCamCapture(struct GBMemory* memory) {
845 if (!memory->cam) {
846 return;
847 }
848 const void* image = NULL;
849 size_t stride;
850 enum mColorFormat format;
851 memory->cam->requestImage(memory->cam, &image, &stride, &format);
852 if (!image) {
853 return;
854 }
855 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
856 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
857 size_t x, y;
858 for (y = 0; y < GBCAM_HEIGHT; ++y) {
859 for (x = 0; x < GBCAM_WIDTH; ++x) {
860 uint32_t gray;
861 uint32_t color;
862 switch (format) {
863 case mCOLOR_XBGR8:
864 case mCOLOR_XRGB8:
865 case mCOLOR_ARGB8:
866 case mCOLOR_ABGR8:
867 color = ((const uint32_t*) image)[y * stride + x];
868 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
869 break;
870 case mCOLOR_BGRX8:
871 case mCOLOR_RGBX8:
872 case mCOLOR_RGBA8:
873 case mCOLOR_BGRA8:
874 color = ((const uint32_t*) image)[y * stride + x];
875 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
876 break;
877 case mCOLOR_BGR5:
878 case mCOLOR_RGB5:
879 case mCOLOR_ARGB5:
880 case mCOLOR_ABGR5:
881 color = ((const uint16_t*) image)[y * stride + x];
882 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
883 break;
884 case mCOLOR_BGR565:
885 case mCOLOR_RGB565:
886 color = ((const uint16_t*) image)[y * stride + x];
887 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
888 break;
889 case mCOLOR_BGRA5:
890 case mCOLOR_RGBA5:
891 color = ((const uint16_t*) image)[y * stride + x];
892 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
893 break;
894 default:
895 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
896 return;
897 }
898 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
899 gray = (gray + 1) * exposure / 0x300;
900 // TODO: Additional processing
901 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
902 if (gray < pocketCam->registers[matrixEntry + 6]) {
903 gray = 0x101;
904 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
905 gray = 0x100;
906 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
907 gray = 0x001;
908 } else {
909 gray = 0;
910 }
911 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
912 uint16_t existing;
913 LOAD_16LE(existing, coord + 0x100, memory->sram);
914 existing |= gray << (7 - (x & 7));
915 STORE_16LE(existing, coord + 0x100, memory->sram);
916 }
917 }
918}
919
920void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
921 struct GBMemory* memory = &gb->memory;
922 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
923 switch (address >> 13) {
924 case 0x5:
925 if (address & 1) {
926 tama5->reg = value;
927 } else {
928 value &= 0xF;
929 if (tama5->reg < GBTAMA5_MAX) {
930 tama5->registers[tama5->reg] = value;
931 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
932 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
933 switch (tama5->reg) {
934 case GBTAMA5_BANK_LO:
935 case GBTAMA5_BANK_HI:
936 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
937 break;
938 case GBTAMA5_WRITE_LO:
939 case GBTAMA5_WRITE_HI:
940 case GBTAMA5_CS:
941 break;
942 case GBTAMA5_ADDR_LO:
943 switch (tama5->registers[GBTAMA5_CS] >> 1) {
944 case 0x0: // RAM write
945 memory->sram[address] = out;
946 break;
947 case 0x1: // RAM read
948 break;
949 default:
950 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
951 }
952 break;
953 default:
954 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
955 break;
956 }
957 } else {
958 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
959 }
960 }
961 break;
962 default:
963 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
964 }
965}
966
967uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
968 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
969 if ((address & 0x1FFF) > 1) {
970 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
971 }
972 if (address & 1) {
973 return 0xFF;
974 } else {
975 uint8_t value = 0xF0;
976 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
977 switch (tama5->reg) {
978 case GBTAMA5_ACTIVE:
979 return 0xF1;
980 case GBTAMA5_READ_LO:
981 case GBTAMA5_READ_HI:
982 switch (tama5->registers[GBTAMA5_CS] >> 1) {
983 case 1:
984 value = memory->sram[address];
985 break;
986 default:
987 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
988 break;
989 }
990 if (tama5->reg == GBTAMA5_READ_HI) {
991 value >>= 4;
992 }
993 value |= 0xF0;
994 return value;
995 default:
996 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
997 return 0xF1;
998 }
999 }
1000}
1001
1002void GBMBCRTCRead(struct GB* gb) {
1003 struct GBMBCRTCSaveBuffer rtcBuffer;
1004 struct VFile* vf = gb->sramVf;
1005 if (!vf) {
1006 return;
1007 }
1008 vf->seek(vf, gb->sramSize, SEEK_SET);
1009 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1010 return;
1011 }
1012
1013 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1014 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1015 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1016 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1017 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1018 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1019}
1020
1021void GBMBCRTCWrite(struct GB* gb) {
1022 struct VFile* vf = gb->sramVf;
1023 if (!vf) {
1024 return;
1025 }
1026
1027 uint8_t rtcRegs[5];
1028 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1029 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1030 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1031
1032 struct GBMBCRTCSaveBuffer rtcBuffer;
1033 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1034 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1035 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1036 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1037 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1038 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1039 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1040 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1041 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1042 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1043 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1044
1045 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1046 // Writing past the end of the file can invalidate the file mapping
1047 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1048 gb->memory.sram = NULL;
1049 }
1050 vf->seek(vf, gb->sramSize, SEEK_SET);
1051 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1052 if (!gb->memory.sram) {
1053 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1054 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1055 }
1056}