1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/gb/interface.h>
 16
 17mLOG_DECLARE_CATEGORY(GB_MBC);
 18mLOG_DECLARE_CATEGORY(GB_MEM);
 19
 20struct GB;
 21
 22enum {
 23	GB_BASE_CART_BANK0 = 0x0000,
 24	GB_BASE_CART_BANK1 = 0x4000,
 25	GB_BASE_CART_HALFBANK1 = 0x4000,
 26	GB_BASE_CART_HALFBANK2 = 0x6000,
 27	GB_BASE_VRAM = 0x8000,
 28	GB_BASE_EXTERNAL_RAM = 0xA000,
 29	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 30	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 31	GB_BASE_OAM = 0xFE00,
 32	GB_BASE_UNUSABLE = 0xFEA0,
 33	GB_BASE_IO = 0xFF00,
 34	GB_BASE_HRAM = 0xFF80,
 35	GB_BASE_IE = 0xFFFF
 36};
 37
 38enum {
 39	GB_REGION_CART_BANK0 = 0x0,
 40	GB_REGION_CART_BANK1 = 0x4,
 41	GB_REGION_VRAM = 0x8,
 42	GB_REGION_EXTERNAL_RAM = 0xA,
 43	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 44	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 45	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 46	GB_REGION_OTHER = 0xF,
 47};
 48
 49enum {
 50	GB_SIZE_CART_BANK0 = 0x4000,
 51	GB_SIZE_CART_HALFBANK = 0x2000,
 52	GB_SIZE_CART_MAX = 0x800000,
 53	GB_SIZE_VRAM = 0x4000,
 54	GB_SIZE_VRAM_BANK0 = 0x2000,
 55	GB_SIZE_EXTERNAL_RAM = 0x2000,
 56	GB_SIZE_WORKING_RAM = 0x8000,
 57	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 58	GB_SIZE_OAM = 0xA0,
 59	GB_SIZE_IO = 0x80,
 60	GB_SIZE_HRAM = 0x7F,
 61};
 62
 63enum {
 64	GB_SRAM_DIRT_NEW = 1,
 65	GB_SRAM_DIRT_SEEN = 2
 66};
 67
 68struct GBMemory;
 69typedef void (*GBMemoryBankControllerWrite)(struct GB*, uint16_t address, uint8_t value);
 70typedef uint8_t (*GBMemoryBankControllerRead)(struct GBMemory*, uint16_t address);
 71
 72DECL_BITFIELD(GBMBC7Field, uint8_t);
 73DECL_BIT(GBMBC7Field, CS, 7);
 74DECL_BIT(GBMBC7Field, CLK, 6);
 75DECL_BIT(GBMBC7Field, DI, 1);
 76DECL_BIT(GBMBC7Field, DO, 0);
 77
 78enum GBMBC7MachineState {
 79	GBMBC7_STATE_IDLE = 0,
 80	GBMBC7_STATE_READ_COMMAND = 1,
 81	GBMBC7_STATE_DO = 2,
 82
 83	GBMBC7_STATE_EEPROM_EWDS = 0x10,
 84	GBMBC7_STATE_EEPROM_WRAL = 0x11,
 85	GBMBC7_STATE_EEPROM_ERAL = 0x12,
 86	GBMBC7_STATE_EEPROM_EWEN = 0x13,
 87	GBMBC7_STATE_EEPROM_WRITE = 0x14,
 88	GBMBC7_STATE_EEPROM_READ = 0x18,
 89	GBMBC7_STATE_EEPROM_ERASE = 0x1C,
 90};
 91
 92enum GBTAMA5Register {
 93	GBTAMA5_BANK_LO = 0x0,
 94	GBTAMA5_BANK_HI = 0x1,
 95	GBTAMA5_WRITE_LO = 0x4,
 96	GBTAMA5_WRITE_HI = 0x5,
 97	GBTAMA5_CS = 0x6,
 98	GBTAMA5_ADDR_LO = 0x7,
 99	GBTAMA5_MAX = 0x8,
100	GBTAMA5_ACTIVE = 0xA,
101	GBTAMA5_READ_LO = 0xC,
102	GBTAMA5_READ_HI = 0xD,
103};
104
105struct GBMBC1State {
106	int mode;
107	int multicartStride;
108};
109
110struct GBMBC6State {
111	int currentBank1;
112	uint8_t* romBank1;
113};
114
115struct GBMBC7State {
116	enum GBMBC7MachineState state;
117	uint16_t sr;
118	uint8_t address;
119	bool writable;
120	int srBits;
121	uint8_t access;
122	uint8_t latch;
123	GBMBC7Field eeprom;
124};
125
126struct GBPocketCamState {
127	bool registersActive;
128	uint8_t registers[0x36];
129};
130
131struct GBTAMA5State {
132	uint8_t reg;
133	uint8_t registers[GBTAMA5_MAX];
134};
135
136union GBMBCState {
137	struct GBMBC1State mbc1;
138	struct GBMBC6State mbc6;
139	struct GBMBC7State mbc7;
140	struct GBPocketCamState pocketCam;
141	struct GBTAMA5State tama5;
142};
143
144struct mRotationSource;
145struct GBMemory {
146	uint8_t* rom;
147	uint8_t* romBase;
148	uint8_t* romBank;
149	enum GBMemoryBankControllerType mbcType;
150	GBMemoryBankControllerWrite mbcWrite;
151	GBMemoryBankControllerRead mbcRead;
152	union GBMBCState mbcState;
153	int currentBank;
154
155	uint8_t* wram;
156	uint8_t* wramBank;
157	int wramCurrentBank;
158
159	bool sramAccess;
160	uint8_t* sram;
161	uint8_t* sramBank;
162	int sramCurrentBank;
163
164	uint8_t io[GB_SIZE_IO];
165	bool ime;
166	uint8_t ie;
167
168	uint8_t hram[GB_SIZE_HRAM];
169
170	uint16_t dmaSource;
171	uint16_t dmaDest;
172	int dmaRemaining;
173
174	uint16_t hdmaSource;
175	uint16_t hdmaDest;
176	int hdmaRemaining;
177	bool isHdma;
178
179	struct mTimingEvent dmaEvent;
180	struct mTimingEvent hdmaEvent;
181
182	size_t romSize;
183
184	bool rtcAccess;
185	int activeRtcReg;
186	bool rtcLatched;
187	uint8_t rtcRegs[5];
188	time_t rtcLastLatch;
189	struct mRTCSource* rtc;
190	struct mRotationSource* rotation;
191	struct mRumble* rumble;
192	struct mImageSource* cam;
193};
194
195struct LR35902Core;
196void GBMemoryInit(struct GB* gb);
197void GBMemoryDeinit(struct GB* gb);
198
199void GBMemoryReset(struct GB* gb);
200void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
201
202uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
203void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
204
205int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address);
206
207uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
208
209void GBMemoryDMA(struct GB* gb, uint16_t base);
210uint8_t GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
211
212void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
213
214struct GBSerializedState;
215void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
216void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
217
218CXX_GUARD_END
219
220#endif