src/arm/decoder-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "decoder.h"
7
8#include "decoder-inlines.h"
9#include "emitter-arm.h"
10#include "isa-inlines.h"
11
12#define ADDR_MODE_1_SHIFT(OP) \
13 info->op3.reg = opcode & 0x0000000F; \
14 info->op3.shifterOp = ARM_SHIFT_ ## OP; \
15 info->operandFormat |= ARM_OPERAND_REGISTER_3; \
16 if (opcode & 0x00000010) { \
17 info->op3.shifterReg = (opcode >> 8) & 0xF; \
18 ++info->iCycles; \
19 info->operandFormat |= ARM_OPERAND_SHIFT_REGISTER_3; \
20 } else { \
21 info->op3.shifterImm = (opcode >> 7) & 0x1F; \
22 info->operandFormat |= ARM_OPERAND_SHIFT_IMMEDIATE_3; \
23 }
24
25#define ADDR_MODE_1_LSL \
26 ADDR_MODE_1_SHIFT(LSL) \
27 if (!info->op3.shifterImm) { \
28 info->operandFormat &= ~ARM_OPERAND_SHIFT_IMMEDIATE_3; \
29 info->op3.shifterOp = ARM_SHIFT_NONE; \
30 }
31
32#define ADDR_MODE_1_LSR ADDR_MODE_1_SHIFT(LSR)
33#define ADDR_MODE_1_ASR ADDR_MODE_1_SHIFT(ASR)
34#define ADDR_MODE_1_ROR \
35 ADDR_MODE_1_SHIFT(ROR) \
36 if (!info->op3.shifterImm) { \
37 info->op3.shifterOp = ARM_SHIFT_RRX; \
38 }
39
40#define ADDR_MODE_1_IMM \
41 int rotate = (opcode & 0x00000F00) >> 7; \
42 int immediate = opcode & 0x000000FF; \
43 info->op3.immediate = ROR(immediate, rotate); \
44 info->operandFormat |= ARM_OPERAND_IMMEDIATE_3;
45
46#define ADDR_MODE_2_SHIFT(OP) \
47 info->memory.format |= ARM_MEMORY_REGISTER_OFFSET | ARM_MEMORY_SHIFTED_OFFSET; \
48 info->memory.offset.shifterOp = ARM_SHIFT_ ## OP; \
49 info->memory.offset.shifterImm = (opcode >> 7) & 0x1F; \
50 info->memory.offset.reg = opcode & 0x0000000F;
51
52#define ADDR_MODE_2_LSL \
53 ADDR_MODE_2_SHIFT(LSL) \
54 if (!info->memory.offset.shifterImm) { \
55 info->memory.format &= ~ARM_MEMORY_SHIFTED_OFFSET; \
56 info->memory.offset.shifterOp = ARM_SHIFT_NONE; \
57 }
58
59#define ADDR_MODE_2_LSR ADDR_MODE_2_SHIFT(LSR) \
60 if (!info->memory.offset.shifterImm) { \
61 info->memory.offset.shifterImm = 32; \
62 }
63
64#define ADDR_MODE_2_ASR ADDR_MODE_2_SHIFT(ASR) \
65 if (!info->memory.offset.shifterImm) { \
66 info->memory.offset.shifterImm = 32; \
67 }
68
69#define ADDR_MODE_2_ROR \
70 ADDR_MODE_2_SHIFT(ROR) \
71 if (!info->memory.offset.shifterImm) { \
72 info->memory.offset.shifterOp = ARM_SHIFT_RRX; \
73 }
74
75#define ADDR_MODE_2_IMM \
76 info->memory.format |= ARM_MEMORY_IMMEDIATE_OFFSET; \
77 info->memory.offset.immediate = opcode & 0x00000FFF;
78
79#define ADDR_MODE_3_REG \
80 info->memory.format |= ARM_MEMORY_REGISTER_OFFSET; \
81 info->memory.offset.reg = opcode & 0x0000000F;
82
83#define ADDR_MODE_3_IMM \
84 info->memory.format |= ARM_MEMORY_IMMEDIATE_OFFSET; \
85 info->memory.offset.immediate = (opcode & 0x0000000F) | ((opcode & 0x00000F00) >> 4);
86
87#define DEFINE_DECODER_ARM(NAME, MNEMONIC, BODY) \
88 static void _ARMDecode ## NAME (uint32_t opcode, struct ARMInstructionInfo* info) { \
89 UNUSED(opcode); \
90 info->mnemonic = ARM_MN_ ## MNEMONIC; \
91 BODY; \
92 }
93
94#define DEFINE_ALU_DECODER_EX_ARM(NAME, MNEMONIC, S, SHIFTER, OTHER_AFFECTED, SKIPPED) \
95 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
96 info->op1.reg = (opcode >> 12) & 0xF; \
97 info->op2.reg = (opcode >> 16) & 0xF; \
98 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
99 OTHER_AFFECTED | \
100 ARM_OPERAND_REGISTER_2; \
101 info->affectsCPSR = S; \
102 SHIFTER; \
103 if (SKIPPED == 1) { \
104 info->op1 = info->op2; \
105 info->op2 = info->op3; \
106 info->operandFormat >>= 8; \
107 } else if (SKIPPED == 2) { \
108 info->op2 = info->op3; \
109 info->operandFormat |= info->operandFormat >> 8; \
110 info->operandFormat &= ~ARM_OPERAND_3; \
111 } \
112 if (info->op1.reg == ARM_PC) { \
113 info->branchType = ARM_BRANCH_INDIRECT; \
114 })
115
116#define DEFINE_ALU_DECODER_ARM(NAME, SKIPPED) \
117 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 0, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
118 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
119 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 0, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
120 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
121 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 0, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
122 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
123 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 0, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
124 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
125 DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 0, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED) \
126 DEFINE_ALU_DECODER_EX_ARM(NAME ## SI, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED)
127
128#define DEFINE_ALU_DECODER_S_ONLY_ARM(NAME) \
129 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_NONE, 1) \
130 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_NONE, 1) \
131 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_NONE, 1) \
132 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_NONE, 1) \
133 DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_NONE, 1)
134
135#define DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S, OTHER_AFFECTED) \
136 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
137 info->op1.reg = (opcode >> 16) & 0xF; \
138 info->op2.reg = opcode & 0xF; \
139 info->op3.reg = (opcode >> 8) & 0xF; \
140 info->op4.reg = (opcode >> 12) & 0xF; \
141 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
142 ARM_OPERAND_AFFECTED_1 | \
143 ARM_OPERAND_REGISTER_2 | \
144 ARM_OPERAND_REGISTER_3 | \
145 OTHER_AFFECTED; \
146 info->affectsCPSR = S; \
147 if (info->op1.reg == ARM_PC) { \
148 info->branchType = ARM_BRANCH_INDIRECT; \
149 })
150
151#define DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S) \
152 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
153 info->op1.reg = (opcode >> 12) & 0xF; \
154 info->op2.reg = (opcode >> 16) & 0xF; \
155 info->op3.reg = opcode & 0xF; \
156 info->op4.reg = (opcode >> 8) & 0xF; \
157 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
158 ARM_OPERAND_AFFECTED_1 | \
159 ARM_OPERAND_REGISTER_2 | \
160 ARM_OPERAND_AFFECTED_2 | \
161 ARM_OPERAND_REGISTER_3 | \
162 ARM_OPERAND_REGISTER_4; \
163 info->affectsCPSR = S; \
164 if (info->op1.reg == ARM_PC) { \
165 info->branchType = ARM_BRANCH_INDIRECT; \
166 })
167
168#define DEFINE_MULTIPLY_DECODER_ARM(NAME, OTHER_AFFECTED) \
169 DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0, OTHER_AFFECTED) \
170 DEFINE_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1, OTHER_AFFECTED)
171
172#define DEFINE_LONG_MULTIPLY_DECODER_ARM(NAME) \
173 DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0) \
174 DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1)
175
176#define DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, ADDRESSING_MODE, ADDRESSING_DECODING, CYCLES, TYPE) \
177 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
178 info->op1.reg = (opcode >> 12) & 0xF; \
179 info->memory.baseReg = (opcode >> 16) & 0xF; \
180 info->memory.width = TYPE; \
181 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
182 ARM_OPERAND_AFFECTED_1 | /* TODO: Remove this for STR */ \
183 ARM_OPERAND_MEMORY_2; \
184 info->memory.format = ARM_MEMORY_REGISTER_BASE | ADDRESSING_MODE; \
185 ADDRESSING_DECODING; \
186 CYCLES;)
187
188#define DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE) \
189 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
190 ARM_MEMORY_POST_INCREMENT | \
191 ARM_MEMORY_WRITEBACK | \
192 ARM_MEMORY_OFFSET_SUBTRACT, \
193 ADDRESSING_MODE, CYCLES, TYPE) \
194 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
195 ARM_MEMORY_POST_INCREMENT | \
196 ARM_MEMORY_WRITEBACK, \
197 ADDRESSING_MODE, CYCLES, TYPE) \
198 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## P, MNEMONIC, \
199 ARM_MEMORY_OFFSET_SUBTRACT, \
200 ADDRESSING_MODE, CYCLES, TYPE) \
201 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PW, MNEMONIC, \
202 ARM_MEMORY_PRE_INCREMENT | \
203 ARM_MEMORY_WRITEBACK | \
204 ARM_MEMORY_OFFSET_SUBTRACT, \
205 ADDRESSING_MODE, CYCLES, TYPE) \
206 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PU, MNEMONIC, \
207 0, \
208 ADDRESSING_MODE, CYCLES, TYPE) \
209 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PUW, MNEMONIC, \
210 ARM_MEMORY_WRITEBACK, \
211 ADDRESSING_MODE, CYCLES, TYPE)
212
213#define DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
214 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE) \
215 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE) \
216 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE) \
217 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE) \
218 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE)
219
220#define DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
221 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDR_MODE_3_REG, CYCLES, TYPE) \
222 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_3_IMM, CYCLES, TYPE)
223
224#define DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE) \
225 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
226 ARM_MEMORY_POST_INCREMENT | \
227 ARM_MEMORY_WRITEBACK | \
228 ARM_MEMORY_OFFSET_SUBTRACT, \
229 ADDRESSING_MODE, CYCLES, TYPE) \
230 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
231 ARM_MEMORY_POST_INCREMENT | \
232 ARM_MEMORY_WRITEBACK, \
233 ADDRESSING_MODE, CYCLES, TYPE)
234
235#define DEFINE_LOAD_STORE_T_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
236 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE) \
237 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE) \
238 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE) \
239 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE) \
240 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE)
241
242#define DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME, MNEMONIC, DIRECTION, WRITEBACK) \
243 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
244 info->memory.baseReg = (opcode >> 16) & 0xF; \
245 info->op1.immediate = opcode & 0x0000FFFF; \
246 if (info->op1.immediate & (1 << ARM_PC)) { \
247 info->branchType = ARM_BRANCH_INDIRECT; \
248 } \
249 info->operandFormat = ARM_OPERAND_MEMORY_1; \
250 info->memory.format = ARM_MEMORY_REGISTER_BASE | \
251 WRITEBACK | \
252 ARM_MEMORY_ ## DIRECTION;)
253
254
255#define DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(NAME) \
256 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DA, NAME, DECREMENT_AFTER, 0) \
257 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
258 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DB, NAME, DECREMENT_BEFORE, 0) \
259 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
260 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IA, NAME, INCREMENT_AFTER, 0) \
261 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
262 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IB, NAME, INCREMENT_BEFORE, 0) \
263 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
264 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDA, NAME, DECREMENT_AFTER, ARM_MEMORY_SPSR_SWAP) \
265 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP) \
266 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDB, NAME, DECREMENT_BEFORE, ARM_MEMORY_SPSR_SWAP) \
267 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP) \
268 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIA, NAME, INCREMENT_AFTER, ARM_MEMORY_SPSR_SWAP) \
269 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP) \
270 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIB, NAME, INCREMENT_BEFORE, ARM_MEMORY_SPSR_SWAP) \
271 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP)
272
273#define DEFINE_SWP_DECODER_ARM(NAME, TYPE) \
274 DEFINE_DECODER_ARM(NAME, SWP, \
275 info->memory.baseReg = (opcode >> 16) & 0xF; \
276 info->op1.reg = (opcode >> 12) & 0xF; \
277 info->op2.reg = opcode & 0xF; \
278 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
279 ARM_OPERAND_AFFECTED_1 | \
280 ARM_OPERAND_REGISTER_2 | \
281 ARM_OPERAND_MEMORY_3; \
282 info->memory.format = ARM_MEMORY_REGISTER_BASE; \
283 info->memory.width = TYPE;)
284
285DEFINE_ALU_DECODER_ARM(ADD, 0)
286DEFINE_ALU_DECODER_ARM(ADC, 0)
287DEFINE_ALU_DECODER_ARM(AND, 0)
288DEFINE_ALU_DECODER_ARM(BIC, 0)
289DEFINE_ALU_DECODER_S_ONLY_ARM(CMN)
290DEFINE_ALU_DECODER_S_ONLY_ARM(CMP)
291DEFINE_ALU_DECODER_ARM(EOR, 0)
292DEFINE_ALU_DECODER_ARM(MOV, 2)
293DEFINE_ALU_DECODER_ARM(MVN, 2)
294DEFINE_ALU_DECODER_ARM(ORR, 0)
295DEFINE_ALU_DECODER_ARM(RSB, 0)
296DEFINE_ALU_DECODER_ARM(RSC, 0)
297DEFINE_ALU_DECODER_ARM(SBC, 0)
298DEFINE_ALU_DECODER_ARM(SUB, 0)
299DEFINE_ALU_DECODER_S_ONLY_ARM(TEQ)
300DEFINE_ALU_DECODER_S_ONLY_ARM(TST)
301
302// TOOD: Estimate cycles
303DEFINE_MULTIPLY_DECODER_ARM(MLA, ARM_OPERAND_REGISTER_4)
304DEFINE_MULTIPLY_DECODER_ARM(MUL, ARM_OPERAND_NONE)
305
306DEFINE_LONG_MULTIPLY_DECODER_ARM(SMLAL)
307DEFINE_LONG_MULTIPLY_DECODER_ARM(SMULL)
308DEFINE_LONG_MULTIPLY_DECODER_ARM(UMLAL)
309DEFINE_LONG_MULTIPLY_DECODER_ARM(UMULL)
310
311// Begin load/store definitions
312
313DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDR, LDR, LOAD_CYCLES, ARM_ACCESS_WORD)
314DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDRB, LDR, LOAD_CYCLES, ARM_ACCESS_BYTE)
315DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRH, LDR, LOAD_CYCLES, ARM_ACCESS_HALFWORD)
316DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSB, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_BYTE)
317DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSH, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_HALFWORD)
318DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STR, STR, STORE_CYCLES, ARM_ACCESS_WORD)
319DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STRB, STR, STORE_CYCLES, ARM_ACCESS_BYTE)
320DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(STRH, STR, STORE_CYCLES, ARM_ACCESS_HALFWORD)
321
322DEFINE_LOAD_STORE_T_DECODER_ARM(LDRBT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_BYTE)
323DEFINE_LOAD_STORE_T_DECODER_ARM(LDRT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_WORD)
324DEFINE_LOAD_STORE_T_DECODER_ARM(STRBT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_BYTE)
325DEFINE_LOAD_STORE_T_DECODER_ARM(STRT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_WORD)
326
327DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(LDM)
328DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(STM)
329
330DEFINE_SWP_DECODER_ARM(SWP, ARM_ACCESS_WORD)
331DEFINE_SWP_DECODER_ARM(SWPB, ARM_ACCESS_BYTE)
332
333// End load/store definitions
334
335// Begin branch definitions
336
337DEFINE_DECODER_ARM(B, B,
338 int32_t offset = opcode << 8;
339 info->op1.immediate = offset >> 6;
340 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
341 info->branchType = ARM_BRANCH;)
342
343DEFINE_DECODER_ARM(BL, BL,
344 int32_t offset = opcode << 8;
345 info->op1.immediate = offset >> 6;
346 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
347 info->branchType = ARM_BRANCH_LINKED;)
348
349DEFINE_DECODER_ARM(BX, BX,
350 info->op1.reg = opcode & 0x0000000F;
351 info->operandFormat = ARM_OPERAND_REGISTER_1;
352 info->branchType = ARM_BRANCH_INDIRECT;)
353
354// End branch definitions
355
356// Begin coprocessor definitions
357
358#define DEFINE_DECODER_COPROCESSOR(NAME, FORMAT) \
359 DEFINE_DECODER_ARM(NAME, NAME, \
360 info->cp.op1 = (opcode >> 21) & 7; \
361 info->cp.op2 = (opcode >> 5) & 7; \
362 info->op1.reg = (opcode >> 12) & 0xF; \
363 info->cp.cp = (opcode >> 8) & 0xF; \
364 info->op2.reg = (opcode >> 16) & 0xF; \
365 info->op3.reg = opcode & 0xF; \
366 info->operandFormat = ARM_OPERAND_REGISTER_1 |\
367 ARM_OPERAND_COPROCESSOR_REG_2 | \
368 ARM_OPERAND_COPROCESSOR_REG_3 | \
369 (FORMAT);)
370
371DEFINE_DECODER_ARM(CDP, CDP, info->operandFormat = ARM_OPERAND_NONE;)
372DEFINE_DECODER_ARM(LDC, LDC, info->operandFormat = ARM_OPERAND_NONE;)
373DEFINE_DECODER_ARM(STC, STC, info->operandFormat = ARM_OPERAND_NONE;)
374DEFINE_DECODER_COPROCESSOR(MCR, ARM_OPERAND_AFFECTED_2 | ARM_OPERAND_AFFECTED_3)
375DEFINE_DECODER_COPROCESSOR(MRC, ARM_OPERAND_AFFECTED_1)
376
377// Begin miscellaneous definitions
378
379DEFINE_DECODER_ARM(BKPT, BKPT,
380 info->operandFormat = ARM_OPERAND_NONE;
381 info->traps = 1;) // Not strictly in ARMv4T, but here for convenience
382DEFINE_DECODER_ARM(ILL, ILL,
383 info->operandFormat = ARM_OPERAND_NONE;
384 info->traps = 1;) // Illegal opcode
385
386DEFINE_DECODER_ARM(MSR, MSR,
387 info->affectsCPSR = 1;
388 info->op1.reg = ARM_CPSR;
389 info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
390 info->op2.reg = opcode & 0x0000000F;
391 info->operandFormat = ARM_OPERAND_REGISTER_1 |
392 ARM_OPERAND_AFFECTED_1 |
393 ARM_OPERAND_REGISTER_2;)
394
395DEFINE_DECODER_ARM(MSRR, MSR,
396 info->op1.reg = ARM_SPSR;
397 info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
398 info->op2.reg = opcode & 0x0000000F;
399 info->operandFormat = ARM_OPERAND_REGISTER_1 |
400 ARM_OPERAND_AFFECTED_1 |
401 ARM_OPERAND_REGISTER_2;)
402
403DEFINE_DECODER_ARM(MRS, MRS,
404 info->affectsCPSR = 1;
405 info->op1.reg = (opcode >> 12) & 0xF;
406 info->op2.reg = ARM_CPSR;
407 info->op2.psrBits = 0;
408 info->operandFormat = ARM_OPERAND_REGISTER_1 |
409 ARM_OPERAND_AFFECTED_1 |
410 ARM_OPERAND_REGISTER_2;)
411
412DEFINE_DECODER_ARM(MRSR, MRS,
413 info->op1.reg = (opcode >> 12) & 0xF;
414 info->op2.reg = ARM_SPSR;
415 info->op2.psrBits = 0;
416 info->operandFormat = ARM_OPERAND_REGISTER_1 |
417 ARM_OPERAND_AFFECTED_1 |
418 ARM_OPERAND_REGISTER_2;)
419
420DEFINE_DECODER_ARM(MSRI, MSR,
421 int rotate = (opcode & 0x00000F00) >> 7;
422 int32_t operand = ROR(opcode & 0x000000FF, rotate);
423 info->affectsCPSR = 1;
424 info->op1.reg = ARM_CPSR;
425 info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
426 info->op2.immediate = operand;
427 info->operandFormat = ARM_OPERAND_REGISTER_1 |
428 ARM_OPERAND_AFFECTED_1 |
429 ARM_OPERAND_IMMEDIATE_2;)
430
431DEFINE_DECODER_ARM(MSRRI, MSR,
432 int rotate = (opcode & 0x00000F00) >> 7;
433 int32_t operand = ROR(opcode & 0x000000FF, rotate);
434 info->op1.reg = ARM_SPSR;
435 info->op1.psrBits = (opcode >> 16) & ARM_PSR_MASK;
436 info->op2.immediate = operand;
437 info->operandFormat = ARM_OPERAND_REGISTER_1 |
438 ARM_OPERAND_AFFECTED_1 |
439 ARM_OPERAND_IMMEDIATE_2;)
440
441DEFINE_DECODER_ARM(SWI, SWI,
442 info->op1.immediate = opcode & 0xFFFFFF;
443 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
444 info->traps = 1;)
445
446typedef void (*ARMDecoder)(uint32_t opcode, struct ARMInstructionInfo* info);
447
448static const ARMDecoder _armDecoderTable[0x1000] = {
449 DECLARE_ARM_EMITTER_BLOCK(_ARMDecode)
450};
451
452void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info) {
453 memset(info, 0, sizeof(*info));
454 info->execMode = MODE_ARM;
455 info->opcode = opcode;
456 info->branchType = ARM_BRANCH_NONE;
457 info->condition = opcode >> 28;
458 info->sInstructionCycles = 1;
459 ARMDecoder decoder = _armDecoderTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
460 decoder(opcode, info);
461}