src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-gpio.h"
4#include "gba-io.h"
5#include "gba-serialize.h"
6#include "hle-bios.h"
7#include "util/memory.h"
8
9static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
10static int GBAWaitMultiple(struct ARMCore* cpu, uint32_t startAddress, int count);
11static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
12
13static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
14static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
17static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
18static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
19static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
20
21void GBAMemoryInit(struct GBA* gba) {
22 struct ARMCore* cpu = gba->cpu;
23 cpu->memory.load32 = GBALoad32;
24 cpu->memory.load16 = GBALoad16;
25 cpu->memory.loadU16 = GBALoadU16;
26 cpu->memory.load8 = GBALoad8;
27 cpu->memory.loadU8 = GBALoadU8;
28 cpu->memory.store32 = GBAStore32;
29 cpu->memory.store16 = GBAStore16;
30 cpu->memory.store8 = GBAStore8;
31
32 gba->memory.bios = (uint32_t*) hleBios;
33 gba->memory.fullBios = 0;
34 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
35 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
36 gba->memory.rom = 0;
37 gba->memory.gpio.p = gba;
38 memset(gba->memory.io, 0, sizeof(gba->memory.io));
39 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
40 int i;
41 for (i = 0; i < 4; ++i) {
42 gba->memory.dma[i].count = 0x10000;
43 gba->memory.dma[i].nextEvent = INT_MAX;
44 }
45 gba->memory.activeDMA = -1;
46 gba->memory.nextDMA = INT_MAX;
47 gba->memory.eventDiff = 0;
48
49 if (!gba->memory.wram || !gba->memory.iwram) {
50 GBAMemoryDeinit(gba);
51 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
52 return;
53 }
54
55 for (i = 0; i < 16; ++i) {
56 gba->memory.waitstates16[i] = GBA_BASE_WAITSTATES[i];
57 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
58 gba->memory.waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
59 gba->memory.waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
60 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
61 gba->memory.waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
62 }
63 for (; i < 256; ++i) {
64 gba->memory.waitstates16[i] = 0;
65 gba->memory.waitstatesSeq16[i] = 0;
66 gba->memory.waitstatesPrefetch16[i] = 0;
67 gba->memory.waitstates32[i] = 0;
68 gba->memory.waitstatesSeq32[i] = 0;
69 gba->memory.waitstatesPrefetch32[i] = 0;
70 }
71
72 gba->memory.activeRegion = -1;
73 cpu->memory.activeRegion = 0;
74 cpu->memory.activeMask = 0;
75 cpu->memory.setActiveRegion = GBASetActiveRegion;
76 cpu->memory.activePrefetchCycles32 = 0;
77 cpu->memory.activePrefetchCycles16 = 0;
78 gba->memory.biosPrefetch = 0;
79 cpu->memory.waitMultiple = GBAWaitMultiple;
80}
81
82void GBAMemoryDeinit(struct GBA* gba) {
83 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
84 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
85 if (gba->memory.rom) {
86 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
87 }
88 GBASavedataDeinit(&gba->memory.savedata);
89}
90
91static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
92 struct GBA* gba = (struct GBA*) cpu->master;
93 struct GBAMemory* memory = &gba->memory;
94
95 int newRegion = address >> BASE_OFFSET;
96 if (newRegion == memory->activeRegion) {
97 return;
98 }
99 if (memory->activeRegion == REGION_BIOS) {
100 memory->biosPrefetch = cpu->memory.load32(cpu, cpu->currentPC + WORD_SIZE_ARM * 2, 0);
101 }
102 memory->activeRegion = newRegion;
103 cpu->memory.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
104 cpu->memory.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
105 cpu->memory.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
106 cpu->memory.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
107 switch (address & ~OFFSET_MASK) {
108 case BASE_BIOS:
109 cpu->memory.activeRegion = memory->bios;
110 cpu->memory.activeMask = SIZE_BIOS - 1;
111 break;
112 case BASE_WORKING_RAM:
113 cpu->memory.activeRegion = memory->wram;
114 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
115 break;
116 case BASE_WORKING_IRAM:
117 cpu->memory.activeRegion = memory->iwram;
118 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
119 break;
120 case BASE_CART0:
121 case BASE_CART0_EX:
122 case BASE_CART1:
123 case BASE_CART1_EX:
124 case BASE_CART2:
125 case BASE_CART2_EX:
126 cpu->memory.activeRegion = memory->rom;
127 cpu->memory.activeMask = SIZE_CART0 - 1;
128 break;
129 default:
130 cpu->memory.activeRegion = 0;
131 cpu->memory.activeMask = 0;
132 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
133 break;
134 }
135}
136
137int32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
138 struct GBA* gba = (struct GBA*) cpu->master;
139 struct GBAMemory* memory = &gba->memory;
140 uint32_t value = 0;
141 int wait = 0;
142
143 switch (address & ~OFFSET_MASK) {
144 case BASE_BIOS:
145 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
146 if (address < SIZE_BIOS) {
147 LOAD_32(value, address, memory->bios);
148 } else {
149 value = 0;
150 }
151 } else {
152 value = memory->biosPrefetch;
153 }
154 break;
155 case BASE_WORKING_RAM:
156 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
157 wait = memory->waitstates32[REGION_WORKING_RAM];
158 break;
159 case BASE_WORKING_IRAM:
160 LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
161 break;
162 case BASE_IO:
163 value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
164 break;
165 case BASE_PALETTE_RAM:
166 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
167 break;
168 case BASE_VRAM:
169 LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
170 break;
171 case BASE_OAM:
172 LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
173 break;
174 case BASE_CART0:
175 case BASE_CART0_EX:
176 case BASE_CART1:
177 case BASE_CART1_EX:
178 case BASE_CART2:
179 case BASE_CART2_EX:
180 wait = memory->waitstates32[address >> BASE_OFFSET];
181 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
182 LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom);
183 }
184 break;
185 case BASE_CART_SRAM:
186 case BASE_CART_SRAM_MIRROR:
187 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
188 break;
189 default:
190 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
191 if (cpu->executionMode == MODE_ARM) {
192 value = cpu->memory.load32(cpu, cpu->currentPC + WORD_SIZE_ARM * 2, 0);
193 } else {
194 value = cpu->memory.load16(cpu, cpu->currentPC + WORD_SIZE_THUMB * 2, 0);
195 value |= value << 16;
196 }
197 break;
198 }
199
200
201 if (cycleCounter) {
202 *cycleCounter += 2 + wait;
203 }
204 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
205 int rotate = (address & 3) << 3;
206 return (value >> rotate) | (value << (32 - rotate));
207}
208
209uint16_t GBALoadU16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
210 return GBALoad16(cpu, address, cycleCounter);
211}
212
213int16_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
214 struct GBA* gba = (struct GBA*) cpu->master;
215 struct GBAMemory* memory = &gba->memory;
216 uint16_t value = 0;
217 int wait = 0;
218
219 switch (address & ~OFFSET_MASK) {
220 case BASE_BIOS:
221 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
222 if (address < SIZE_BIOS) {
223 LOAD_16(value, address, memory->bios);
224 } else {
225 value = 0;
226 }
227 } else {
228 value = memory->biosPrefetch;
229 }
230 break;
231 case BASE_WORKING_RAM:
232 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
233 wait = memory->waitstates16[REGION_WORKING_RAM];
234 break;
235 case BASE_WORKING_IRAM:
236 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
237 break;
238 case BASE_IO:
239 value = GBAIORead(gba, address & (SIZE_IO - 1));
240 break;
241 case BASE_PALETTE_RAM:
242 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
243 break;
244 case BASE_VRAM:
245 LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
246 break;
247 case BASE_OAM:
248 LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
249 break;
250 case BASE_CART0:
251 case BASE_CART0_EX:
252 case BASE_CART1:
253 case BASE_CART1_EX:
254 case BASE_CART2:
255 wait = memory->waitstates16[address >> BASE_OFFSET];
256 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
257 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
258 }
259 break;
260 case BASE_CART2_EX:
261 wait = memory->waitstates16[address >> BASE_OFFSET];
262 if (memory->savedata.type == SAVEDATA_EEPROM) {
263 value = GBASavedataReadEEPROM(&memory->savedata);
264 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
265 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
266 }
267 break;
268 case BASE_CART_SRAM:
269 case BASE_CART_SRAM_MIRROR:
270 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
271 break;
272 default:
273 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
274 value = cpu->memory.load16(cpu, cpu->currentPC + (cpu->executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0);
275 break;
276 }
277
278 if (cycleCounter) {
279 *cycleCounter += 2 + wait;
280 }
281 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
282 int rotate = (address & 1) << 3;
283 return (value >> rotate) | (value << (16 - rotate));
284}
285
286uint8_t GBALoadU8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
287 return GBALoad8(cpu, address, cycleCounter);
288}
289
290int8_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
291 struct GBA* gba = (struct GBA*) cpu->master;
292 struct GBAMemory* memory = &gba->memory;
293 int8_t value = 0;
294 int wait = 0;
295
296 switch (address & ~OFFSET_MASK) {
297 case BASE_BIOS:
298 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
299 if (address < SIZE_BIOS) {
300 value = ((int8_t*) memory->bios)[address];
301 } else {
302 value = 0;
303 }
304 } else {
305 value = memory->biosPrefetch;
306 }
307 break;
308 case BASE_WORKING_RAM:
309 value = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
310 wait = memory->waitstates16[REGION_WORKING_RAM];
311 break;
312 case BASE_WORKING_IRAM:
313 value = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
314 break;
315 case BASE_IO:
316 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
317 break;
318 case BASE_PALETTE_RAM:
319 value = ((int8_t*) gba->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
320 break;
321 case BASE_VRAM:
322 value = ((int8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
323 break;
324 case BASE_OAM:
325 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
326 break;
327 case BASE_CART0:
328 case BASE_CART0_EX:
329 case BASE_CART1:
330 case BASE_CART1_EX:
331 case BASE_CART2:
332 case BASE_CART2_EX:
333 wait = memory->waitstates16[address >> BASE_OFFSET];
334 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
335 value = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
336 }
337 break;
338 case BASE_CART_SRAM:
339 case BASE_CART_SRAM_MIRROR:
340 wait = memory->waitstates16[address >> BASE_OFFSET];
341 if (memory->savedata.type == SAVEDATA_NONE) {
342 GBASavedataInitSRAM(&memory->savedata);
343 }
344 if (memory->savedata.type == SAVEDATA_SRAM) {
345 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
346 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
347 value = GBASavedataReadFlash(&memory->savedata, address);
348 }
349 break;
350 default:
351 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
352 value = cpu->memory.load16(cpu, cpu->currentPC + (cpu->executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0) >> ((address & 1) << 3);
353 break;
354 }
355
356 if (cycleCounter) {
357 *cycleCounter += 2 + wait;
358 }
359 return value;
360}
361
362void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
363 struct GBA* gba = (struct GBA*) cpu->master;
364 struct GBAMemory* memory = &gba->memory;
365 int wait = 0;
366
367 switch (address & ~OFFSET_MASK) {
368 case BASE_WORKING_RAM:
369 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
370 wait = memory->waitstates32[REGION_WORKING_RAM];
371 break;
372 case BASE_WORKING_IRAM:
373 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
374 break;
375 case BASE_IO:
376 GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
377 break;
378 case BASE_PALETTE_RAM:
379 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
380 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
381 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
382 break;
383 case BASE_VRAM:
384 if ((address & OFFSET_MASK) < SIZE_VRAM) {
385 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
386 } else if ((address & OFFSET_MASK) < 0x00020000) {
387 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
388 }
389 break;
390 case BASE_OAM:
391 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
392 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
393 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
394 break;
395 case BASE_CART0:
396 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
397 break;
398 case BASE_CART_SRAM:
399 case BASE_CART_SRAM_MIRROR:
400 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
401 break;
402 default:
403 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
404 break;
405 }
406
407 if (cycleCounter) {
408 *cycleCounter += 1 + wait;
409 }
410}
411
412void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
413 struct GBA* gba = (struct GBA*) cpu->master;
414 struct GBAMemory* memory = &gba->memory;
415 int wait = 0;
416
417 switch (address & ~OFFSET_MASK) {
418 case BASE_WORKING_RAM:
419 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
420 wait = memory->waitstates16[REGION_WORKING_RAM];
421 break;
422 case BASE_WORKING_IRAM:
423 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
424 break;
425 case BASE_IO:
426 GBAIOWrite(gba, address & (SIZE_IO - 1), value);
427 break;
428 case BASE_PALETTE_RAM:
429 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
430 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
431 break;
432 case BASE_VRAM:
433 if ((address & OFFSET_MASK) < SIZE_VRAM) {
434 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
435 } else if ((address & OFFSET_MASK) < 0x00020000) {
436 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
437 }
438 break;
439 case BASE_OAM:
440 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
441 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
442 break;
443 case BASE_CART0:
444 if (IS_GPIO_REGISTER(address & 0xFFFFFF)) {
445 uint32_t reg = address & 0xFFFFFF;
446 GBAGPIOWrite(&memory->gpio, reg, value);
447 } else {
448 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
449 }
450 break;
451 case BASE_CART2_EX:
452 if (memory->savedata.type == SAVEDATA_NONE) {
453 GBASavedataInitEEPROM(&memory->savedata);
454 }
455 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
456 break;
457 case BASE_CART_SRAM:
458 case BASE_CART_SRAM_MIRROR:
459 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
460 break;
461 default:
462 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
463 break;
464 }
465
466 if (cycleCounter) {
467 *cycleCounter += 1 + wait;
468 }
469}
470
471void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
472 struct GBA* gba = (struct GBA*) cpu->master;
473 struct GBAMemory* memory = &gba->memory;
474 int wait = 0;
475
476 switch (address & ~OFFSET_MASK) {
477 case BASE_WORKING_RAM:
478 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
479 wait = memory->waitstates16[REGION_WORKING_RAM];
480 break;
481 case BASE_WORKING_IRAM:
482 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
483 break;
484 case BASE_IO:
485 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
486 break;
487 case BASE_PALETTE_RAM:
488 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
489 break;
490 case BASE_VRAM:
491 if (address >= 0x06018000) {
492 // TODO: check BG mode
493 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
494 break;
495 }
496 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
497 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
498 break;
499 case BASE_OAM:
500 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
501 break;
502 case BASE_CART0:
503 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
504 break;
505 case BASE_CART_SRAM:
506 case BASE_CART_SRAM_MIRROR:
507 if (memory->savedata.type == SAVEDATA_NONE) {
508 if (address == SAVEDATA_FLASH_BASE) {
509 GBASavedataInitFlash(&memory->savedata);
510 } else {
511 GBASavedataInitSRAM(&memory->savedata);
512 }
513 }
514 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
515 GBASavedataWriteFlash(&memory->savedata, address, value);
516 } else if (memory->savedata.type == SAVEDATA_SRAM) {
517 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
518 }
519 wait = memory->waitstates16[REGION_CART_SRAM];
520 break;
521 default:
522 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
523 break;
524 }
525
526 if (cycleCounter) {
527 *cycleCounter += 1 + wait;
528 }
529}
530
531static int GBAWaitMultiple(struct ARMCore* cpu, uint32_t startAddress, int count) {
532 struct GBA* gba = (struct GBA*) cpu->master;
533 struct GBAMemory* memory = &gba->memory;
534 int wait = 1 + memory->waitstates32[startAddress >> BASE_OFFSET];
535 wait += (1 + memory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
536 return wait;
537}
538
539void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
540 struct GBAMemory* memory = &gba->memory;
541 struct ARMCore* cpu = gba->cpu;
542 int sram = parameters & 0x0003;
543 int ws0 = (parameters & 0x000C) >> 2;
544 int ws0seq = (parameters & 0x0010) >> 4;
545 int ws1 = (parameters & 0x0060) >> 5;
546 int ws1seq = (parameters & 0x0080) >> 7;
547 int ws2 = (parameters & 0x0300) >> 8;
548 int ws2seq = (parameters & 0x0400) >> 10;
549 int prefetch = parameters & 0x4000;
550
551 memory->waitstates16[REGION_CART_SRAM] = memory->waitstates16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
552 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
553 memory->waitstates32[REGION_CART_SRAM] = memory->waitstates32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
554 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
555
556 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
557 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
558 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
559
560 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
561 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
562 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
563
564 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
565 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
566 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
567
568 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
569 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
570 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
571
572 if (!prefetch) {
573 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
574 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
575 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
576
577 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
578 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
579 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
580 } else {
581 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
582 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
583 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
584
585 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
586 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
587 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
588 }
589
590 cpu->memory.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
591 cpu->memory.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
592 cpu->memory.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
593 cpu->memory.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
594}
595
596void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
597 struct GBAMemory* memory = &gba->memory;
598 memory->dma[dma].source = address & 0xFFFFFFFE;
599}
600
601void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
602 struct GBAMemory* memory = &gba->memory;
603 memory->dma[dma].dest = address & 0xFFFFFFFE;
604}
605
606void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
607 struct GBAMemory* memory = &gba->memory;
608 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
609}
610
611uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
612 struct GBAMemory* memory = &gba->memory;
613 struct GBADMA* currentDma = &memory->dma[dma];
614 int wasEnabled = currentDma->enable;
615 currentDma->packed = control;
616
617 if (currentDma->drq) {
618 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
619 }
620
621 if (!wasEnabled && currentDma->enable) {
622 currentDma->nextSource = currentDma->source;
623 currentDma->nextDest = currentDma->dest;
624 currentDma->nextCount = currentDma->count;
625 GBAMemoryScheduleDMA(gba, dma, currentDma);
626 }
627 // If the DMA has already occurred, this value might have changed since the function started
628 return currentDma->packed;
629};
630
631void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
632 struct ARMCore* cpu = gba->cpu;
633 switch (info->timing) {
634 case DMA_TIMING_NOW:
635 info->nextEvent = cpu->cycles;
636 GBAMemoryUpdateDMAs(gba, 0);
637 break;
638 case DMA_TIMING_HBLANK:
639 // Handled implicitly
640 info->nextEvent = INT_MAX;
641 break;
642 case DMA_TIMING_VBLANK:
643 // Handled implicitly
644 info->nextEvent = INT_MAX;
645 break;
646 case DMA_TIMING_CUSTOM:
647 info->nextEvent = INT_MAX;
648 switch (number) {
649 case 0:
650 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
651 break;
652 case 1:
653 case 2:
654 GBAAudioScheduleFifoDma(&gba->audio, number, info);
655 break;
656 case 3:
657 // GBAVideoScheduleVCaptureDma(dma, info);
658 break;
659 }
660 }
661}
662
663void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
664 struct GBAMemory* memory = &gba->memory;
665 struct GBADMA* dma;
666 int i;
667 for (i = 0; i < 4; ++i) {
668 dma = &memory->dma[i];
669 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
670 dma->nextEvent = cycles;
671 }
672 }
673 GBAMemoryUpdateDMAs(gba, 0);
674}
675
676void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
677 struct GBAMemory* memory = &gba->memory;
678 struct GBADMA* dma;
679 int i;
680 for (i = 0; i < 4; ++i) {
681 dma = &memory->dma[i];
682 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
683 dma->nextEvent = cycles;
684 }
685 }
686 GBAMemoryUpdateDMAs(gba, 0);
687}
688
689int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
690 struct GBAMemory* memory = &gba->memory;
691 if (memory->nextDMA == INT_MAX) {
692 return INT_MAX;
693 }
694 memory->nextDMA -= cycles;
695 memory->eventDiff += cycles;
696 if (memory->nextDMA <= 0) {
697 struct GBADMA* dma = &memory->dma[memory->activeDMA];
698 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
699 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
700 memory->eventDiff = 0;
701 }
702 return memory->nextDMA;
703}
704
705void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
706 int i;
707 struct GBAMemory* memory = &gba->memory;
708 struct ARMCore* cpu = gba->cpu;
709 memory->activeDMA = -1;
710 memory->nextDMA = INT_MAX;
711 for (i = 3; i >= 0; --i) {
712 struct GBADMA* dma = &memory->dma[i];
713 if (dma->nextEvent != INT_MAX) {
714 dma->nextEvent -= cycles;
715 if (dma->enable) {
716 memory->activeDMA = i;
717 memory->nextDMA = dma->nextEvent;
718 }
719 }
720 }
721 if (memory->nextDMA < cpu->nextEvent) {
722 cpu->nextEvent = memory->nextDMA;
723 }
724}
725
726void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
727 struct GBAMemory* memory = &gba->memory;
728 struct ARMCore* cpu = gba->cpu;
729 uint32_t width = info->width ? 4 : 2;
730 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
731 int destOffset = DMA_OFFSET[info->dstControl] * width;
732 int32_t wordsRemaining = info->nextCount;
733 uint32_t source = info->nextSource;
734 uint32_t dest = info->nextDest;
735 uint32_t sourceRegion = source >> BASE_OFFSET;
736 uint32_t destRegion = dest >> BASE_OFFSET;
737 int32_t cycles = 0;
738
739 if (source == info->source) {
740 // TODO: support 4 cycles for ROM access
741 cycles += 2;
742 if (width == 4) {
743 cycles += memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion];
744 source &= 0xFFFFFFFC;
745 dest &= 0xFFFFFFFC;
746 } else {
747 cycles += memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion];
748 }
749 } else {
750 if (width == 4) {
751 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
752 } else {
753 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
754 }
755 }
756
757 if (width == 4) {
758 int32_t word;
759 word = cpu->memory.load32(cpu, source, 0);
760 cpu->memory.store32(cpu, dest, word, 0);
761 source += sourceOffset;
762 dest += destOffset;
763 --wordsRemaining;
764 } else {
765 uint16_t word;
766 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
767 word = GBASavedataReadEEPROM(&memory->savedata);
768 cpu->memory.store16(cpu, dest, word, 0);
769 source += sourceOffset;
770 dest += destOffset;
771 --wordsRemaining;
772 } else if (destRegion == REGION_CART2_EX) {
773 if (memory->savedata.type == SAVEDATA_NONE) {
774 GBASavedataInitEEPROM(&memory->savedata);
775 }
776 word = cpu->memory.load16(cpu, source, 0);
777 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
778 source += sourceOffset;
779 dest += destOffset;
780 --wordsRemaining;
781 } else {
782 word = cpu->memory.load16(cpu, source, 0);
783 cpu->memory.store16(cpu, dest, word, 0);
784 source += sourceOffset;
785 dest += destOffset;
786 --wordsRemaining;
787 }
788 }
789
790 if (!wordsRemaining) {
791 if (!info->repeat) {
792 info->enable = 0;
793 info->nextEvent = INT_MAX;
794
795 // Clear the enable bit in memory
796 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
797 } else {
798 info->nextCount = info->count;
799 if (info->dstControl == DMA_INCREMENT_RELOAD) {
800 info->nextDest = info->dest;
801 }
802 GBAMemoryScheduleDMA(gba, number, info);
803 }
804 if (info->doIrq) {
805 GBARaiseIRQ(gba, IRQ_DMA0 + number);
806 }
807 } else {
808 info->nextDest = dest;
809 info->nextCount = wordsRemaining;
810 }
811 info->nextSource = source;
812
813 int i;
814 for (i = 0; i < 4; ++i) {
815 if (memory->dma[i].nextEvent != INT_MAX) {
816 memory->dma[i].nextEvent += cycles;
817 }
818 }
819 cpu->cycles += cycles;
820}
821
822void GBAMemorySerialize(struct GBAMemory* memory, struct GBASerializedState* state) {
823 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
824 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
825}
826
827void GBAMemoryDeserialize(struct GBAMemory* memory, struct GBASerializedState* state) {
828 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
829 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
830}