src/gba/dma.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gba/dma.h>
7
8#include <mgba/internal/gba/gba.h>
9#include <mgba/internal/gba/io.h>
10
11static void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate);
12
13static void GBADMAService(struct GBA* gba, int number, struct GBADMA* info);
14
15static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
16
17void GBADMAInit(struct GBA* gba) {
18 gba->memory.dmaEvent.name = "GBA DMA";
19 gba->memory.dmaEvent.callback = _dmaEvent;
20 gba->memory.dmaEvent.context = gba;
21 gba->memory.dmaEvent.priority = 0x40;
22}
23
24void GBADMAReset(struct GBA* gba) {
25 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
26 int i;
27 for (i = 0; i < 4; ++i) {
28 gba->memory.dma[i].count = 0x4000;
29 }
30 gba->memory.dma[3].count = 0x10000;
31 gba->memory.activeDMA = -1;
32}
33static bool _isValidDMASAD(int dma, uint32_t address) {
34 if (dma == 0 && address >= BASE_CART0 && address < BASE_CART_SRAM) {
35 return false;
36 }
37 return address >= BASE_WORKING_RAM;
38}
39
40static bool _isValidDMADAD(int dma, uint32_t address) {
41 return dma == 3 || address < BASE_CART0;
42}
43
44uint32_t GBADMAWriteSAD(struct GBA* gba, int dma, uint32_t address) {
45 struct GBAMemory* memory = &gba->memory;
46 address &= 0x0FFFFFFE;
47 if (_isValidDMASAD(dma, address)) {
48 memory->dma[dma].source = address;
49 }
50 return memory->dma[dma].source;
51}
52
53uint32_t GBADMAWriteDAD(struct GBA* gba, int dma, uint32_t address) {
54 struct GBAMemory* memory = &gba->memory;
55 address &= 0x0FFFFFFE;
56 if (_isValidDMADAD(dma, address)) {
57 memory->dma[dma].dest = address;
58 }
59 return memory->dma[dma].dest;
60}
61
62void GBADMAWriteCNT_LO(struct GBA* gba, int dma, uint16_t count) {
63 struct GBAMemory* memory = &gba->memory;
64 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
65}
66
67uint16_t GBADMAWriteCNT_HI(struct GBA* gba, int dma, uint16_t control) {
68 struct GBAMemory* memory = &gba->memory;
69 struct GBADMA* currentDma = &memory->dma[dma];
70 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
71 if (dma < 3) {
72 control &= 0xF7E0;
73 } else {
74 control &= 0xFFE0;
75 }
76 currentDma->reg = control;
77
78 if (GBADMARegisterIsDRQ(currentDma->reg)) {
79 mLOG(GBA_MEM, STUB, "DRQ not implemented");
80 }
81
82 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
83 currentDma->nextSource = currentDma->source;
84 if (currentDma->nextSource >= BASE_CART0 && currentDma->nextSource < BASE_CART_SRAM && GBADMARegisterGetSrcControl(currentDma->reg) < 3) {
85 currentDma->reg = GBADMARegisterClearSrcControl(currentDma->reg);
86 }
87 currentDma->nextDest = currentDma->dest;
88 GBADMASchedule(gba, dma, currentDma);
89 }
90 // If the DMA has already occurred, this value might have changed since the function started
91 return currentDma->reg;
92};
93
94void GBADMASchedule(struct GBA* gba, int number, struct GBADMA* info) {
95 switch (GBADMARegisterGetTiming(info->reg)) {
96 case DMA_TIMING_NOW:
97 info->when = mTimingCurrentTime(&gba->timing) + 3; // DMAs take 3 cycles to start
98 info->nextCount = info->count;
99 break;
100 case DMA_TIMING_HBLANK:
101 case DMA_TIMING_VBLANK:
102 // Handled implicitly
103 return;
104 case DMA_TIMING_CUSTOM:
105 switch (number) {
106 case 0:
107 mLOG(GBA_MEM, WARN, "Discarding invalid DMA0 scheduling");
108 return;
109 case 1:
110 case 2:
111 GBAAudioScheduleFifoDma(&gba->audio, number, info);
112 break;
113 case 3:
114 // GBAVideoScheduleVCaptureDma(dma, info);
115 break;
116 }
117 }
118 GBADMAUpdate(gba);
119}
120
121void GBADMARunHblank(struct GBA* gba, int32_t cycles) {
122 struct GBAMemory* memory = &gba->memory;
123 struct GBADMA* dma;
124 int i;
125 for (i = 0; i < 4; ++i) {
126 dma = &memory->dma[i];
127 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK && !dma->nextCount) {
128 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
129 dma->nextCount = dma->count;
130 }
131 }
132 GBADMAUpdate(gba);
133}
134
135void GBADMARunVblank(struct GBA* gba, int32_t cycles) {
136 struct GBAMemory* memory = &gba->memory;
137 struct GBADMA* dma;
138 int i;
139 for (i = 0; i < 4; ++i) {
140 dma = &memory->dma[i];
141 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK && !dma->nextCount) {
142 dma->when = mTimingCurrentTime(&gba->timing) + 3 + cycles;
143 dma->nextCount = dma->count;
144 }
145 }
146 GBADMAUpdate(gba);
147}
148
149void _dmaEvent(struct mTiming* timing, void* context, uint32_t cyclesLate) {
150 UNUSED(timing);
151 UNUSED(cyclesLate);
152 struct GBA* gba = context;
153 struct GBAMemory* memory = &gba->memory;
154 struct GBADMA* dma = &memory->dma[memory->activeDMA];
155 if (dma->nextCount == dma->count) {
156 dma->when = mTimingCurrentTime(&gba->timing);
157 }
158 if (dma->nextCount & 0xFFFFF) {
159 GBADMAService(gba, memory->activeDMA, dma);
160 } else {
161 dma->nextCount = 0;
162 if (!GBADMARegisterIsRepeat(dma->reg) || GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_NOW) {
163 dma->reg = GBADMARegisterClearEnable(dma->reg);
164
165 // Clear the enable bit in memory
166 memory->io[(REG_DMA0CNT_HI + memory->activeDMA * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
167 }
168 if (GBADMARegisterGetDestControl(dma->reg) == DMA_INCREMENT_RELOAD) {
169 dma->nextDest = dma->dest;
170 }
171 if (GBADMARegisterIsDoIRQ(dma->reg)) {
172 GBARaiseIRQ(gba, IRQ_DMA0 + memory->activeDMA);
173 }
174 GBADMAUpdate(gba);
175 }
176}
177
178void GBADMAUpdate(struct GBA* gba) {
179 int i;
180 struct GBAMemory* memory = &gba->memory;
181 memory->activeDMA = -1;
182 uint32_t currentTime = mTimingCurrentTime(&gba->timing);
183 for (i = 0; i < 4; ++i) {
184 struct GBADMA* dma = &memory->dma[i];
185 if (GBADMARegisterIsEnable(dma->reg) && dma->nextCount) {
186 memory->activeDMA = i;
187 break;
188 }
189 }
190
191 if (memory->activeDMA >= 0) {
192 mTimingDeschedule(&gba->timing, &memory->dmaEvent);
193 mTimingSchedule(&gba->timing, &memory->dmaEvent, memory->dma[memory->activeDMA].when - currentTime);
194 } else {
195 gba->cpuBlocked = false;
196 }
197}
198
199void GBADMAService(struct GBA* gba, int number, struct GBADMA* info) {
200 struct GBAMemory* memory = &gba->memory;
201 struct ARMCore* cpu = gba->cpu;
202 uint32_t width = 2 << GBADMARegisterGetWidth(info->reg);
203 int32_t wordsRemaining = info->nextCount;
204 uint32_t source = info->nextSource;
205 uint32_t dest = info->nextDest;
206 uint32_t sourceRegion = source >> BASE_OFFSET;
207 uint32_t destRegion = dest >> BASE_OFFSET;
208 int32_t cycles = 2;
209
210 gba->cpuBlocked = true;
211 if (info->count == info->nextCount) {
212 if (sourceRegion < REGION_CART0 || destRegion < REGION_CART0) {
213 cycles += 2;
214 }
215 if (width == 4) {
216 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
217 } else {
218 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
219 }
220 source &= -width;
221 dest &= -width;
222 } else {
223 if (width == 4) {
224 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
225 } else {
226 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
227 }
228 }
229 info->when += cycles;
230
231 gba->performingDMA = 1 | (number << 1);
232 uint32_t word;
233 if (width == 4) {
234 word = cpu->memory.load32(cpu, source, 0);
235 gba->bus = word;
236 cpu->memory.store32(cpu, dest, word, 0);
237 } else {
238 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
239 word = GBASavedataReadEEPROM(&memory->savedata);
240 cpu->memory.store16(cpu, dest, word, 0);
241 } else if (destRegion == REGION_CART2_EX) {
242 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
243 mLOG(GBA_MEM, INFO, "Detected EEPROM savegame");
244 GBASavedataInitEEPROM(&memory->savedata, gba->realisticTiming);
245 }
246 word = cpu->memory.load16(cpu, source, 0);
247 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
248 } else {
249 word = cpu->memory.load16(cpu, source, 0);
250 cpu->memory.store16(cpu, dest, word, 0);
251 }
252 gba->bus = word | (word << 16);
253 }
254 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
255 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
256 source += sourceOffset;
257 dest += destOffset;
258 --wordsRemaining;
259 gba->performingDMA = 0;
260
261 info->nextCount = wordsRemaining;
262 info->nextSource = source;
263 info->nextDest = dest;
264 if (!wordsRemaining) {
265 info->nextCount |= 0x80000000;
266 }
267 GBADMAUpdate(gba);
268}