src/arm/isa-thumb.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "isa-thumb.h"
7
8#include "isa-inlines.h"
9#include "emitter-thumb.h"
10
11// Instruction definitions
12// Beware pre-processor insanity
13
14#define THUMB_ADDITION_S(M, N, D) \
15 cpu->cpsr.n = ARM_SIGN(D); \
16 cpu->cpsr.z = !(D); \
17 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
18 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
19
20#define THUMB_SUBTRACTION_S(M, N, D) \
21 cpu->cpsr.n = ARM_SIGN(D); \
22 cpu->cpsr.z = !(D); \
23 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
24 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
25
26#define THUMB_NEUTRAL_S(M, N, D) \
27 cpu->cpsr.n = ARM_SIGN(D); \
28 cpu->cpsr.z = !(D);
29
30#define THUMB_ADDITION(D, M, N) \
31 int n = N; \
32 int m = M; \
33 D = M + N; \
34 THUMB_ADDITION_S(m, n, D)
35
36#define THUMB_SUBTRACTION(D, M, N) \
37 int n = N; \
38 int m = M; \
39 D = M - N; \
40 THUMB_SUBTRACTION_S(m, n, D)
41
42#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activeSeqCycles16)
43
44#define THUMB_LOAD_POST_BODY ++currentCycles;
45
46#define THUMB_STORE_POST_BODY \
47 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
48
49#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
50 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
51 int currentCycles = THUMB_PREFETCH_CYCLES; \
52 BODY; \
53 cpu->cycles += currentCycles; \
54 }
55
56#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
57 DEFINE_INSTRUCTION_THUMB(NAME, \
58 int immediate = IMMEDIATE; \
59 int rd = opcode & 0x0007; \
60 int rm = (opcode >> 3) & 0x0007; \
61 BODY;)
62
63#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
64 COUNT_CALL_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
65
66DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
67 if (!immediate) {
68 cpu->gprs[rd] = cpu->gprs[rm];
69 } else {
70 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
71 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
72 }
73 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
74
75DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
76 if (!immediate) {
77 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
78 cpu->gprs[rd] = 0;
79 } else {
80 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
81 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
82 }
83 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
84
85DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
86 if (!immediate) {
87 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
88 if (cpu->cpsr.c) {
89 cpu->gprs[rd] = 0xFFFFFFFF;
90 } else {
91 cpu->gprs[rd] = 0;
92 }
93 } else {
94 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
95 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
96 }
97 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
98
99DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, ¤tCycles); THUMB_LOAD_POST_BODY;)
100DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.loadU8(cpu, cpu->gprs[rm] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
101DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.loadU16(cpu, cpu->gprs[rm] + immediate * 2, ¤tCycles); THUMB_LOAD_POST_BODY;)
102DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
103DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
104DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
105
106#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
107 DEFINE_INSTRUCTION_THUMB(NAME, \
108 int rm = RM; \
109 int rd = opcode & 0x0007; \
110 int rn = (opcode >> 3) & 0x0007; \
111 BODY;)
112
113#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
114 COUNT_CALL_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
115
116DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
117DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
118
119#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
120 DEFINE_INSTRUCTION_THUMB(NAME, \
121 int immediate = IMMEDIATE; \
122 int rd = opcode & 0x0007; \
123 int rn = (opcode >> 3) & 0x0007; \
124 BODY;)
125
126#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
127 COUNT_CALL_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
128
129DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
130DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
131
132#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
133 DEFINE_INSTRUCTION_THUMB(NAME, \
134 int rd = RD; \
135 int immediate = opcode & 0x00FF; \
136 BODY;)
137
138#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
139 COUNT_CALL_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
140
141DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
142DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
143DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
144DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
145
146#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
147 DEFINE_INSTRUCTION_THUMB(NAME, \
148 int rd = opcode & 0x0007; \
149 int rn = (opcode >> 3) & 0x0007; \
150 BODY;)
151
152DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
153DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
154DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
155 int rs = cpu->gprs[rn] & 0xFF;
156 if (rs) {
157 if (rs < 32) {
158 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
159 cpu->gprs[rd] <<= rs;
160 } else {
161 if (rs > 32) {
162 cpu->cpsr.c = 0;
163 } else {
164 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
165 }
166 cpu->gprs[rd] = 0;
167 }
168 }
169 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
170
171DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
172 int rs = cpu->gprs[rn] & 0xFF;
173 if (rs) {
174 if (rs < 32) {
175 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
176 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
177 } else {
178 if (rs > 32) {
179 cpu->cpsr.c = 0;
180 } else {
181 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
182 }
183 cpu->gprs[rd] = 0;
184 }
185 }
186 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
187
188DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
189 int rs = cpu->gprs[rn] & 0xFF;
190 if (rs) {
191 if (rs < 32) {
192 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
193 cpu->gprs[rd] >>= rs;
194 } else {
195 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
196 if (cpu->cpsr.c) {
197 cpu->gprs[rd] = 0xFFFFFFFF;
198 } else {
199 cpu->gprs[rd] = 0;
200 }
201 }
202 }
203 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
204
205DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
206 int n = cpu->gprs[rn];
207 int d = cpu->gprs[rd];
208 cpu->gprs[rd] = d + n + cpu->cpsr.c;
209 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
210
211DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
212 int n = cpu->gprs[rn] + !cpu->cpsr.c;
213 int d = cpu->gprs[rd];
214 cpu->gprs[rd] = d - n;
215 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
216DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
217 int rs = cpu->gprs[rn] & 0xFF;
218 if (rs) {
219 int r4 = rs & 0x1F;
220 if (r4 > 0) {
221 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
222 cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4);
223 } else {
224 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
225 }
226 }
227 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
228DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
229DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
230DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
231DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
232DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
233DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rn]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
234DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
235DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
236
237#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
238 DEFINE_INSTRUCTION_THUMB(NAME, \
239 int rd = (opcode & 0x0007) | H1; \
240 int rm = ((opcode >> 3) & 0x0007) | H2; \
241 BODY;)
242
243#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
244 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
245 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
246 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
247 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
248
249DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
250 cpu->gprs[rd] += cpu->gprs[rm];
251 if (rd == ARM_PC) {
252 THUMB_WRITE_PC;
253 })
254
255DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
256DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
257 cpu->gprs[rd] = cpu->gprs[rm];
258 if (rd == ARM_PC) {
259 THUMB_WRITE_PC;
260 })
261
262#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
263 DEFINE_INSTRUCTION_THUMB(NAME, \
264 int rd = RD; \
265 int immediate = (opcode & 0x00FF) << 2; \
266 BODY;)
267
268#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
269 COUNT_CALL_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
270
271DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
272DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
273DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
274
275DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
276DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
277
278#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
279 DEFINE_INSTRUCTION_THUMB(NAME, \
280 int rm = RM; \
281 int rd = opcode & 0x0007; \
282 int rn = (opcode >> 3) & 0x0007; \
283 BODY;)
284
285#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
286 COUNT_CALL_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
287
288DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
289DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.loadU8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
290DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.loadU16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
291DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
292DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
293DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
294DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
295DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
296
297#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
298 DEFINE_INSTRUCTION_THUMB(NAME, \
299 int rn = RN; \
300 UNUSED(rn); \
301 int rs = opcode & 0xFF; \
302 int32_t address = cpu->gprs[RN]; \
303 PRE_BODY; \
304 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
305 WRITEBACK;)
306
307#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, LS, DIRECTION, WRITEBACK) \
308 COUNT_CALL_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, LS, DIRECTION, , WRITEBACK)
309
310DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
311 load,
312 IA,
313 THUMB_LOAD_POST_BODY;
314 if (!((1 << rn) & rs)) {
315 cpu->gprs[rn] = address;
316 })
317
318DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
319 store,
320 IA,
321 THUMB_STORE_POST_BODY;
322 cpu->gprs[rn] = address;)
323
324#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
325 DEFINE_INSTRUCTION_THUMB(B ## COND, \
326 if (ARM_COND_ ## COND) { \
327 int8_t immediate = opcode; \
328 cpu->gprs[ARM_PC] += immediate << 1; \
329 THUMB_WRITE_PC; \
330 })
331
332DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
333DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
334DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
335DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
336DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
337DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
338DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
339DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
340DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
341DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
342DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
343DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
344DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
345DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
346
347DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
348DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
349
350DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
351 ARM_SP,
352 load,
353 IA,
354 ,
355 THUMB_LOAD_POST_BODY;
356 cpu->gprs[ARM_SP] = address)
357
358DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
359 ARM_SP,
360 load,
361 IA,
362 rs |= 1 << ARM_PC,
363 THUMB_LOAD_POST_BODY;
364 cpu->gprs[ARM_SP] = address;
365 THUMB_WRITE_PC;)
366
367DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
368 ARM_SP,
369 store,
370 DB,
371 ,
372 THUMB_STORE_POST_BODY;
373 cpu->gprs[ARM_SP] = address)
374
375DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
376 ARM_SP,
377 store,
378 DB,
379 rs |= 1 << ARM_LR,
380 THUMB_STORE_POST_BODY;
381 cpu->gprs[ARM_SP] = address)
382
383DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
384DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
385DEFINE_INSTRUCTION_THUMB(B,
386 int16_t immediate = (opcode & 0x07FF) << 5;
387 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
388 THUMB_WRITE_PC;)
389
390DEFINE_INSTRUCTION_THUMB(BL1,
391 int16_t immediate = (opcode & 0x07FF) << 5;
392 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
393
394DEFINE_INSTRUCTION_THUMB(BL2,
395 uint16_t immediate = (opcode & 0x07FF) << 1;
396 uint32_t pc = cpu->gprs[ARM_PC];
397 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
398 cpu->gprs[ARM_LR] = pc - 1;
399 THUMB_WRITE_PC;)
400
401DEFINE_INSTRUCTION_THUMB(BX,
402 int rm = (opcode >> 3) & 0xF;
403 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
404 int misalign = 0;
405 if (rm == ARM_PC) {
406 misalign = cpu->gprs[rm] & 0x00000002;
407 }
408 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
409 if (cpu->executionMode == MODE_THUMB) {
410 THUMB_WRITE_PC;
411 } else {
412 ARM_WRITE_PC;
413 })
414
415DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
416
417const ThumbInstruction _thumbTable[0x400] = {
418 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
419};